This patch supports following MVE ACLE intrinsics with quaternary operands.

vabdq_m_s8, vabdq_m_s32, vabdq_m_s16, vabdq_m_u8, vabdq_m_u32, vabdq_m_u16, vaddq_m_n_s8, vaddq_m_n_s32, vaddq_m_n_s16, vaddq_m_n_u8, vaddq_m_n_u32, vaddq_m_n_u16, vaddq_m_s8, vaddq_m_s32, vaddq_m_s16, vaddq_m_u8, vaddq_m_u32, vaddq_m_u16, vandq_m_s8, vandq_m_s32, vandq_m_s16, vandq_m_u8, vandq_m_u32, vandq_m_u16, vbicq_m_s8, vbicq_m_s32, vbicq_m_s16, vbicq_m_u8, vbicq_m_u32, vbicq_m_u16, vbrsrq_m_n_s8, vbrsrq_m_n_s32, vbrsrq_m_n_s16, vbrsrq_m_n_u8, vbrsrq_m_n_u32, vbrsrq_m_n_u16, vcaddq_rot270_m_s8, vcaddq_rot270_m_s32, vcaddq_rot270_m_s16, vcaddq_rot270_m_u8, vcaddq_rot270_m_u32, vcaddq_rot270_m_u16, vcaddq_rot90_m_s8, vcaddq_rot90_m_s32, vcaddq_rot90_m_s16, vcaddq_rot90_m_u8, vcaddq_rot90_m_u32, vcaddq_rot90_m_u16, veorq_m_s8, veorq_m_s32, veorq_m_s16, veorq_m_u8, veorq_m_u32, veorq_m_u16, vhaddq_m_n_s8, vhaddq_m_n_s32, vhaddq_m_n_s16, vhaddq_m_n_u8, vhaddq_m_n_u32, vhaddq_m_n_u16, vhaddq_m_s8, vhaddq_m_s32, vhaddq_m_s16, vhaddq_m_u8, vhaddq_m_u32, vhaddq_m_u16, vhcaddq_rot270_m_s8, vhcaddq_rot270_m_s32, vhcaddq_rot270_m_s16, vhcaddq_rot90_m_s8, vhcaddq_rot90_m_s32, vhcaddq_rot90_m_s16, vhsubq_m_n_s8, vhsubq_m_n_s32, vhsubq_m_n_s16, vhsubq_m_n_u8, vhsubq_m_n_u32, vhsubq_m_n_u16, vhsubq_m_s8, vhsubq_m_s32, vhsubq_m_s16, vhsubq_m_u8, vhsubq_m_u32, vhsubq_m_u16, vmaxq_m_s8, vmaxq_m_s32, vmaxq_m_s16, vmaxq_m_u8, vmaxq_m_u32, vmaxq_m_u16, vminq_m_s8, vminq_m_s32, vminq_m_s16, vminq_m_u8, vminq_m_u32, vminq_m_u16, vmladavaq_p_s8, vmladavaq_p_s32, vmladavaq_p_s16, vmladavaq_p_u8, vmladavaq_p_u32, vmladavaq_p_u16, vmladavaxq_p_s8, vmladavaxq_p_s32, vmladavaxq_p_s16, vmlaq_m_n_s8, vmlaq_m_n_s32, vmlaq_m_n_s16, vmlaq_m_n_u8, vmlaq_m_n_u32, vmlaq_m_n_u16, vmlasq_m_n_s8, vmlasq_m_n_s32, vmlasq_m_n_s16, vmlasq_m_n_u8, vmlasq_m_n_u32, vmlasq_m_n_u16, vmlsdavaq_p_s8, vmlsdavaq_p_s32, vmlsdavaq_p_s16, vmlsdavaxq_p_s8, vmlsdavaxq_p_s32, vmlsdavaxq_p_s16, vmulhq_m_s8, vmulhq_m_s32, vmulhq_m_s16, vmulhq_m_u8, vmulhq_m_u32, vmulhq_m_u16, vmullbq_int_m_s8, vmullbq_int_m_s32, vmullbq_int_m_s16, vmullbq_int_m_u8, vmullbq_int_m_u32, vmullbq_int_m_u16, vmulltq_int_m_s8, vmulltq_int_m_s32, vmulltq_int_m_s16, vmulltq_int_m_u8, vmulltq_int_m_u32, vmulltq_int_m_u16, vmulq_m_n_s8, vmulq_m_n_s32, vmulq_m_n_s16, vmulq_m_n_u8, vmulq_m_n_u32, vmulq_m_n_u16, vmulq_m_s8, vmulq_m_s32, vmulq_m_s16, vmulq_m_u8, vmulq_m_u32, vmulq_m_u16, vornq_m_s8, vornq_m_s32, vornq_m_s16, vornq_m_u8, vornq_m_u32, vornq_m_u16, vorrq_m_s8, vorrq_m_s32, vorrq_m_s16, vorrq_m_u8, vorrq_m_u32, vorrq_m_u16, vqaddq_m_n_s8, vqaddq_m_n_s32, vqaddq_m_n_s16, vqaddq_m_n_u8, vqaddq_m_n_u32, vqaddq_m_n_u16, vqaddq_m_s8, vqaddq_m_s32, vqaddq_m_s16, vqaddq_m_u8, vqaddq_m_u32, vqaddq_m_u16, vqdmladhq_m_s8, vqdmladhq_m_s32, vqdmladhq_m_s16, vqdmladhxq_m_s8, vqdmladhxq_m_s32, vqdmladhxq_m_s16, vqdmlahq_m_n_s8, vqdmlahq_m_n_s32, vqdmlahq_m_n_s16, vqdmlahq_m_n_u8, vqdmlahq_m_n_u32, vqdmlahq_m_n_u16, vqdmlsdhq_m_s8, vqdmlsdhq_m_s32, vqdmlsdhq_m_s16, vqdmlsdhxq_m_s8, vqdmlsdhxq_m_s32, vqdmlsdhxq_m_s16, vqdmulhq_m_n_s8, vqdmulhq_m_n_s32, vqdmulhq_m_n_s16, vqdmulhq_m_s8, vqdmulhq_m_s32, vqdmulhq_m_s16, vqrdmladhq_m_s8, vqrdmladhq_m_s32, vqrdmladhq_m_s16, vqrdmladhxq_m_s8, vqrdmladhxq_m_s32, vqrdmladhxq_m_s16, vqrdmlahq_m_n_s8, vqrdmlahq_m_n_s32, vqrdmlahq_m_n_s16, vqrdmlahq_m_n_u8, vqrdmlahq_m_n_u32, vqrdmlahq_m_n_u16, vqrdmlashq_m_n_s8, vqrdmlashq_m_n_s32, vqrdmlashq_m_n_s16, vqrdmlashq_m_n_u8, vqrdmlashq_m_n_u32, vqrdmlashq_m_n_u16, vqrdmlsdhq_m_s8, vqrdmlsdhq_m_s32, vqrdmlsdhq_m_s16, vqrdmlsdhxq_m_s8, vqrdmlsdhxq_m_s32, vqrdmlsdhxq_m_s16, vqrdmulhq_m_n_s8, vqrdmulhq_m_n_s32, vqrdmulhq_m_n_s16, vqrdmulhq_m_s8, vqrdmulhq_m_s32, vqrdmulhq_m_s16, vqrshlq_m_s8, vqrshlq_m_s32, vqrshlq_m_s16, vqrshlq_m_u8, vqrshlq_m_u32, vqrshlq_m_u16, vqshlq_m_n_s8, vqshlq_m_n_s32, vqshlq_m_n_s16, vqshlq_m_n_u8, vqshlq_m_n_u32, vqshlq_m_n_u16, vqshlq_m_s8, vqshlq_m_s32, vqshlq_m_s16, vqshlq_m_u8, vqshlq_m_u32, vqshlq_m_u16, vqsubq_m_n_s8, vqsubq_m_n_s32, vqsubq_m_n_s16, vqsubq_m_n_u8, vqsubq_m_n_u32, vqsubq_m_n_u16, vqsubq_m_s8, vqsubq_m_s32, vqsubq_m_s16, vqsubq_m_u8, vqsubq_m_u32, vqsubq_m_u16, vrhaddq_m_s8, vrhaddq_m_s32, vrhaddq_m_s16, vrhaddq_m_u8, vrhaddq_m_u32, vrhaddq_m_u16, vrmulhq_m_s8, vrmulhq_m_s32, vrmulhq_m_s16, vrmulhq_m_u8, vrmulhq_m_u32, vrmulhq_m_u16, vrshlq_m_s8, vrshlq_m_s32, vrshlq_m_s16, vrshlq_m_u8, vrshlq_m_u32, vrshlq_m_u16, vrshrq_m_n_s8, vrshrq_m_n_s32, vrshrq_m_n_s16, vrshrq_m_n_u8, vrshrq_m_n_u32, vrshrq_m_n_u16, vshlq_m_n_s8, vshlq_m_n_s32, vshlq_m_n_s16, vshlq_m_n_u8, vshlq_m_n_u32, vshlq_m_n_u16, vshrq_m_n_s8, vshrq_m_n_s32, vshrq_m_n_s16, vshrq_m_n_u8, vshrq_m_n_u32, vshrq_m_n_u16, vsliq_m_n_s8, vsliq_m_n_s32, vsliq_m_n_s16, vsliq_m_n_u8, vsliq_m_n_u32, vsliq_m_n_u16, vsubq_m_n_s8, vsubq_m_n_s32, vsubq_m_n_s16, vsubq_m_n_u8, vsubq_m_n_u32, vsubq_m_n_u16.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vabdq_m_s8): Define macro.
	(vabdq_m_s32): Likewise.
	(vabdq_m_s16): Likewise.
	(vabdq_m_u8): Likewise.
	(vabdq_m_u32): Likewise.
	(vabdq_m_u16): Likewise.
	(vaddq_m_n_s8): Likewise.
	(vaddq_m_n_s32): Likewise.
	(vaddq_m_n_s16): Likewise.
	(vaddq_m_n_u8): Likewise.
	(vaddq_m_n_u32): Likewise.
	(vaddq_m_n_u16): Likewise.
	(vaddq_m_s8): Likewise.
	(vaddq_m_s32): Likewise.
	(vaddq_m_s16): Likewise.
	(vaddq_m_u8): Likewise.
	(vaddq_m_u32): Likewise.
	(vaddq_m_u16): Likewise.
	(vandq_m_s8): Likewise.
	(vandq_m_s32): Likewise.
	(vandq_m_s16): Likewise.
	(vandq_m_u8): Likewise.
	(vandq_m_u32): Likewise.
	(vandq_m_u16): Likewise.
	(vbicq_m_s8): Likewise.
	(vbicq_m_s32): Likewise.
	(vbicq_m_s16): Likewise.
	(vbicq_m_u8): Likewise.
	(vbicq_m_u32): Likewise.
	(vbicq_m_u16): Likewise.
	(vbrsrq_m_n_s8): Likewise.
	(vbrsrq_m_n_s32): Likewise.
	(vbrsrq_m_n_s16): Likewise.
	(vbrsrq_m_n_u8): Likewise.
	(vbrsrq_m_n_u32): Likewise.
	(vbrsrq_m_n_u16): Likewise.
	(vcaddq_rot270_m_s8): Likewise.
	(vcaddq_rot270_m_s32): Likewise.
	(vcaddq_rot270_m_s16): Likewise.
	(vcaddq_rot270_m_u8): Likewise.
	(vcaddq_rot270_m_u32): Likewise.
	(vcaddq_rot270_m_u16): Likewise.
	(vcaddq_rot90_m_s8): Likewise.
	(vcaddq_rot90_m_s32): Likewise.
	(vcaddq_rot90_m_s16): Likewise.
	(vcaddq_rot90_m_u8): Likewise.
	(vcaddq_rot90_m_u32): Likewise.
	(vcaddq_rot90_m_u16): Likewise.
	(veorq_m_s8): Likewise.
	(veorq_m_s32): Likewise.
	(veorq_m_s16): Likewise.
	(veorq_m_u8): Likewise.
	(veorq_m_u32): Likewise.
	(veorq_m_u16): Likewise.
	(vhaddq_m_n_s8): Likewise.
	(vhaddq_m_n_s32): Likewise.
	(vhaddq_m_n_s16): Likewise.
	(vhaddq_m_n_u8): Likewise.
	(vhaddq_m_n_u32): Likewise.
	(vhaddq_m_n_u16): Likewise.
	(vhaddq_m_s8): Likewise.
	(vhaddq_m_s32): Likewise.
	(vhaddq_m_s16): Likewise.
	(vhaddq_m_u8): Likewise.
	(vhaddq_m_u32): Likewise.
	(vhaddq_m_u16): Likewise.
	(vhcaddq_rot270_m_s8): Likewise.
	(vhcaddq_rot270_m_s32): Likewise.
	(vhcaddq_rot270_m_s16): Likewise.
	(vhcaddq_rot90_m_s8): Likewise.
	(vhcaddq_rot90_m_s32): Likewise.
	(vhcaddq_rot90_m_s16): Likewise.
	(vhsubq_m_n_s8): Likewise.
	(vhsubq_m_n_s32): Likewise.
	(vhsubq_m_n_s16): Likewise.
	(vhsubq_m_n_u8): Likewise.
	(vhsubq_m_n_u32): Likewise.
	(vhsubq_m_n_u16): Likewise.
	(vhsubq_m_s8): Likewise.
	(vhsubq_m_s32): Likewise.
	(vhsubq_m_s16): Likewise.
	(vhsubq_m_u8): Likewise.
	(vhsubq_m_u32): Likewise.
	(vhsubq_m_u16): Likewise.
	(vmaxq_m_s8): Likewise.
	(vmaxq_m_s32): Likewise.
	(vmaxq_m_s16): Likewise.
	(vmaxq_m_u8): Likewise.
	(vmaxq_m_u32): Likewise.
	(vmaxq_m_u16): Likewise.
	(vminq_m_s8): Likewise.
	(vminq_m_s32): Likewise.
	(vminq_m_s16): Likewise.
	(vminq_m_u8): Likewise.
	(vminq_m_u32): Likewise.
	(vminq_m_u16): Likewise.
	(vmladavaq_p_s8): Likewise.
	(vmladavaq_p_s32): Likewise.
	(vmladavaq_p_s16): Likewise.
	(vmladavaq_p_u8): Likewise.
	(vmladavaq_p_u32): Likewise.
	(vmladavaq_p_u16): Likewise.
	(vmladavaxq_p_s8): Likewise.
	(vmladavaxq_p_s32): Likewise.
	(vmladavaxq_p_s16): Likewise.
	(vmlaq_m_n_s8): Likewise.
	(vmlaq_m_n_s32): Likewise.
	(vmlaq_m_n_s16): Likewise.
	(vmlaq_m_n_u8): Likewise.
	(vmlaq_m_n_u32): Likewise.
	(vmlaq_m_n_u16): Likewise.
	(vmlasq_m_n_s8): Likewise.
	(vmlasq_m_n_s32): Likewise.
	(vmlasq_m_n_s16): Likewise.
	(vmlasq_m_n_u8): Likewise.
	(vmlasq_m_n_u32): Likewise.
	(vmlasq_m_n_u16): Likewise.
	(vmlsdavaq_p_s8): Likewise.
	(vmlsdavaq_p_s32): Likewise.
	(vmlsdavaq_p_s16): Likewise.
	(vmlsdavaxq_p_s8): Likewise.
	(vmlsdavaxq_p_s32): Likewise.
	(vmlsdavaxq_p_s16): Likewise.
	(vmulhq_m_s8): Likewise.
	(vmulhq_m_s32): Likewise.
	(vmulhq_m_s16): Likewise.
	(vmulhq_m_u8): Likewise.
	(vmulhq_m_u32): Likewise.
	(vmulhq_m_u16): Likewise.
	(vmullbq_int_m_s8): Likewise.
	(vmullbq_int_m_s32): Likewise.
	(vmullbq_int_m_s16): Likewise.
	(vmullbq_int_m_u8): Likewise.
	(vmullbq_int_m_u32): Likewise.
	(vmullbq_int_m_u16): Likewise.
	(vmulltq_int_m_s8): Likewise.
	(vmulltq_int_m_s32): Likewise.
	(vmulltq_int_m_s16): Likewise.
	(vmulltq_int_m_u8): Likewise.
	(vmulltq_int_m_u32): Likewise.
	(vmulltq_int_m_u16): Likewise.
	(vmulq_m_n_s8): Likewise.
	(vmulq_m_n_s32): Likewise.
	(vmulq_m_n_s16): Likewise.
	(vmulq_m_n_u8): Likewise.
	(vmulq_m_n_u32): Likewise.
	(vmulq_m_n_u16): Likewise.
	(vmulq_m_s8): Likewise.
	(vmulq_m_s32): Likewise.
	(vmulq_m_s16): Likewise.
	(vmulq_m_u8): Likewise.
	(vmulq_m_u32): Likewise.
	(vmulq_m_u16): Likewise.
	(vornq_m_s8): Likewise.
	(vornq_m_s32): Likewise.
	(vornq_m_s16): Likewise.
	(vornq_m_u8): Likewise.
	(vornq_m_u32): Likewise.
	(vornq_m_u16): Likewise.
	(vorrq_m_s8): Likewise.
	(vorrq_m_s32): Likewise.
	(vorrq_m_s16): Likewise.
	(vorrq_m_u8): Likewise.
	(vorrq_m_u32): Likewise.
	(vorrq_m_u16): Likewise.
	(vqaddq_m_n_s8): Likewise.
	(vqaddq_m_n_s32): Likewise.
	(vqaddq_m_n_s16): Likewise.
	(vqaddq_m_n_u8): Likewise.
	(vqaddq_m_n_u32): Likewise.
	(vqaddq_m_n_u16): Likewise.
	(vqaddq_m_s8): Likewise.
	(vqaddq_m_s32): Likewise.
	(vqaddq_m_s16): Likewise.
	(vqaddq_m_u8): Likewise.
	(vqaddq_m_u32): Likewise.
	(vqaddq_m_u16): Likewise.
	(vqdmladhq_m_s8): Likewise.
	(vqdmladhq_m_s32): Likewise.
	(vqdmladhq_m_s16): Likewise.
	(vqdmladhxq_m_s8): Likewise.
	(vqdmladhxq_m_s32): Likewise.
	(vqdmladhxq_m_s16): Likewise.
	(vqdmlahq_m_n_s8): Likewise.
	(vqdmlahq_m_n_s32): Likewise.
	(vqdmlahq_m_n_s16): Likewise.
	(vqdmlahq_m_n_u8): Likewise.
	(vqdmlahq_m_n_u32): Likewise.
	(vqdmlahq_m_n_u16): Likewise.
	(vqdmlsdhq_m_s8): Likewise.
	(vqdmlsdhq_m_s32): Likewise.
	(vqdmlsdhq_m_s16): Likewise.
	(vqdmlsdhxq_m_s8): Likewise.
	(vqdmlsdhxq_m_s32): Likewise.
	(vqdmlsdhxq_m_s16): Likewise.
	(vqdmulhq_m_n_s8): Likewise.
	(vqdmulhq_m_n_s32): Likewise.
	(vqdmulhq_m_n_s16): Likewise.
	(vqdmulhq_m_s8): Likewise.
	(vqdmulhq_m_s32): Likewise.
	(vqdmulhq_m_s16): Likewise.
	(vqrdmladhq_m_s8): Likewise.
	(vqrdmladhq_m_s32): Likewise.
	(vqrdmladhq_m_s16): Likewise.
	(vqrdmladhxq_m_s8): Likewise.
	(vqrdmladhxq_m_s32): Likewise.
	(vqrdmladhxq_m_s16): Likewise.
	(vqrdmlahq_m_n_s8): Likewise.
	(vqrdmlahq_m_n_s32): Likewise.
	(vqrdmlahq_m_n_s16): Likewise.
	(vqrdmlahq_m_n_u8): Likewise.
	(vqrdmlahq_m_n_u32): Likewise.
	(vqrdmlahq_m_n_u16): Likewise.
	(vqrdmlashq_m_n_s8): Likewise.
	(vqrdmlashq_m_n_s32): Likewise.
	(vqrdmlashq_m_n_s16): Likewise.
	(vqrdmlashq_m_n_u8): Likewise.
	(vqrdmlashq_m_n_u32): Likewise.
	(vqrdmlashq_m_n_u16): Likewise.
	(vqrdmlsdhq_m_s8): Likewise.
	(vqrdmlsdhq_m_s32): Likewise.
	(vqrdmlsdhq_m_s16): Likewise.
	(vqrdmlsdhxq_m_s8): Likewise.
	(vqrdmlsdhxq_m_s32): Likewise.
	(vqrdmlsdhxq_m_s16): Likewise.
	(vqrdmulhq_m_n_s8): Likewise.
	(vqrdmulhq_m_n_s32): Likewise.
	(vqrdmulhq_m_n_s16): Likewise.
	(vqrdmulhq_m_s8): Likewise.
	(vqrdmulhq_m_s32): Likewise.
	(vqrdmulhq_m_s16): Likewise.
	(vqrshlq_m_s8): Likewise.
	(vqrshlq_m_s32): Likewise.
	(vqrshlq_m_s16): Likewise.
	(vqrshlq_m_u8): Likewise.
	(vqrshlq_m_u32): Likewise.
	(vqrshlq_m_u16): Likewise.
	(vqshlq_m_n_s8): Likewise.
	(vqshlq_m_n_s32): Likewise.
	(vqshlq_m_n_s16): Likewise.
	(vqshlq_m_n_u8): Likewise.
	(vqshlq_m_n_u32): Likewise.
	(vqshlq_m_n_u16): Likewise.
	(vqshlq_m_s8): Likewise.
	(vqshlq_m_s32): Likewise.
	(vqshlq_m_s16): Likewise.
	(vqshlq_m_u8): Likewise.
	(vqshlq_m_u32): Likewise.
	(vqshlq_m_u16): Likewise.
	(vqsubq_m_n_s8): Likewise.
	(vqsubq_m_n_s32): Likewise.
	(vqsubq_m_n_s16): Likewise.
	(vqsubq_m_n_u8): Likewise.
	(vqsubq_m_n_u32): Likewise.
	(vqsubq_m_n_u16): Likewise.
	(vqsubq_m_s8): Likewise.
	(vqsubq_m_s32): Likewise.
	(vqsubq_m_s16): Likewise.
	(vqsubq_m_u8): Likewise.
	(vqsubq_m_u32): Likewise.
	(vqsubq_m_u16): Likewise.
	(vrhaddq_m_s8): Likewise.
	(vrhaddq_m_s32): Likewise.
	(vrhaddq_m_s16): Likewise.
	(vrhaddq_m_u8): Likewise.
	(vrhaddq_m_u32): Likewise.
	(vrhaddq_m_u16): Likewise.
	(vrmulhq_m_s8): Likewise.
	(vrmulhq_m_s32): Likewise.
	(vrmulhq_m_s16): Likewise.
	(vrmulhq_m_u8): Likewise.
	(vrmulhq_m_u32): Likewise.
	(vrmulhq_m_u16): Likewise.
	(vrshlq_m_s8): Likewise.
	(vrshlq_m_s32): Likewise.
	(vrshlq_m_s16): Likewise.
	(vrshlq_m_u8): Likewise.
	(vrshlq_m_u32): Likewise.
	(vrshlq_m_u16): Likewise.
	(vrshrq_m_n_s8): Likewise.
	(vrshrq_m_n_s32): Likewise.
	(vrshrq_m_n_s16): Likewise.
	(vrshrq_m_n_u8): Likewise.
	(vrshrq_m_n_u32): Likewise.
	(vrshrq_m_n_u16): Likewise.
	(vshlq_m_n_s8): Likewise.
	(vshlq_m_n_s32): Likewise.
	(vshlq_m_n_s16): Likewise.
	(vshlq_m_n_u8): Likewise.
	(vshlq_m_n_u32): Likewise.
	(vshlq_m_n_u16): Likewise.
	(vshrq_m_n_s8): Likewise.
	(vshrq_m_n_s32): Likewise.
	(vshrq_m_n_s16): Likewise.
	(vshrq_m_n_u8): Likewise.
	(vshrq_m_n_u32): Likewise.
	(vshrq_m_n_u16): Likewise.
	(vsliq_m_n_s8): Likewise.
	(vsliq_m_n_s32): Likewise.
	(vsliq_m_n_s16): Likewise.
	(vsliq_m_n_u8): Likewise.
	(vsliq_m_n_u32): Likewise.
	(vsliq_m_n_u16): Likewise.
	(vsubq_m_n_s8): Likewise.
	(vsubq_m_n_s32): Likewise.
	(vsubq_m_n_s16): Likewise.
	(vsubq_m_n_u8): Likewise.
	(vsubq_m_n_u32): Likewise.
	(vsubq_m_n_u16): Likewise.
	(__arm_vabdq_m_s8): Define intrinsic.
	(__arm_vabdq_m_s32): Likewise.
	(__arm_vabdq_m_s16): Likewise.
	(__arm_vabdq_m_u8): Likewise.
	(__arm_vabdq_m_u32): Likewise.
	(__arm_vabdq_m_u16): Likewise.
	(__arm_vaddq_m_n_s8): Likewise.
	(__arm_vaddq_m_n_s32): Likewise.
	(__arm_vaddq_m_n_s16): Likewise.
	(__arm_vaddq_m_n_u8): Likewise.
	(__arm_vaddq_m_n_u32): Likewise.
	(__arm_vaddq_m_n_u16): Likewise.
	(__arm_vaddq_m_s8): Likewise.
	(__arm_vaddq_m_s32): Likewise.
	(__arm_vaddq_m_s16): Likewise.
	(__arm_vaddq_m_u8): Likewise.
	(__arm_vaddq_m_u32): Likewise.
	(__arm_vaddq_m_u16): Likewise.
	(__arm_vandq_m_s8): Likewise.
	(__arm_vandq_m_s32): Likewise.
	(__arm_vandq_m_s16): Likewise.
	(__arm_vandq_m_u8): Likewise.
	(__arm_vandq_m_u32): Likewise.
	(__arm_vandq_m_u16): Likewise.
	(__arm_vbicq_m_s8): Likewise.
	(__arm_vbicq_m_s32): Likewise.
	(__arm_vbicq_m_s16): Likewise.
	(__arm_vbicq_m_u8): Likewise.
	(__arm_vbicq_m_u32): Likewise.
	(__arm_vbicq_m_u16): Likewise.
	(__arm_vbrsrq_m_n_s8): Likewise.
	(__arm_vbrsrq_m_n_s32): Likewise.
	(__arm_vbrsrq_m_n_s16): Likewise.
	(__arm_vbrsrq_m_n_u8): Likewise.
	(__arm_vbrsrq_m_n_u32): Likewise.
	(__arm_vbrsrq_m_n_u16): Likewise.
	(__arm_vcaddq_rot270_m_s8): Likewise.
	(__arm_vcaddq_rot270_m_s32): Likewise.
	(__arm_vcaddq_rot270_m_s16): Likewise.
	(__arm_vcaddq_rot270_m_u8): Likewise.
	(__arm_vcaddq_rot270_m_u32): Likewise.
	(__arm_vcaddq_rot270_m_u16): Likewise.
	(__arm_vcaddq_rot90_m_s8): Likewise.
	(__arm_vcaddq_rot90_m_s32): Likewise.
	(__arm_vcaddq_rot90_m_s16): Likewise.
	(__arm_vcaddq_rot90_m_u8): Likewise.
	(__arm_vcaddq_rot90_m_u32): Likewise.
	(__arm_vcaddq_rot90_m_u16): Likewise.
	(__arm_veorq_m_s8): Likewise.
	(__arm_veorq_m_s32): Likewise.
	(__arm_veorq_m_s16): Likewise.
	(__arm_veorq_m_u8): Likewise.
	(__arm_veorq_m_u32): Likewise.
	(__arm_veorq_m_u16): Likewise.
	(__arm_vhaddq_m_n_s8): Likewise.
	(__arm_vhaddq_m_n_s32): Likewise.
	(__arm_vhaddq_m_n_s16): Likewise.
	(__arm_vhaddq_m_n_u8): Likewise.
	(__arm_vhaddq_m_n_u32): Likewise.
	(__arm_vhaddq_m_n_u16): Likewise.
	(__arm_vhaddq_m_s8): Likewise.
	(__arm_vhaddq_m_s32): Likewise.
	(__arm_vhaddq_m_s16): Likewise.
	(__arm_vhaddq_m_u8): Likewise.
	(__arm_vhaddq_m_u32): Likewise.
	(__arm_vhaddq_m_u16): Likewise.
	(__arm_vhcaddq_rot270_m_s8): Likewise.
	(__arm_vhcaddq_rot270_m_s32): Likewise.
	(__arm_vhcaddq_rot270_m_s16): Likewise.
	(__arm_vhcaddq_rot90_m_s8): Likewise.
	(__arm_vhcaddq_rot90_m_s32): Likewise.
	(__arm_vhcaddq_rot90_m_s16): Likewise.
	(__arm_vhsubq_m_n_s8): Likewise.
	(__arm_vhsubq_m_n_s32): Likewise.
	(__arm_vhsubq_m_n_s16): Likewise.
	(__arm_vhsubq_m_n_u8): Likewise.
	(__arm_vhsubq_m_n_u32): Likewise.
	(__arm_vhsubq_m_n_u16): Likewise.
	(__arm_vhsubq_m_s8): Likewise.
	(__arm_vhsubq_m_s32): Likewise.
	(__arm_vhsubq_m_s16): Likewise.
	(__arm_vhsubq_m_u8): Likewise.
	(__arm_vhsubq_m_u32): Likewise.
	(__arm_vhsubq_m_u16): Likewise.
	(__arm_vmaxq_m_s8): Likewise.
	(__arm_vmaxq_m_s32): Likewise.
	(__arm_vmaxq_m_s16): Likewise.
	(__arm_vmaxq_m_u8): Likewise.
	(__arm_vmaxq_m_u32): Likewise.
	(__arm_vmaxq_m_u16): Likewise.
	(__arm_vminq_m_s8): Likewise.
	(__arm_vminq_m_s32): Likewise.
	(__arm_vminq_m_s16): Likewise.
	(__arm_vminq_m_u8): Likewise.
	(__arm_vminq_m_u32): Likewise.
	(__arm_vminq_m_u16): Likewise.
	(__arm_vmladavaq_p_s8): Likewise.
	(__arm_vmladavaq_p_s32): Likewise.
	(__arm_vmladavaq_p_s16): Likewise.
	(__arm_vmladavaq_p_u8): Likewise.
	(__arm_vmladavaq_p_u32): Likewise.
	(__arm_vmladavaq_p_u16): Likewise.
	(__arm_vmladavaxq_p_s8): Likewise.
	(__arm_vmladavaxq_p_s32): Likewise.
	(__arm_vmladavaxq_p_s16): Likewise.
	(__arm_vmlaq_m_n_s8): Likewise.
	(__arm_vmlaq_m_n_s32): Likewise.
	(__arm_vmlaq_m_n_s16): Likewise.
	(__arm_vmlaq_m_n_u8): Likewise.
	(__arm_vmlaq_m_n_u32): Likewise.
	(__arm_vmlaq_m_n_u16): Likewise.
	(__arm_vmlasq_m_n_s8): Likewise.
	(__arm_vmlasq_m_n_s32): Likewise.
	(__arm_vmlasq_m_n_s16): Likewise.
	(__arm_vmlasq_m_n_u8): Likewise.
	(__arm_vmlasq_m_n_u32): Likewise.
	(__arm_vmlasq_m_n_u16): Likewise.
	(__arm_vmlsdavaq_p_s8): Likewise.
	(__arm_vmlsdavaq_p_s32): Likewise.
	(__arm_vmlsdavaq_p_s16): Likewise.
	(__arm_vmlsdavaxq_p_s8): Likewise.
	(__arm_vmlsdavaxq_p_s32): Likewise.
	(__arm_vmlsdavaxq_p_s16): Likewise.
	(__arm_vmulhq_m_s8): Likewise.
	(__arm_vmulhq_m_s32): Likewise.
	(__arm_vmulhq_m_s16): Likewise.
	(__arm_vmulhq_m_u8): Likewise.
	(__arm_vmulhq_m_u32): Likewise.
	(__arm_vmulhq_m_u16): Likewise.
	(__arm_vmullbq_int_m_s8): Likewise.
	(__arm_vmullbq_int_m_s32): Likewise.
	(__arm_vmullbq_int_m_s16): Likewise.
	(__arm_vmullbq_int_m_u8): Likewise.
	(__arm_vmullbq_int_m_u32): Likewise.
	(__arm_vmullbq_int_m_u16): Likewise.
	(__arm_vmulltq_int_m_s8): Likewise.
	(__arm_vmulltq_int_m_s32): Likewise.
	(__arm_vmulltq_int_m_s16): Likewise.
	(__arm_vmulltq_int_m_u8): Likewise.
	(__arm_vmulltq_int_m_u32): Likewise.
	(__arm_vmulltq_int_m_u16): Likewise.
	(__arm_vmulq_m_n_s8): Likewise.
	(__arm_vmulq_m_n_s32): Likewise.
	(__arm_vmulq_m_n_s16): Likewise.
	(__arm_vmulq_m_n_u8): Likewise.
	(__arm_vmulq_m_n_u32): Likewise.
	(__arm_vmulq_m_n_u16): Likewise.
	(__arm_vmulq_m_s8): Likewise.
	(__arm_vmulq_m_s32): Likewise.
	(__arm_vmulq_m_s16): Likewise.
	(__arm_vmulq_m_u8): Likewise.
	(__arm_vmulq_m_u32): Likewise.
	(__arm_vmulq_m_u16): Likewise.
	(__arm_vornq_m_s8): Likewise.
	(__arm_vornq_m_s32): Likewise.
	(__arm_vornq_m_s16): Likewise.
	(__arm_vornq_m_u8): Likewise.
	(__arm_vornq_m_u32): Likewise.
	(__arm_vornq_m_u16): Likewise.
	(__arm_vorrq_m_s8): Likewise.
	(__arm_vorrq_m_s32): Likewise.
	(__arm_vorrq_m_s16): Likewise.
	(__arm_vorrq_m_u8): Likewise.
	(__arm_vorrq_m_u32): Likewise.
	(__arm_vorrq_m_u16): Likewise.
	(__arm_vqaddq_m_n_s8): Likewise.
	(__arm_vqaddq_m_n_s32): Likewise.
	(__arm_vqaddq_m_n_s16): Likewise.
	(__arm_vqaddq_m_n_u8): Likewise.
	(__arm_vqaddq_m_n_u32): Likewise.
	(__arm_vqaddq_m_n_u16): Likewise.
	(__arm_vqaddq_m_s8): Likewise.
	(__arm_vqaddq_m_s32): Likewise.
	(__arm_vqaddq_m_s16): Likewise.
	(__arm_vqaddq_m_u8): Likewise.
	(__arm_vqaddq_m_u32): Likewise.
	(__arm_vqaddq_m_u16): Likewise.
	(__arm_vqdmladhq_m_s8): Likewise.
	(__arm_vqdmladhq_m_s32): Likewise.
	(__arm_vqdmladhq_m_s16): Likewise.
	(__arm_vqdmladhxq_m_s8): Likewise.
	(__arm_vqdmladhxq_m_s32): Likewise.
	(__arm_vqdmladhxq_m_s16): Likewise.
	(__arm_vqdmlahq_m_n_s8): Likewise.
	(__arm_vqdmlahq_m_n_s32): Likewise.
	(__arm_vqdmlahq_m_n_s16): Likewise.
	(__arm_vqdmlahq_m_n_u8): Likewise.
	(__arm_vqdmlahq_m_n_u32): Likewise.
	(__arm_vqdmlahq_m_n_u16): Likewise.
	(__arm_vqdmlsdhq_m_s8): Likewise.
	(__arm_vqdmlsdhq_m_s32): Likewise.
	(__arm_vqdmlsdhq_m_s16): Likewise.
	(__arm_vqdmlsdhxq_m_s8): Likewise.
	(__arm_vqdmlsdhxq_m_s32): Likewise.
	(__arm_vqdmlsdhxq_m_s16): Likewise.
	(__arm_vqdmulhq_m_n_s8): Likewise.
	(__arm_vqdmulhq_m_n_s32): Likewise.
	(__arm_vqdmulhq_m_n_s16): Likewise.
	(__arm_vqdmulhq_m_s8): Likewise.
	(__arm_vqdmulhq_m_s32): Likewise.
	(__arm_vqdmulhq_m_s16): Likewise.
	(__arm_vqrdmladhq_m_s8): Likewise.
	(__arm_vqrdmladhq_m_s32): Likewise.
	(__arm_vqrdmladhq_m_s16): Likewise.
	(__arm_vqrdmladhxq_m_s8): Likewise.
	(__arm_vqrdmladhxq_m_s32): Likewise.
	(__arm_vqrdmladhxq_m_s16): Likewise.
	(__arm_vqrdmlahq_m_n_s8): Likewise.
	(__arm_vqrdmlahq_m_n_s32): Likewise.
	(__arm_vqrdmlahq_m_n_s16): Likewise.
	(__arm_vqrdmlahq_m_n_u8): Likewise.
	(__arm_vqrdmlahq_m_n_u32): Likewise.
	(__arm_vqrdmlahq_m_n_u16): Likewise.
	(__arm_vqrdmlashq_m_n_s8): Likewise.
	(__arm_vqrdmlashq_m_n_s32): Likewise.
	(__arm_vqrdmlashq_m_n_s16): Likewise.
	(__arm_vqrdmlashq_m_n_u8): Likewise.
	(__arm_vqrdmlashq_m_n_u32): Likewise.
	(__arm_vqrdmlashq_m_n_u16): Likewise.
	(__arm_vqrdmlsdhq_m_s8): Likewise.
	(__arm_vqrdmlsdhq_m_s32): Likewise.
	(__arm_vqrdmlsdhq_m_s16): Likewise.
	(__arm_vqrdmlsdhxq_m_s8): Likewise.
	(__arm_vqrdmlsdhxq_m_s32): Likewise.
	(__arm_vqrdmlsdhxq_m_s16): Likewise.
	(__arm_vqrdmulhq_m_n_s8): Likewise.
	(__arm_vqrdmulhq_m_n_s32): Likewise.
	(__arm_vqrdmulhq_m_n_s16): Likewise.
	(__arm_vqrdmulhq_m_s8): Likewise.
	(__arm_vqrdmulhq_m_s32): Likewise.
	(__arm_vqrdmulhq_m_s16): Likewise.
	(__arm_vqrshlq_m_s8): Likewise.
	(__arm_vqrshlq_m_s32): Likewise.
	(__arm_vqrshlq_m_s16): Likewise.
	(__arm_vqrshlq_m_u8): Likewise.
	(__arm_vqrshlq_m_u32): Likewise.
	(__arm_vqrshlq_m_u16): Likewise.
	(__arm_vqshlq_m_n_s8): Likewise.
	(__arm_vqshlq_m_n_s32): Likewise.
	(__arm_vqshlq_m_n_s16): Likewise.
	(__arm_vqshlq_m_n_u8): Likewise.
	(__arm_vqshlq_m_n_u32): Likewise.
	(__arm_vqshlq_m_n_u16): Likewise.
	(__arm_vqshlq_m_s8): Likewise.
	(__arm_vqshlq_m_s32): Likewise.
	(__arm_vqshlq_m_s16): Likewise.
	(__arm_vqshlq_m_u8): Likewise.
	(__arm_vqshlq_m_u32): Likewise.
	(__arm_vqshlq_m_u16): Likewise.
	(__arm_vqsubq_m_n_s8): Likewise.
	(__arm_vqsubq_m_n_s32): Likewise.
	(__arm_vqsubq_m_n_s16): Likewise.
	(__arm_vqsubq_m_n_u8): Likewise.
	(__arm_vqsubq_m_n_u32): Likewise.
	(__arm_vqsubq_m_n_u16): Likewise.
	(__arm_vqsubq_m_s8): Likewise.
	(__arm_vqsubq_m_s32): Likewise.
	(__arm_vqsubq_m_s16): Likewise.
	(__arm_vqsubq_m_u8): Likewise.
	(__arm_vqsubq_m_u32): Likewise.
	(__arm_vqsubq_m_u16): Likewise.
	(__arm_vrhaddq_m_s8): Likewise.
	(__arm_vrhaddq_m_s32): Likewise.
	(__arm_vrhaddq_m_s16): Likewise.
	(__arm_vrhaddq_m_u8): Likewise.
	(__arm_vrhaddq_m_u32): Likewise.
	(__arm_vrhaddq_m_u16): Likewise.
	(__arm_vrmulhq_m_s8): Likewise.
	(__arm_vrmulhq_m_s32): Likewise.
	(__arm_vrmulhq_m_s16): Likewise.
	(__arm_vrmulhq_m_u8): Likewise.
	(__arm_vrmulhq_m_u32): Likewise.
	(__arm_vrmulhq_m_u16): Likewise.
	(__arm_vrshlq_m_s8): Likewise.
	(__arm_vrshlq_m_s32): Likewise.
	(__arm_vrshlq_m_s16): Likewise.
	(__arm_vrshlq_m_u8): Likewise.
	(__arm_vrshlq_m_u32): Likewise.
	(__arm_vrshlq_m_u16): Likewise.
	(__arm_vrshrq_m_n_s8): Likewise.
	(__arm_vrshrq_m_n_s32): Likewise.
	(__arm_vrshrq_m_n_s16): Likewise.
	(__arm_vrshrq_m_n_u8): Likewise.
	(__arm_vrshrq_m_n_u32): Likewise.
	(__arm_vrshrq_m_n_u16): Likewise.
	(__arm_vshlq_m_n_s8): Likewise.
	(__arm_vshlq_m_n_s32): Likewise.
	(__arm_vshlq_m_n_s16): Likewise.
	(__arm_vshlq_m_n_u8): Likewise.
	(__arm_vshlq_m_n_u32): Likewise.
	(__arm_vshlq_m_n_u16): Likewise.
	(__arm_vshrq_m_n_s8): Likewise.
	(__arm_vshrq_m_n_s32): Likewise.
	(__arm_vshrq_m_n_s16): Likewise.
	(__arm_vshrq_m_n_u8): Likewise.
	(__arm_vshrq_m_n_u32): Likewise.
	(__arm_vshrq_m_n_u16): Likewise.
	(__arm_vsliq_m_n_s8): Likewise.
	(__arm_vsliq_m_n_s32): Likewise.
	(__arm_vsliq_m_n_s16): Likewise.
	(__arm_vsliq_m_n_u8): Likewise.
	(__arm_vsliq_m_n_u32): Likewise.
	(__arm_vsliq_m_n_u16): Likewise.
	(__arm_vsubq_m_n_s8): Likewise.
	(__arm_vsubq_m_n_s32): Likewise.
	(__arm_vsubq_m_n_s16): Likewise.
	(__arm_vsubq_m_n_u8): Likewise.
	(__arm_vsubq_m_n_u32): Likewise.
	(__arm_vsubq_m_n_u16): Likewise.
	(vqdmladhq_m): Define polymorphic variant.
	(vqdmladhxq_m): Likewise.
	(vqdmlsdhq_m): Likewise.
	(vqdmlsdhxq_m): Likewise.
	(vabdq_m): Likewise.
	(vandq_m): Likewise.
	(vbicq_m): Likewise.
	(vbrsrq_m_n): Likewise.
	(vcaddq_rot270_m): Likewise.
	(vcaddq_rot90_m): Likewise.
	(veorq_m): Likewise.
	(vmaxq_m): Likewise.
	(vminq_m): Likewise.
	(vmladavaq_p): Likewise.
	(vmlaq_m_n): Likewise.
	(vmlasq_m_n): Likewise.
	(vmulhq_m): Likewise.
	(vmullbq_int_m): Likewise.
	(vmulltq_int_m): Likewise.
	(vornq_m): Likewise.
	(vorrq_m): Likewise.
	(vqdmlahq_m_n): Likewise.
	(vqrdmlahq_m_n): Likewise.
	(vqrdmlashq_m_n): Likewise.
	(vqrshlq_m): Likewise.
	(vqshlq_m_n): Likewise.
	(vqshlq_m): Likewise.
	(vrhaddq_m): Likewise.
	(vrmulhq_m): Likewise.
	(vrshlq_m): Likewise.
	(vrshrq_m_n): Likewise.
	(vshlq_m_n): Likewise.
	(vshrq_m_n): Likewise.
	(vsliq_m): Likewise.
	(vaddq_m_n): Likewise.
	(vaddq_m): Likewise.
	(vhaddq_m_n): Likewise.
	(vhaddq_m): Likewise.
	(vhcaddq_rot270_m): Likewise.
	(vhcaddq_rot90_m): Likewise.
	(vhsubq_m): Likewise.
	(vhsubq_m_n): Likewise.
	(vmulq_m_n): Likewise.
	(vmulq_m): Likewise.
	(vqaddq_m_n): Likewise.
	(vqaddq_m): Likewise.
	(vqdmulhq_m_n): Likewise.
	(vqdmulhq_m): Likewise.
	(vsubq_m_n): Likewise.
	(vsliq_m_n): Likewise.
	(vqsubq_m_n): Likewise.
	(vqsubq_m): Likewise.
	(vqrdmulhq_m): Likewise.
	(vqrdmulhq_m_n): Likewise.
	(vqrdmlsdhxq_m): Likewise.
	(vqrdmlsdhq_m): Likewise.
	(vqrdmladhq_m): Likewise.
	(vqrdmladhxq_m): Likewise.
	(vmlsdavaxq_p): Likewise.
	(vmlsdavaq_p): Likewise.
	(vmladavaxq_p): Likewise.
	* config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
	builtin qualifier.
	(QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
	* config/arm/mve.md (VHSUBQ_M): Define iterators.
	(VSLIQ_M_N): Likewise.
	(VQRDMLAHQ_M_N): Likewise.
	(VRSHLQ_M): Likewise.
	(VMINQ_M): Likewise.
	(VMULLBQ_INT_M): Likewise.
	(VMULHQ_M): Likewise.
	(VMULQ_M): Likewise.
	(VHSUBQ_M_N): Likewise.
	(VHADDQ_M_N): Likewise.
	(VORRQ_M): Likewise.
	(VRMULHQ_M): Likewise.
	(VQADDQ_M): Likewise.
	(VRSHRQ_M_N): Likewise.
	(VQSUBQ_M_N): Likewise.
	(VADDQ_M): Likewise.
	(VORNQ_M): Likewise.
	(VQDMLAHQ_M_N): Likewise.
	(VRHADDQ_M): Likewise.
	(VQSHLQ_M): Likewise.
	(VANDQ_M): Likewise.
	(VBICQ_M): Likewise.
	(VSHLQ_M_N): Likewise.
	(VCADDQ_ROT270_M): Likewise.
	(VQRSHLQ_M): Likewise.
	(VQADDQ_M_N): Likewise.
	(VADDQ_M_N): Likewise.
	(VMAXQ_M): Likewise.
	(VQSUBQ_M): Likewise.
	(VMLASQ_M_N): Likewise.
	(VMLADAVAQ_P): Likewise.
	(VBRSRQ_M_N): Likewise.
	(VMULQ_M_N): Likewise.
	(VCADDQ_ROT90_M): Likewise.
	(VMULLTQ_INT_M): Likewise.
	(VEORQ_M): Likewise.
	(VSHRQ_M_N): Likewise.
	(VSUBQ_M_N): Likewise.
	(VHADDQ_M): Likewise.
	(VABDQ_M): Likewise.
	(VQRDMLASHQ_M_N): Likewise.
	(VMLAQ_M_N): Likewise.
	(VQSHLQ_M_N): Likewise.
	(mve_vabdq_m_<supf><mode>): Define RTL pattern.
	(mve_vaddq_m_n_<supf><mode>): Likewise.
	(mve_vaddq_m_<supf><mode>): Likewise.
	(mve_vandq_m_<supf><mode>): Likewise.
	(mve_vbicq_m_<supf><mode>): Likewise.
	(mve_vbrsrq_m_n_<supf><mode>): Likewise.
	(mve_vcaddq_rot270_m_<supf><mode>): Likewise.
	(mve_vcaddq_rot90_m_<supf><mode>): Likewise.
	(mve_veorq_m_<supf><mode>): Likewise.
	(mve_vhaddq_m_n_<supf><mode>): Likewise.
	(mve_vhaddq_m_<supf><mode>): Likewise.
	(mve_vhsubq_m_n_<supf><mode>): Likewise.
	(mve_vhsubq_m_<supf><mode>): Likewise.
	(mve_vmaxq_m_<supf><mode>): Likewise.
	(mve_vminq_m_<supf><mode>): Likewise.
	(mve_vmladavaq_p_<supf><mode>): Likewise.
	(mve_vmlaq_m_n_<supf><mode>): Likewise.
	(mve_vmlasq_m_n_<supf><mode>): Likewise.
	(mve_vmulhq_m_<supf><mode>): Likewise.
	(mve_vmullbq_int_m_<supf><mode>): Likewise.
	(mve_vmulltq_int_m_<supf><mode>): Likewise.
	(mve_vmulq_m_n_<supf><mode>): Likewise.
	(mve_vmulq_m_<supf><mode>): Likewise.
	(mve_vornq_m_<supf><mode>): Likewise.
	(mve_vorrq_m_<supf><mode>): Likewise.
	(mve_vqaddq_m_n_<supf><mode>): Likewise.
	(mve_vqaddq_m_<supf><mode>): Likewise.
	(mve_vqdmlahq_m_n_<supf><mode>): Likewise.
	(mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
	(mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
	(mve_vqrshlq_m_<supf><mode>): Likewise.
	(mve_vqshlq_m_n_<supf><mode>): Likewise.
	(mve_vqshlq_m_<supf><mode>): Likewise.
	(mve_vqsubq_m_n_<supf><mode>): Likewise.
	(mve_vqsubq_m_<supf><mode>): Likewise.
	(mve_vrhaddq_m_<supf><mode>): Likewise.
	(mve_vrmulhq_m_<supf><mode>): Likewise.
	(mve_vrshlq_m_<supf><mode>): Likewise.
	(mve_vrshrq_m_n_<supf><mode>): Likewise.
	(mve_vshlq_m_n_<supf><mode>): Likewise.
	(mve_vshrq_m_n_<supf><mode>): Likewise.
	(mve_vsliq_m_n_<supf><mode>): Likewise.
	(mve_vsubq_m_n_<supf><mode>): Likewise.
	(mve_vhcaddq_rot270_m_s<mode>): Likewise.
	(mve_vhcaddq_rot90_m_s<mode>): Likewise.
	(mve_vmladavaxq_p_s<mode>): Likewise.
	(mve_vmlsdavaq_p_s<mode>): Likewise.
	(mve_vmlsdavaxq_p_s<mode>): Likewise.
	(mve_vqdmladhq_m_s<mode>): Likewise.
	(mve_vqdmladhxq_m_s<mode>): Likewise.
	(mve_vqdmlsdhq_m_s<mode>): Likewise.
	(mve_vqdmlsdhxq_m_s<mode>): Likewise.
	(mve_vqdmulhq_m_n_s<mode>): Likewise.
	(mve_vqdmulhq_m_s<mode>): Likewise.
	(mve_vqrdmladhq_m_s<mode>): Likewise.
	(mve_vqrdmladhxq_m_s<mode>): Likewise.
	(mve_vqrdmlsdhq_m_s<mode>): Likewise.
	(mve_vqrdmlsdhxq_m_s<mode>): Likewise.
	(mve_vqrdmulhq_m_n_s<mode>): Likewise.
	(mve_vqrdmulhq_m_s<mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.