This patch supports following MVE ACLE intrinsics with ternary operands.

vpselq_u8, vpselq_s8, vrev64q_m_u8, vqrdmlashq_n_u8, vqrdmlahq_n_u8, vqdmlahq_n_u8, vmvnq_m_u8, vmlasq_n_u8, vmlaq_n_u8, vmladavq_p_u8, vmladavaq_u8, vminvq_p_u8, vmaxvq_p_u8, vdupq_m_n_u8, vcmpneq_m_u8, vcmpneq_m_n_u8, vcmphiq_m_u8, vcmphiq_m_n_u8, vcmpeqq_m_u8, vcmpeqq_m_n_u8, vcmpcsq_m_u8, vcmpcsq_m_n_u8, vclzq_m_u8, vaddvaq_p_u8, vsriq_n_u8, vsliq_n_u8, vshlq_m_r_u8, vrshlq_m_n_u8, vqshlq_m_r_u8, vqrshlq_m_n_u8, vminavq_p_s8, vminaq_m_s8, vmaxavq_p_s8, vmaxaq_m_s8, vcmpneq_m_s8, vcmpneq_m_n_s8, vcmpltq_m_s8, vcmpltq_m_n_s8, vcmpleq_m_s8, vcmpleq_m_n_s8, vcmpgtq_m_s8, vcmpgtq_m_n_s8, vcmpgeq_m_s8, vcmpgeq_m_n_s8, vcmpeqq_m_s8, vcmpeqq_m_n_s8, vshlq_m_r_s8, vrshlq_m_n_s8, vrev64q_m_s8, vqshlq_m_r_s8, vqrshlq_m_n_s8, vqnegq_m_s8, vqabsq_m_s8, vnegq_m_s8, vmvnq_m_s8, vmlsdavxq_p_s8, vmlsdavq_p_s8, vmladavxq_p_s8, vmladavq_p_s8, vminvq_p_s8, vmaxvq_p_s8, vdupq_m_n_s8, vclzq_m_s8, vclsq_m_s8, vaddvaq_p_s8, vabsq_m_s8, vqrdmlsdhxq_s8, vqrdmlsdhq_s8, vqrdmlashq_n_s8, vqrdmlahq_n_s8, vqrdmladhxq_s8, vqrdmladhq_s8, vqdmlsdhxq_s8, vqdmlsdhq_s8, vqdmlahq_n_s8, vqdmladhxq_s8, vqdmladhq_s8, vmlsdavaxq_s8, vmlsdavaq_s8, vmlasq_n_s8, vmlaq_n_s8, vmladavaxq_s8, vmladavaq_s8, vsriq_n_s8, vsliq_n_s8, vpselq_u16, vpselq_s16, vrev64q_m_u16, vqrdmlashq_n_u16, vqrdmlahq_n_u16, vqdmlahq_n_u16, vmvnq_m_u16, vmlasq_n_u16, vmlaq_n_u16, vmladavq_p_u16, vmladavaq_u16, vminvq_p_u16, vmaxvq_p_u16, vdupq_m_n_u16, vcmpneq_m_u16, vcmpneq_m_n_u16, vcmphiq_m_u16, vcmphiq_m_n_u16, vcmpeqq_m_u16, vcmpeqq_m_n_u16, vcmpcsq_m_u16, vcmpcsq_m_n_u16, vclzq_m_u16, vaddvaq_p_u16, vsriq_n_u16, vsliq_n_u16, vshlq_m_r_u16, vrshlq_m_n_u16, vqshlq_m_r_u16, vqrshlq_m_n_u16, vminavq_p_s16, vminaq_m_s16, vmaxavq_p_s16, vmaxaq_m_s16, vcmpneq_m_s16, vcmpneq_m_n_s16, vcmpltq_m_s16, vcmpltq_m_n_s16, vcmpleq_m_s16, vcmpleq_m_n_s16, vcmpgtq_m_s16, vcmpgtq_m_n_s16, vcmpgeq_m_s16, vcmpgeq_m_n_s16, vcmpeqq_m_s16, vcmpeqq_m_n_s16, vshlq_m_r_s16, vrshlq_m_n_s16, vrev64q_m_s16, vqshlq_m_r_s16, vqrshlq_m_n_s16, vqnegq_m_s16, vqabsq_m_s16, vnegq_m_s16, vmvnq_m_s16, vmlsdavxq_p_s16, vmlsdavq_p_s16, vmladavxq_p_s16, vmladavq_p_s16, vminvq_p_s16, vmaxvq_p_s16, vdupq_m_n_s16, vclzq_m_s16, vclsq_m_s16, vaddvaq_p_s16, vabsq_m_s16, vqrdmlsdhxq_s16, vqrdmlsdhq_s16, vqrdmlashq_n_s16, vqrdmlahq_n_s16, vqrdmladhxq_s16, vqrdmladhq_s16, vqdmlsdhxq_s16, vqdmlsdhq_s16, vqdmlahq_n_s16, vqdmladhxq_s16, vqdmladhq_s16, vmlsdavaxq_s16, vmlsdavaq_s16, vmlasq_n_s16, vmlaq_n_s16, vmladavaxq_s16, vmladavaq_s16, vsriq_n_s16, vsliq_n_s16, vpselq_u32, vpselq_s32, vrev64q_m_u32, vqrdmlashq_n_u32, vqrdmlahq_n_u32, vqdmlahq_n_u32, vmvnq_m_u32, vmlasq_n_u32, vmlaq_n_u32, vmladavq_p_u32, vmladavaq_u32, vminvq_p_u32, vmaxvq_p_u32, vdupq_m_n_u32, vcmpneq_m_u32, vcmpneq_m_n_u32, vcmphiq_m_u32, vcmphiq_m_n_u32, vcmpeqq_m_u32, vcmpeqq_m_n_u32, vcmpcsq_m_u32, vcmpcsq_m_n_u32, vclzq_m_u32, vaddvaq_p_u32, vsriq_n_u32, vsliq_n_u32, vshlq_m_r_u32, vrshlq_m_n_u32, vqshlq_m_r_u32, vqrshlq_m_n_u32, vminavq_p_s32, vminaq_m_s32, vmaxavq_p_s32, vmaxaq_m_s32, vcmpneq_m_s32, vcmpneq_m_n_s32, vcmpltq_m_s32, vcmpltq_m_n_s32, vcmpleq_m_s32, vcmpleq_m_n_s32, vcmpgtq_m_s32, vcmpgtq_m_n_s32, vcmpgeq_m_s32, vcmpgeq_m_n_s32, vcmpeqq_m_s32, vcmpeqq_m_n_s32, vshlq_m_r_s32, vrshlq_m_n_s32, vrev64q_m_s32, vqshlq_m_r_s32, vqrshlq_m_n_s32, vqnegq_m_s32, vqabsq_m_s32, vnegq_m_s32, vmvnq_m_s32, vmlsdavxq_p_s32, vmlsdavq_p_s32, vmladavxq_p_s32, vmladavq_p_s32, vminvq_p_s32, vmaxvq_p_s32, vdupq_m_n_s32, vclzq_m_s32, vclsq_m_s32, vaddvaq_p_s32, vabsq_m_s32, vqrdmlsdhxq_s32, vqrdmlsdhq_s32, vqrdmlashq_n_s32, vqrdmlahq_n_s32, vqrdmladhxq_s32, vqrdmladhq_s32, vqdmlsdhxq_s32, vqdmlsdhq_s32, vqdmlahq_n_s32, vqdmladhxq_s32, vqdmladhq_s32, vmlsdavaxq_s32, vmlsdavaq_s32, vmlasq_n_s32, vmlaq_n_s32, vmladavaxq_s32, vmladavaq_s32, vsriq_n_s32, vsliq_n_s32, vpselq_u64, vpselq_s64.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

In this patch new constraints "Rc" and "Re" are added, which checks the constant is with in the range of 0 to 15 and 0 to 31 respectively.

Also a new predicates "mve_imm_15" and "mve_imm_31" are added, to check the the matching constraint Rc and Re respectively.

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vpselq_u8): Define macro.
	(vpselq_s8): Likewise.
	(vrev64q_m_u8): Likewise.
	(vqrdmlashq_n_u8): Likewise.
	(vqrdmlahq_n_u8): Likewise.
	(vqdmlahq_n_u8): Likewise.
	(vmvnq_m_u8): Likewise.
	(vmlasq_n_u8): Likewise.
	(vmlaq_n_u8): Likewise.
	(vmladavq_p_u8): Likewise.
	(vmladavaq_u8): Likewise.
	(vminvq_p_u8): Likewise.
	(vmaxvq_p_u8): Likewise.
	(vdupq_m_n_u8): Likewise.
	(vcmpneq_m_u8): Likewise.
	(vcmpneq_m_n_u8): Likewise.
	(vcmphiq_m_u8): Likewise.
	(vcmphiq_m_n_u8): Likewise.
	(vcmpeqq_m_u8): Likewise.
	(vcmpeqq_m_n_u8): Likewise.
	(vcmpcsq_m_u8): Likewise.
	(vcmpcsq_m_n_u8): Likewise.
	(vclzq_m_u8): Likewise.
	(vaddvaq_p_u8): Likewise.
	(vsriq_n_u8): Likewise.
	(vsliq_n_u8): Likewise.
	(vshlq_m_r_u8): Likewise.
	(vrshlq_m_n_u8): Likewise.
	(vqshlq_m_r_u8): Likewise.
	(vqrshlq_m_n_u8): Likewise.
	(vminavq_p_s8): Likewise.
	(vminaq_m_s8): Likewise.
	(vmaxavq_p_s8): Likewise.
	(vmaxaq_m_s8): Likewise.
	(vcmpneq_m_s8): Likewise.
	(vcmpneq_m_n_s8): Likewise.
	(vcmpltq_m_s8): Likewise.
	(vcmpltq_m_n_s8): Likewise.
	(vcmpleq_m_s8): Likewise.
	(vcmpleq_m_n_s8): Likewise.
	(vcmpgtq_m_s8): Likewise.
	(vcmpgtq_m_n_s8): Likewise.
	(vcmpgeq_m_s8): Likewise.
	(vcmpgeq_m_n_s8): Likewise.
	(vcmpeqq_m_s8): Likewise.
	(vcmpeqq_m_n_s8): Likewise.
	(vshlq_m_r_s8): Likewise.
	(vrshlq_m_n_s8): Likewise.
	(vrev64q_m_s8): Likewise.
	(vqshlq_m_r_s8): Likewise.
	(vqrshlq_m_n_s8): Likewise.
	(vqnegq_m_s8): Likewise.
	(vqabsq_m_s8): Likewise.
	(vnegq_m_s8): Likewise.
	(vmvnq_m_s8): Likewise.
	(vmlsdavxq_p_s8): Likewise.
	(vmlsdavq_p_s8): Likewise.
	(vmladavxq_p_s8): Likewise.
	(vmladavq_p_s8): Likewise.
	(vminvq_p_s8): Likewise.
	(vmaxvq_p_s8): Likewise.
	(vdupq_m_n_s8): Likewise.
	(vclzq_m_s8): Likewise.
	(vclsq_m_s8): Likewise.
	(vaddvaq_p_s8): Likewise.
	(vabsq_m_s8): Likewise.
	(vqrdmlsdhxq_s8): Likewise.
	(vqrdmlsdhq_s8): Likewise.
	(vqrdmlashq_n_s8): Likewise.
	(vqrdmlahq_n_s8): Likewise.
	(vqrdmladhxq_s8): Likewise.
	(vqrdmladhq_s8): Likewise.
	(vqdmlsdhxq_s8): Likewise.
	(vqdmlsdhq_s8): Likewise.
	(vqdmlahq_n_s8): Likewise.
	(vqdmladhxq_s8): Likewise.
	(vqdmladhq_s8): Likewise.
	(vmlsdavaxq_s8): Likewise.
	(vmlsdavaq_s8): Likewise.
	(vmlasq_n_s8): Likewise.
	(vmlaq_n_s8): Likewise.
	(vmladavaxq_s8): Likewise.
	(vmladavaq_s8): Likewise.
	(vsriq_n_s8): Likewise.
	(vsliq_n_s8): Likewise.
	(vpselq_u16): Likewise.
	(vpselq_s16): Likewise.
	(vrev64q_m_u16): Likewise.
	(vqrdmlashq_n_u16): Likewise.
	(vqrdmlahq_n_u16): Likewise.
	(vqdmlahq_n_u16): Likewise.
	(vmvnq_m_u16): Likewise.
	(vmlasq_n_u16): Likewise.
	(vmlaq_n_u16): Likewise.
	(vmladavq_p_u16): Likewise.
	(vmladavaq_u16): Likewise.
	(vminvq_p_u16): Likewise.
	(vmaxvq_p_u16): Likewise.
	(vdupq_m_n_u16): Likewise.
	(vcmpneq_m_u16): Likewise.
	(vcmpneq_m_n_u16): Likewise.
	(vcmphiq_m_u16): Likewise.
	(vcmphiq_m_n_u16): Likewise.
	(vcmpeqq_m_u16): Likewise.
	(vcmpeqq_m_n_u16): Likewise.
	(vcmpcsq_m_u16): Likewise.
	(vcmpcsq_m_n_u16): Likewise.
	(vclzq_m_u16): Likewise.
	(vaddvaq_p_u16): Likewise.
	(vsriq_n_u16): Likewise.
	(vsliq_n_u16): Likewise.
	(vshlq_m_r_u16): Likewise.
	(vrshlq_m_n_u16): Likewise.
	(vqshlq_m_r_u16): Likewise.
	(vqrshlq_m_n_u16): Likewise.
	(vminavq_p_s16): Likewise.
	(vminaq_m_s16): Likewise.
	(vmaxavq_p_s16): Likewise.
	(vmaxaq_m_s16): Likewise.
	(vcmpneq_m_s16): Likewise.
	(vcmpneq_m_n_s16): Likewise.
	(vcmpltq_m_s16): Likewise.
	(vcmpltq_m_n_s16): Likewise.
	(vcmpleq_m_s16): Likewise.
	(vcmpleq_m_n_s16): Likewise.
	(vcmpgtq_m_s16): Likewise.
	(vcmpgtq_m_n_s16): Likewise.
	(vcmpgeq_m_s16): Likewise.
	(vcmpgeq_m_n_s16): Likewise.
	(vcmpeqq_m_s16): Likewise.
	(vcmpeqq_m_n_s16): Likewise.
	(vshlq_m_r_s16): Likewise.
	(vrshlq_m_n_s16): Likewise.
	(vrev64q_m_s16): Likewise.
	(vqshlq_m_r_s16): Likewise.
	(vqrshlq_m_n_s16): Likewise.
	(vqnegq_m_s16): Likewise.
	(vqabsq_m_s16): Likewise.
	(vnegq_m_s16): Likewise.
	(vmvnq_m_s16): Likewise.
	(vmlsdavxq_p_s16): Likewise.
	(vmlsdavq_p_s16): Likewise.
	(vmladavxq_p_s16): Likewise.
	(vmladavq_p_s16): Likewise.
	(vminvq_p_s16): Likewise.
	(vmaxvq_p_s16): Likewise.
	(vdupq_m_n_s16): Likewise.
	(vclzq_m_s16): Likewise.
	(vclsq_m_s16): Likewise.
	(vaddvaq_p_s16): Likewise.
	(vabsq_m_s16): Likewise.
	(vqrdmlsdhxq_s16): Likewise.
	(vqrdmlsdhq_s16): Likewise.
	(vqrdmlashq_n_s16): Likewise.
	(vqrdmlahq_n_s16): Likewise.
	(vqrdmladhxq_s16): Likewise.
	(vqrdmladhq_s16): Likewise.
	(vqdmlsdhxq_s16): Likewise.
	(vqdmlsdhq_s16): Likewise.
	(vqdmlahq_n_s16): Likewise.
	(vqdmladhxq_s16): Likewise.
	(vqdmladhq_s16): Likewise.
	(vmlsdavaxq_s16): Likewise.
	(vmlsdavaq_s16): Likewise.
	(vmlasq_n_s16): Likewise.
	(vmlaq_n_s16): Likewise.
	(vmladavaxq_s16): Likewise.
	(vmladavaq_s16): Likewise.
	(vsriq_n_s16): Likewise.
	(vsliq_n_s16): Likewise.
	(vpselq_u32): Likewise.
	(vpselq_s32): Likewise.
	(vrev64q_m_u32): Likewise.
	(vqrdmlashq_n_u32): Likewise.
	(vqrdmlahq_n_u32): Likewise.
	(vqdmlahq_n_u32): Likewise.
	(vmvnq_m_u32): Likewise.
	(vmlasq_n_u32): Likewise.
	(vmlaq_n_u32): Likewise.
	(vmladavq_p_u32): Likewise.
	(vmladavaq_u32): Likewise.
	(vminvq_p_u32): Likewise.
	(vmaxvq_p_u32): Likewise.
	(vdupq_m_n_u32): Likewise.
	(vcmpneq_m_u32): Likewise.
	(vcmpneq_m_n_u32): Likewise.
	(vcmphiq_m_u32): Likewise.
	(vcmphiq_m_n_u32): Likewise.
	(vcmpeqq_m_u32): Likewise.
	(vcmpeqq_m_n_u32): Likewise.
	(vcmpcsq_m_u32): Likewise.
	(vcmpcsq_m_n_u32): Likewise.
	(vclzq_m_u32): Likewise.
	(vaddvaq_p_u32): Likewise.
	(vsriq_n_u32): Likewise.
	(vsliq_n_u32): Likewise.
	(vshlq_m_r_u32): Likewise.
	(vrshlq_m_n_u32): Likewise.
	(vqshlq_m_r_u32): Likewise.
	(vqrshlq_m_n_u32): Likewise.
	(vminavq_p_s32): Likewise.
	(vminaq_m_s32): Likewise.
	(vmaxavq_p_s32): Likewise.
	(vmaxaq_m_s32): Likewise.
	(vcmpneq_m_s32): Likewise.
	(vcmpneq_m_n_s32): Likewise.
	(vcmpltq_m_s32): Likewise.
	(vcmpltq_m_n_s32): Likewise.
	(vcmpleq_m_s32): Likewise.
	(vcmpleq_m_n_s32): Likewise.
	(vcmpgtq_m_s32): Likewise.
	(vcmpgtq_m_n_s32): Likewise.
	(vcmpgeq_m_s32): Likewise.
	(vcmpgeq_m_n_s32): Likewise.
	(vcmpeqq_m_s32): Likewise.
	(vcmpeqq_m_n_s32): Likewise.
	(vshlq_m_r_s32): Likewise.
	(vrshlq_m_n_s32): Likewise.
	(vrev64q_m_s32): Likewise.
	(vqshlq_m_r_s32): Likewise.
	(vqrshlq_m_n_s32): Likewise.
	(vqnegq_m_s32): Likewise.
	(vqabsq_m_s32): Likewise.
	(vnegq_m_s32): Likewise.
	(vmvnq_m_s32): Likewise.
	(vmlsdavxq_p_s32): Likewise.
	(vmlsdavq_p_s32): Likewise.
	(vmladavxq_p_s32): Likewise.
	(vmladavq_p_s32): Likewise.
	(vminvq_p_s32): Likewise.
	(vmaxvq_p_s32): Likewise.
	(vdupq_m_n_s32): Likewise.
	(vclzq_m_s32): Likewise.
	(vclsq_m_s32): Likewise.
	(vaddvaq_p_s32): Likewise.
	(vabsq_m_s32): Likewise.
	(vqrdmlsdhxq_s32): Likewise.
	(vqrdmlsdhq_s32): Likewise.
	(vqrdmlashq_n_s32): Likewise.
	(vqrdmlahq_n_s32): Likewise.
	(vqrdmladhxq_s32): Likewise.
	(vqrdmladhq_s32): Likewise.
	(vqdmlsdhxq_s32): Likewise.
	(vqdmlsdhq_s32): Likewise.
	(vqdmlahq_n_s32): Likewise.
	(vqdmladhxq_s32): Likewise.
	(vqdmladhq_s32): Likewise.
	(vmlsdavaxq_s32): Likewise.
	(vmlsdavaq_s32): Likewise.
	(vmlasq_n_s32): Likewise.
	(vmlaq_n_s32): Likewise.
	(vmladavaxq_s32): Likewise.
	(vmladavaq_s32): Likewise.
	(vsriq_n_s32): Likewise.
	(vsliq_n_s32): Likewise.
	(vpselq_u64): Likewise.
	(vpselq_s64): Likewise.
	(__arm_vpselq_u8): Define intrinsic.
	(__arm_vpselq_s8): Likewise.
	(__arm_vrev64q_m_u8): Likewise.
	(__arm_vqrdmlashq_n_u8): Likewise.
	(__arm_vqrdmlahq_n_u8): Likewise.
	(__arm_vqdmlahq_n_u8): Likewise.
	(__arm_vmvnq_m_u8): Likewise.
	(__arm_vmlasq_n_u8): Likewise.
	(__arm_vmlaq_n_u8): Likewise.
	(__arm_vmladavq_p_u8): Likewise.
	(__arm_vmladavaq_u8): Likewise.
	(__arm_vminvq_p_u8): Likewise.
	(__arm_vmaxvq_p_u8): Likewise.
	(__arm_vdupq_m_n_u8): Likewise.
	(__arm_vcmpneq_m_u8): Likewise.
	(__arm_vcmpneq_m_n_u8): Likewise.
	(__arm_vcmphiq_m_u8): Likewise.
	(__arm_vcmphiq_m_n_u8): Likewise.
	(__arm_vcmpeqq_m_u8): Likewise.
	(__arm_vcmpeqq_m_n_u8): Likewise.
	(__arm_vcmpcsq_m_u8): Likewise.
	(__arm_vcmpcsq_m_n_u8): Likewise.
	(__arm_vclzq_m_u8): Likewise.
	(__arm_vaddvaq_p_u8): Likewise.
	(__arm_vsriq_n_u8): Likewise.
	(__arm_vsliq_n_u8): Likewise.
	(__arm_vshlq_m_r_u8): Likewise.
	(__arm_vrshlq_m_n_u8): Likewise.
	(__arm_vqshlq_m_r_u8): Likewise.
	(__arm_vqrshlq_m_n_u8): Likewise.
	(__arm_vminavq_p_s8): Likewise.
	(__arm_vminaq_m_s8): Likewise.
	(__arm_vmaxavq_p_s8): Likewise.
	(__arm_vmaxaq_m_s8): Likewise.
	(__arm_vcmpneq_m_s8): Likewise.
	(__arm_vcmpneq_m_n_s8): Likewise.
	(__arm_vcmpltq_m_s8): Likewise.
	(__arm_vcmpltq_m_n_s8): Likewise.
	(__arm_vcmpleq_m_s8): Likewise.
	(__arm_vcmpleq_m_n_s8): Likewise.
	(__arm_vcmpgtq_m_s8): Likewise.
	(__arm_vcmpgtq_m_n_s8): Likewise.
	(__arm_vcmpgeq_m_s8): Likewise.
	(__arm_vcmpgeq_m_n_s8): Likewise.
	(__arm_vcmpeqq_m_s8): Likewise.
	(__arm_vcmpeqq_m_n_s8): Likewise.
	(__arm_vshlq_m_r_s8): Likewise.
	(__arm_vrshlq_m_n_s8): Likewise.
	(__arm_vrev64q_m_s8): Likewise.
	(__arm_vqshlq_m_r_s8): Likewise.
	(__arm_vqrshlq_m_n_s8): Likewise.
	(__arm_vqnegq_m_s8): Likewise.
	(__arm_vqabsq_m_s8): Likewise.
	(__arm_vnegq_m_s8): Likewise.
	(__arm_vmvnq_m_s8): Likewise.
	(__arm_vmlsdavxq_p_s8): Likewise.
	(__arm_vmlsdavq_p_s8): Likewise.
	(__arm_vmladavxq_p_s8): Likewise.
	(__arm_vmladavq_p_s8): Likewise.
	(__arm_vminvq_p_s8): Likewise.
	(__arm_vmaxvq_p_s8): Likewise.
	(__arm_vdupq_m_n_s8): Likewise.
	(__arm_vclzq_m_s8): Likewise.
	(__arm_vclsq_m_s8): Likewise.
	(__arm_vaddvaq_p_s8): Likewise.
	(__arm_vabsq_m_s8): Likewise.
	(__arm_vqrdmlsdhxq_s8): Likewise.
	(__arm_vqrdmlsdhq_s8): Likewise.
	(__arm_vqrdmlashq_n_s8): Likewise.
	(__arm_vqrdmlahq_n_s8): Likewise.
	(__arm_vqrdmladhxq_s8): Likewise.
	(__arm_vqrdmladhq_s8): Likewise.
	(__arm_vqdmlsdhxq_s8): Likewise.
	(__arm_vqdmlsdhq_s8): Likewise.
	(__arm_vqdmlahq_n_s8): Likewise.
	(__arm_vqdmladhxq_s8): Likewise.
	(__arm_vqdmladhq_s8): Likewise.
	(__arm_vmlsdavaxq_s8): Likewise.
	(__arm_vmlsdavaq_s8): Likewise.
	(__arm_vmlasq_n_s8): Likewise.
	(__arm_vmlaq_n_s8): Likewise.
	(__arm_vmladavaxq_s8): Likewise.
	(__arm_vmladavaq_s8): Likewise.
	(__arm_vsriq_n_s8): Likewise.
	(__arm_vsliq_n_s8): Likewise.
	(__arm_vpselq_u16): Likewise.
	(__arm_vpselq_s16): Likewise.
	(__arm_vrev64q_m_u16): Likewise.
	(__arm_vqrdmlashq_n_u16): Likewise.
	(__arm_vqrdmlahq_n_u16): Likewise.
	(__arm_vqdmlahq_n_u16): Likewise.
	(__arm_vmvnq_m_u16): Likewise.
	(__arm_vmlasq_n_u16): Likewise.
	(__arm_vmlaq_n_u16): Likewise.
	(__arm_vmladavq_p_u16): Likewise.
	(__arm_vmladavaq_u16): Likewise.
	(__arm_vminvq_p_u16): Likewise.
	(__arm_vmaxvq_p_u16): Likewise.
	(__arm_vdupq_m_n_u16): Likewise.
	(__arm_vcmpneq_m_u16): Likewise.
	(__arm_vcmpneq_m_n_u16): Likewise.
	(__arm_vcmphiq_m_u16): Likewise.
	(__arm_vcmphiq_m_n_u16): Likewise.
	(__arm_vcmpeqq_m_u16): Likewise.
	(__arm_vcmpeqq_m_n_u16): Likewise.
	(__arm_vcmpcsq_m_u16): Likewise.
	(__arm_vcmpcsq_m_n_u16): Likewise.
	(__arm_vclzq_m_u16): Likewise.
	(__arm_vaddvaq_p_u16): Likewise.
	(__arm_vsriq_n_u16): Likewise.
	(__arm_vsliq_n_u16): Likewise.
	(__arm_vshlq_m_r_u16): Likewise.
	(__arm_vrshlq_m_n_u16): Likewise.
	(__arm_vqshlq_m_r_u16): Likewise.
	(__arm_vqrshlq_m_n_u16): Likewise.
	(__arm_vminavq_p_s16): Likewise.
	(__arm_vminaq_m_s16): Likewise.
	(__arm_vmaxavq_p_s16): Likewise.
	(__arm_vmaxaq_m_s16): Likewise.
	(__arm_vcmpneq_m_s16): Likewise.
	(__arm_vcmpneq_m_n_s16): Likewise.
	(__arm_vcmpltq_m_s16): Likewise.
	(__arm_vcmpltq_m_n_s16): Likewise.
	(__arm_vcmpleq_m_s16): Likewise.
	(__arm_vcmpleq_m_n_s16): Likewise.
	(__arm_vcmpgtq_m_s16): Likewise.
	(__arm_vcmpgtq_m_n_s16): Likewise.
	(__arm_vcmpgeq_m_s16): Likewise.
	(__arm_vcmpgeq_m_n_s16): Likewise.
	(__arm_vcmpeqq_m_s16): Likewise.
	(__arm_vcmpeqq_m_n_s16): Likewise.
	(__arm_vshlq_m_r_s16): Likewise.
	(__arm_vrshlq_m_n_s16): Likewise.
	(__arm_vrev64q_m_s16): Likewise.
	(__arm_vqshlq_m_r_s16): Likewise.
	(__arm_vqrshlq_m_n_s16): Likewise.
	(__arm_vqnegq_m_s16): Likewise.
	(__arm_vqabsq_m_s16): Likewise.
	(__arm_vnegq_m_s16): Likewise.
	(__arm_vmvnq_m_s16): Likewise.
	(__arm_vmlsdavxq_p_s16): Likewise.
	(__arm_vmlsdavq_p_s16): Likewise.
	(__arm_vmladavxq_p_s16): Likewise.
	(__arm_vmladavq_p_s16): Likewise.
	(__arm_vminvq_p_s16): Likewise.
	(__arm_vmaxvq_p_s16): Likewise.
	(__arm_vdupq_m_n_s16): Likewise.
	(__arm_vclzq_m_s16): Likewise.
	(__arm_vclsq_m_s16): Likewise.
	(__arm_vaddvaq_p_s16): Likewise.
	(__arm_vabsq_m_s16): Likewise.
	(__arm_vqrdmlsdhxq_s16): Likewise.
	(__arm_vqrdmlsdhq_s16): Likewise.
	(__arm_vqrdmlashq_n_s16): Likewise.
	(__arm_vqrdmlahq_n_s16): Likewise.
	(__arm_vqrdmladhxq_s16): Likewise.
	(__arm_vqrdmladhq_s16): Likewise.
	(__arm_vqdmlsdhxq_s16): Likewise.
	(__arm_vqdmlsdhq_s16): Likewise.
	(__arm_vqdmlahq_n_s16): Likewise.
	(__arm_vqdmladhxq_s16): Likewise.
	(__arm_vqdmladhq_s16): Likewise.
	(__arm_vmlsdavaxq_s16): Likewise.
	(__arm_vmlsdavaq_s16): Likewise.
	(__arm_vmlasq_n_s16): Likewise.
	(__arm_vmlaq_n_s16): Likewise.
	(__arm_vmladavaxq_s16): Likewise.
	(__arm_vmladavaq_s16): Likewise.
	(__arm_vsriq_n_s16): Likewise.
	(__arm_vsliq_n_s16): Likewise.
	(__arm_vpselq_u32): Likewise.
	(__arm_vpselq_s32): Likewise.
	(__arm_vrev64q_m_u32): Likewise.
	(__arm_vqrdmlashq_n_u32): Likewise.
	(__arm_vqrdmlahq_n_u32): Likewise.
	(__arm_vqdmlahq_n_u32): Likewise.
	(__arm_vmvnq_m_u32): Likewise.
	(__arm_vmlasq_n_u32): Likewise.
	(__arm_vmlaq_n_u32): Likewise.
	(__arm_vmladavq_p_u32): Likewise.
	(__arm_vmladavaq_u32): Likewise.
	(__arm_vminvq_p_u32): Likewise.
	(__arm_vmaxvq_p_u32): Likewise.
	(__arm_vdupq_m_n_u32): Likewise.
	(__arm_vcmpneq_m_u32): Likewise.
	(__arm_vcmpneq_m_n_u32): Likewise.
	(__arm_vcmphiq_m_u32): Likewise.
	(__arm_vcmphiq_m_n_u32): Likewise.
	(__arm_vcmpeqq_m_u32): Likewise.
	(__arm_vcmpeqq_m_n_u32): Likewise.
	(__arm_vcmpcsq_m_u32): Likewise.
	(__arm_vcmpcsq_m_n_u32): Likewise.
	(__arm_vclzq_m_u32): Likewise.
	(__arm_vaddvaq_p_u32): Likewise.
	(__arm_vsriq_n_u32): Likewise.
	(__arm_vsliq_n_u32): Likewise.
	(__arm_vshlq_m_r_u32): Likewise.
	(__arm_vrshlq_m_n_u32): Likewise.
	(__arm_vqshlq_m_r_u32): Likewise.
	(__arm_vqrshlq_m_n_u32): Likewise.
	(__arm_vminavq_p_s32): Likewise.
	(__arm_vminaq_m_s32): Likewise.
	(__arm_vmaxavq_p_s32): Likewise.
	(__arm_vmaxaq_m_s32): Likewise.
	(__arm_vcmpneq_m_s32): Likewise.
	(__arm_vcmpneq_m_n_s32): Likewise.
	(__arm_vcmpltq_m_s32): Likewise.
	(__arm_vcmpltq_m_n_s32): Likewise.
	(__arm_vcmpleq_m_s32): Likewise.
	(__arm_vcmpleq_m_n_s32): Likewise.
	(__arm_vcmpgtq_m_s32): Likewise.
	(__arm_vcmpgtq_m_n_s32): Likewise.
	(__arm_vcmpgeq_m_s32): Likewise.
	(__arm_vcmpgeq_m_n_s32): Likewise.
	(__arm_vcmpeqq_m_s32): Likewise.
	(__arm_vcmpeqq_m_n_s32): Likewise.
	(__arm_vshlq_m_r_s32): Likewise.
	(__arm_vrshlq_m_n_s32): Likewise.
	(__arm_vrev64q_m_s32): Likewise.
	(__arm_vqshlq_m_r_s32): Likewise.
	(__arm_vqrshlq_m_n_s32): Likewise.
	(__arm_vqnegq_m_s32): Likewise.
	(__arm_vqabsq_m_s32): Likewise.
	(__arm_vnegq_m_s32): Likewise.
	(__arm_vmvnq_m_s32): Likewise.
	(__arm_vmlsdavxq_p_s32): Likewise.
	(__arm_vmlsdavq_p_s32): Likewise.
	(__arm_vmladavxq_p_s32): Likewise.
	(__arm_vmladavq_p_s32): Likewise.
	(__arm_vminvq_p_s32): Likewise.
	(__arm_vmaxvq_p_s32): Likewise.
	(__arm_vdupq_m_n_s32): Likewise.
	(__arm_vclzq_m_s32): Likewise.
	(__arm_vclsq_m_s32): Likewise.
	(__arm_vaddvaq_p_s32): Likewise.
	(__arm_vabsq_m_s32): Likewise.
	(__arm_vqrdmlsdhxq_s32): Likewise.
	(__arm_vqrdmlsdhq_s32): Likewise.
	(__arm_vqrdmlashq_n_s32): Likewise.
	(__arm_vqrdmlahq_n_s32): Likewise.
	(__arm_vqrdmladhxq_s32): Likewise.
	(__arm_vqrdmladhq_s32): Likewise.
	(__arm_vqdmlsdhxq_s32): Likewise.
	(__arm_vqdmlsdhq_s32): Likewise.
	(__arm_vqdmlahq_n_s32): Likewise.
	(__arm_vqdmladhxq_s32): Likewise.
	(__arm_vqdmladhq_s32): Likewise.
	(__arm_vmlsdavaxq_s32): Likewise.
	(__arm_vmlsdavaq_s32): Likewise.
	(__arm_vmlasq_n_s32): Likewise.
	(__arm_vmlaq_n_s32): Likewise.
	(__arm_vmladavaxq_s32): Likewise.
	(__arm_vmladavaq_s32): Likewise.
	(__arm_vsriq_n_s32): Likewise.
	(__arm_vsliq_n_s32): Likewise.
	(__arm_vpselq_u64): Likewise.
	(__arm_vpselq_s64): Likewise.
	(vcmpneq_m_n): Define polymorphic variant.
	(vcmpneq_m): Likewise.
	(vqrdmlsdhq): Likewise.
	(vqrdmlsdhxq): Likewise.
	(vqrshlq_m_n): Likewise.
	(vqshlq_m_r): Likewise.
	(vrev64q_m): Likewise.
	(vrshlq_m_n): Likewise.
	(vshlq_m_r): Likewise.
	(vsliq_n): Likewise.
	(vsriq_n): Likewise.
	(vqrdmlashq_n): Likewise.
	(vqrdmlahq): Likewise.
	(vqrdmladhxq): Likewise.
	(vqrdmladhq): Likewise.
	(vqnegq_m): Likewise.
	(vqdmlsdhxq): Likewise.
	(vabsq_m): Likewise.
	(vclsq_m): Likewise.
	(vclzq_m): Likewise.
	(vcmpgeq_m): Likewise.
	(vcmpgeq_m_n): Likewise.
	(vdupq_m_n): Likewise.
	(vmaxaq_m): Likewise.
	(vmlaq_n): Likewise.
	(vmlasq_n): Likewise.
	(vmvnq_m): Likewise.
	(vnegq_m): Likewise.
	(vpselq): Likewise.
	(vqdmlahq_n): Likewise.
	(vqrdmlahq_n): Likewise.
	(vqdmlsdhq): Likewise.
	(vqdmladhq): Likewise.
	(vqabsq_m): Likewise.
	(vminaq_m): Likewise.
	(vrmlaldavhaq): Likewise.
	(vmlsdavxq_p): Likewise.
	(vmlsdavq_p): Likewise.
	(vmlsdavaxq): Likewise.
	(vmlsdavaq): Likewise.
	(vaddvaq_p): Likewise.
	(vcmpcsq_m_n): Likewise.
	(vcmpcsq_m): Likewise.
	(vcmpeqq_m_n): Likewise.
	(vcmpeqq_m): Likewise.
	(vmladavxq_p): Likewise.
	(vmladavq_p): Likewise.
	(vmladavaxq): Likewise.
	(vmladavaq): Likewise.
	(vminvq_p): Likewise.
	(vminavq_p): Likewise.
	(vmaxvq_p): Likewise.
	(vmaxavq_p): Likewise.
	(vcmpltq_m_n): Likewise.
	(vcmpltq_m): Likewise.
	(vcmpleq_m): Likewise.
	(vcmpleq_m_n): Likewise.
	(vcmphiq_m_n): Likewise.
	(vcmphiq_m): Likewise.
	(vcmpgtq_m_n): Likewise.
	(vcmpgtq_m): Likewise.
	* config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
	builtin qualifier.
	(TERNOP_NONE_NONE_NONE_NONE): Likewise.
	(TERNOP_NONE_NONE_NONE_UNONE): Likewise.
	(TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
	(TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
	* config/arm/constraints.md (Rc): Define constraint to check constant is
	in the range of 0 to 15.
	(Re): Define constraint to check constant is in the range of 0 to 31.
	* config/arm/mve.md (VADDVAQ_P): Define iterator.
	(VCLZQ_M): Likewise.
	(VCMPEQQ_M_N): Likewise.
	(VCMPEQQ_M): Likewise.
	(VCMPNEQ_M_N): Likewise.
	(VCMPNEQ_M): Likewise.
	(VDUPQ_M_N): Likewise.
	(VMAXVQ_P): Likewise.
	(VMINVQ_P): Likewise.
	(VMLADAVAQ): Likewise.
	(VMLADAVQ_P): Likewise.
	(VMLAQ_N): Likewise.
	(VMLASQ_N): Likewise.
	(VMVNQ_M): Likewise.
	(VPSELQ): Likewise.
	(VQDMLAHQ_N): Likewise.
	(VQRDMLAHQ_N): Likewise.
	(VQRDMLASHQ_N): Likewise.
	(VQRSHLQ_M_N): Likewise.
	(VQSHLQ_M_R): Likewise.
	(VREV64Q_M): Likewise.
	(VRSHLQ_M_N): Likewise.
	(VSHLQ_M_R): Likewise.
	(VSLIQ_N): Likewise.
	(VSRIQ_N): Likewise.
	(mve_vabsq_m_s<mode>): Define RTL pattern.
	(mve_vaddvaq_p_<supf><mode>): Likewise.
	(mve_vclsq_m_s<mode>): Likewise.
	(mve_vclzq_m_<supf><mode>): Likewise.
	(mve_vcmpcsq_m_n_u<mode>): Likewise.
	(mve_vcmpcsq_m_u<mode>): Likewise.
	(mve_vcmpeqq_m_n_<supf><mode>): Likewise.
	(mve_vcmpeqq_m_<supf><mode>): Likewise.
	(mve_vcmpgeq_m_n_s<mode>): Likewise.
	(mve_vcmpgeq_m_s<mode>): Likewise.
	(mve_vcmpgtq_m_n_s<mode>): Likewise.
	(mve_vcmpgtq_m_s<mode>): Likewise.
	(mve_vcmphiq_m_n_u<mode>): Likewise.
	(mve_vcmphiq_m_u<mode>): Likewise.
	(mve_vcmpleq_m_n_s<mode>): Likewise.
	(mve_vcmpleq_m_s<mode>): Likewise.
	(mve_vcmpltq_m_n_s<mode>): Likewise.
	(mve_vcmpltq_m_s<mode>): Likewise.
	(mve_vcmpneq_m_n_<supf><mode>): Likewise.
	(mve_vcmpneq_m_<supf><mode>): Likewise.
	(mve_vdupq_m_n_<supf><mode>): Likewise.
	(mve_vmaxaq_m_s<mode>): Likewise.
	(mve_vmaxavq_p_s<mode>): Likewise.
	(mve_vmaxvq_p_<supf><mode>): Likewise.
	(mve_vminaq_m_s<mode>): Likewise.
	(mve_vminavq_p_s<mode>): Likewise.
	(mve_vminvq_p_<supf><mode>): Likewise.
	(mve_vmladavaq_<supf><mode>): Likewise.
	(mve_vmladavq_p_<supf><mode>): Likewise.
	(mve_vmladavxq_p_s<mode>): Likewise.
	(mve_vmlaq_n_<supf><mode>): Likewise.
	(mve_vmlasq_n_<supf><mode>): Likewise.
	(mve_vmlsdavq_p_s<mode>): Likewise.
	(mve_vmlsdavxq_p_s<mode>): Likewise.
	(mve_vmvnq_m_<supf><mode>): Likewise.
	(mve_vnegq_m_s<mode>): Likewise.
	(mve_vpselq_<supf><mode>): Likewise.
	(mve_vqabsq_m_s<mode>): Likewise.
	(mve_vqdmlahq_n_<supf><mode>): Likewise.
	(mve_vqnegq_m_s<mode>): Likewise.
	(mve_vqrdmladhq_s<mode>): Likewise.
	(mve_vqrdmladhxq_s<mode>): Likewise.
	(mve_vqrdmlahq_n_<supf><mode>): Likewise.
	(mve_vqrdmlashq_n_<supf><mode>): Likewise.
	(mve_vqrdmlsdhq_s<mode>): Likewise.
	(mve_vqrdmlsdhxq_s<mode>): Likewise.
	(mve_vqrshlq_m_n_<supf><mode>): Likewise.
	(mve_vqshlq_m_r_<supf><mode>): Likewise.
	(mve_vrev64q_m_<supf><mode>): Likewise.
	(mve_vrshlq_m_n_<supf><mode>): Likewise.
	(mve_vshlq_m_r_<supf><mode>): Likewise.
	(mve_vsliq_n_<supf><mode>): Likewise.
	(mve_vsriq_n_<supf><mode>): Likewise.
	(mve_vqdmlsdhxq_s<mode>): Likewise.
	(mve_vqdmlsdhq_s<mode>): Likewise.
	(mve_vqdmladhxq_s<mode>): Likewise.
	(mve_vqdmladhq_s<mode>): Likewise.
	(mve_vmlsdavaxq_s<mode>): Likewise.
	(mve_vmlsdavaq_s<mode>): Likewise.
	(mve_vmladavaxq_s<mode>): Likewise.
	* config/arm/predicates.md (mve_imm_15):Define predicate to check the
	matching constraint Rc.
	(mve_imm_31): Define predicate to check	the matching constraint Re.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise.