Updated merge conflict'

.gitignore

-Flows/*/*/run/*/
\ No newline at end of file
+Flows/*/*/run/*/
+Flows/job

Flows/ASAP7/mempool_tile/constraints/mempool_tile_wrap.sdc

@@ -1299,4 +1299,4 @@ set_clock_uncertainty -setup 0.08 [get_clocks clk_i]
 set_clock_uncertainty -hold 0.08 [get_clocks clk_i]
 set_clock_latency  0.07 [get_clocks vclk_i]
 ## List of unsupported SDC commands ##
-set_critical_range 0.100 [current_design]
+#set_critical_range 0.100 [current_design]

Flows/NanGate45/mempool_tile/constraints/mempool_tile_wrap.sdc

@@ -20,7 +20,7 @@ set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
 
 # Create virtual clock.
 create_clock -name "vclk_i" -period $clock_cycle
-set_clock_uncertainty $clk_uncertainty [get_clocks vclk_i]
+set_clock_uncertainty $uncertainty [get_clocks vclk_i]
 set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
 set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
 
@@ -34,26 +34,26 @@ set_max_fanout $maxFanout [current_design]
 set_false_path -from tile_id_i
 
 # TCDM Master
-set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_master_*req_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*req_*"]
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
 
-set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_master_*resp_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*resp_*"]
+set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
 
 # TCDM Slave
-set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_slave_*req_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*req_*"]
+set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
 
-set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_slave_*resp_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
 
 # Refill port
-set_input_delay  [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ refill_*"] 
-set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ refill_*"]
+#set_input_delay  [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ refill_*"] 
+#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
 
 # Reset
 set_input_delay  [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
 
 # Critical range
 # Depending on the synthesis tool used, this can be helpful.
-set_critical_range 0.100 [current_design]
+#set_critical_range 0.100 [current_design]

Flows/SKY130HD/mempool_tile/constraints/mempool_tile_wrap.sdc

@@ -56,4 +56,4 @@ set_input_delay  [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
 
 # Critical range
 # Depending on the synthesis tool used, this can be helpful.
-set_critical_range 0.100 [current_design]
+#set_critical_range 0.100 [current_design]

Flows/util/genJobList.py

@@ -2,32 +2,27 @@ import os
 import shutil
 import fileinput
 import re
-from datetime import datetime
+import time
 
 testcases = ['ariane136', 'ariane133', 'mempool_tile', 'nvdla']
 enablements = ['NanGate45', 'ASAP7']
 flows = [1, 2]
 job_file = "all_jobs"
-tnow = datetime.now()
-suffix = f'{tnow.month}{tnow.day}{tnow.year}_{tnow.hour}{tnow.minute}{tnow.second}'
-
 
 fp = open(job_file, "w")
+run_dir_name= f"run-{time.strftime('%Y%m%d-%H%M%S')}"
 for enablement in enablements:
   for testcase in testcases:
     for flow in flows:
       ## Check if the run directory exists
-      run_dir = f"./{enablement}/{testcase}/run"
+      run_dir = f"./{enablement}/{testcase}/{run_dir_name}"
+      print(run_dir)
       if not os.path.exists(run_dir):
         os.makedirs(run_dir)
       
       ## Copy the scripts
       scripts_src = f"./{enablement}/{testcase}/scripts/cadence"
-      
-      if suffix != "":
-        scripts_dst = f"./{enablement}/{testcase}/run/flow{flow}_{suffix}"
-      else:
-        scripts_dst = f"./{enablement}/{testcase}/run/flow{flow}"
+      scripts_dst = f"{run_dir}/flow{flow}"
       
       if os.path.exists(scripts_dst):
           print(f"For TestCase:{testcase} Enablement:{enablement} Flow:{flow}"