Merge branch 'main' of https://github.com/TILOS-AI-Institute/MacroPlacement into main

Enablements/ASAP7/README.md

 # ASAP7 (7.5T cell library (RVT only), FakeRAM2.0 memory generation)
+
+The Arizona State university's 7nm Predictive PDK (ASAP7) was developed at ASU in collaboration with ARM Research and it is available under BSD-3-Clause license.  
+
+As the ASAP7 enablement does not have memory generators, we use the FakeRAM2.0 memory generator available in the [FakeRAM2.0](https://github.com/ABKGroup/FakeRAM2.0) GitHub repo.
+
+With this combined enablement, testcases with SRAMs can be synthesized, placed and routed using both proprietary (commercial) tools such as Cadence Genus/Innovus, and open-source tools such as OpenROAD.
+
+The [*./lef*](./lef) directory contains the technology, standard cell and macro lef files, the [*./lib*](./lib/) directory contains the standard cell and macro liberty files and the [*./qrc*](./qrc/) directory contains the qrc technology file.

Enablements/ASAP7/lib/sram_asap7_64x256_1rw.lib

@@ -2,7 +2,7 @@ library(sram_asap7_64x256_1rw) {
     technology (cmos);
     delay_model : table_lookup;
     revision : 1.0;
-    date : "2022-06-13 17:29:18Z";
+    date : "2022-07-02 07:14:59Z";
     comment : "SRAM";
     time_unit : "1ns";
     voltage_unit : "1V";
@@ -383,77 +383,6 @@ cell(sram_asap7_64x256_1rw) {
             }
         }
     }
-    bus(w_mask_in)   {
-        bus_type : sram_asap7_64x256_1rw_DATA;
-        memory_write() {
-            address : addr_in;
-            clocked_on : "clk";
-        }
-        direction : input;
-        capacitance : 0.005;
-        timing() {
-            related_pin     : clk;
-            timing_type     : setup_rising ;
-            rise_constraint(sram_asap7_64x256_1rw_constraint_template) {
-                index_1 ("0.009, 0.227");
-                index_2 ("0.009, 0.227");
-                values ( \
-                  "0.050, 0.050", \
-                  "0.050, 0.050" \
-                )
-            }
-            fall_constraint(sram_asap7_64x256_1rw_constraint_template) {
-                index_1 ("0.009, 0.227");
-                index_2 ("0.009, 0.227");
-                values ( \
-                  "0.050, 0.050", \
-                  "0.050, 0.050" \
-                )
-            }
-        } 
-        timing() {
-            related_pin     : clk;
-            timing_type     : hold_rising ;
-            rise_constraint(sram_asap7_64x256_1rw_constraint_template) {
-                index_1 ("0.009, 0.227");
-                index_2 ("0.009, 0.227");
-                values ( \
-                  "0.050, 0.050", \
-                  "0.050, 0.050" \
-                )
-            }
-            fall_constraint(sram_asap7_64x256_1rw_constraint_template) {
-                index_1 ("0.009, 0.227");
-                index_2 ("0.009, 0.227");
-                values ( \
-                  "0.050, 0.050", \
-                  "0.050, 0.050" \
-                )
-            }
-        }
-        internal_power(){
-            when : "(! (we_in) )";
-            rise_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
-                index_1 ("0.009, 0.227");
-                values ("0.013, 0.013")
-            }
-            fall_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
-                index_1 ("0.009, 0.227");
-                values ("0.013, 0.013")
-            }
-        }
-        internal_power(){
-            when : "(we_in)";
-            rise_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
-                index_1 ("0.009, 0.227");
-                values ("0.013, 0.013")
-            }
-            fall_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
-                index_1 ("0.009, 0.227");
-                values ("0.013, 0.013")
-            }
-        }
-    }
     cell_leakage_power : 128.900;
 }
 

Enablements/NanGate45/README.md

@@ -6,4 +6,4 @@ As the FreePDK45/NanGate45 enablement does not have memory generators, we use th
 
 With this combined enablement, testcases with SRAMs can be synthesized, placed and routed using both proprietary (commercial) tools such as Cadence Genus/Innovus, and open-source tools such as OpenROAD.
 
- The [*./lef*](./lef) directory contains the technology, standard cell and macro lef files and the [*./lib*](./lib/) directory contains the standard cell and macro liberty files.
+ The [*./lef*](./lef) directory contains the technology, standard cell and macro lef files, the [*./lib*](./lib/) directory contains the standard cell and macro liberty files and the [*./qrc*](./qrc/) directory contains the qrc technology file.

Enablements/SKY130HD/README.md

+# SKY130HD FakeStack (SKY130HD library, bsg_fakeram memory generation, 9M FkaeStack)
+
+The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases.  
+
+In this enablement, each of the five routing layers and four cut layers have different lef properties (.e.g, minimum spacing, width, enclosure, etc.). Consider the five layers of the metal stack are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x<sub>1</sub>Ma_x<sub>2</sub>Mb_x<sub>3</sub>Mc_x<sub>4</sub>Md_1Me, where x<sub>i</sub> is greater or equal to one.  
+
+We use the bsg_fakeram memory generator available in the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) GitHub repo to generate the required SRAMs. The [sky130hd.cfg](./util/sky130hd.cfg) is the configuration file used to generate all the required memories.
+
+With this combined enablement, testcases with SRAMs can be synthesized, placed and routed using both proprietary (commercial) tools such as Cadence Genus/Innovus, and open-source tools such as OpenROAD.
+
+The [*./lef*](./lef) directory contains the technology, standard cell and macro lef files, the [*./lib*](./lib/) directory contains the standard cell and macro liberty files.
\ No newline at end of file

Enablements/SKY130HD/util/sky130hd.cfg

+{
+  # The process node. This is used to tell cacti what technology to use when
+  # estimating power, performance and area numbers.
+  "tech_nm": 130,
+
+  # The operating voltage.
+  "voltage": 1.8,
+
+  # String to add in front of every metal layer number for the layer name.
+  "metalPrefix": "met",
+
+  # The pin width for signal pins.
+  "pinWidth_nm": 460,
+
+  # The minimum pin pitch for signal pins (all pins will have a pitch that is a
+  # multuple of this pitch. The first pin will be a multiple of this pitch from
+  # the bottom edge of the macro too.
+  "pinPitch_nm": 460,
+
+  # Optional: snap the width and height of the sram to a multiple value.
+  "snapWidth_nm":  460,
+  "snapHeight_nm": 1360,
+
+  # Flips the pin orientations. Non-fliped assumes metal1 is vertical therefore
+  # supply pins on metal4 will be horizontal and signal pins will also be on
+  # metal4. If set to true, supply pins on metal4 will be vertical and signal
+  # pins will be on metal3.
+  "flipPins": true,
+
+  # List of SRAM configurations (name, width, depth, and banks)
+  "srams": [
+    {"name": "fakeram130_256x64", "width": 64, "depth":  256, "banks": 1},
+    {"name": "fakeram130_256x512", "width": 512, "depth":  256, "banks": 1},
+    {"name": "fakeram130_256x32", "width": 32, "depth":  256, "banks": 1},
+    {"name": "fakeram130_256x16", "width": 16, "depth":  256, "banks": 1},
+    {"name": "fakeram130_64x64", "width":  64, "depth": 64, "banks": 2}
+  ]
+}

Flows/ASAP7/ariane133/scripts/cadence/design_setup.tcl

@@ -4,8 +4,11 @@
 set DESIGN ariane 
 set sdc  ../../constraints/${DESIGN}.sdc
 
-# def file with die size and placed IO pins
-set floorplan_def ../../def/ariane133_fp_rows.def
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set floorplan_def ../../def/ariane133_fp_placed_macros.def
+} else {
+    set floorplan_def ../../def/ariane133_fp.def
+}
 #
 # Effort level during optimization in syn_generic -physical (or called generic) stage
 # possible values are : high, medium or low
@@ -14,3 +17,6 @@ set GEN_EFF medium
 # Effort level during optimization in syn_map -physical (or called mapping) stage
 # possible values are : high, medium or low
 set MAP_EFF high
+#
+set HALO_WIDTH 2
+set TOP_ROUTING_LAYER 7

Flows/ASAP7/ariane133/scripts/cadence/run.sh

@@ -6,6 +6,10 @@ module load genus/21.1
 module unload innovus
 module load innovus/21.1
 
+#
+# To run the Physical Synthesis (iSpatial) flow - flow2
+export PHY_SYNTH=1
+
 mkdir log -p
-genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
-innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
+genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
+innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl

Flows/ASAP7/ariane133/scripts/cadence/run_genus_hybrid.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_mmmc mmmc_iSpatial_setup.tcl
+}
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+    read_physical -lefs $lefs
+}
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set pathi
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    set_db library $list_lib
+}
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    read_sdc $sdc
+}
+
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_def $floorplan_def
+    check_floorplan -detailed
+}
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_generic -physical
+} else {
+    syn_generic
+}
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+ 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_map -physical
+} else {
+    syn_map
+}
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_opt -spatial
+} else {
+    syn_opt
+}
+
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+} else {
+    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+}
+
+exit

Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl

@@ -7,10 +7,12 @@ source mmmc_setup.tcl
 setMultiCpuUsage -localCpu 16
 set util 0.3
 
-set netlist "./syn_handoff/$DESIGN.v"
-set sdc "./syn_handoff/$DESIGN.sdc"
+set handoff_dir  "./syn_handoff"
 
-set site "asap7sc7p5t"
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
+
+set site "FreePDK45_38x28_10R_NP_162NW_34O"
 
 set rptDir summaryReport/ 
 set encDir enc/
@@ -39,7 +41,7 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
 set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
 
 set_interactive_constraint_modes {CON}
-setDesignMode -process 7
+setDesignMode -process 45
 
 clearGlobalNets
 globalNetConnect VDD -type pgpin -pin VDD -inst * -override
@@ -56,28 +58,22 @@ generateVias
 createBasicPathGroups -expanded
 
 ## Generate the floorplan ##
-#floorPlan -r 1.0 $util 10 10 10 10
-defIn $floorplan_def 
-
-## Macro Placement ##
-#redirect mp_config.tcl {source gen_mp_config.tcl}
-#proto_design -constraints mp_config.tcl 
-addHaloToBlock -allMacro 1 1 1 1
-setFPlanMode -snapBlockGrid LayerTrack
-place_design -concurrent_macros
-refine_macro_place
-snapFPlan -pin
-saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
-## Creating Pin Blcokage for lower and upper pin layers ##
-createPinBlkg -name Layer_1 -layer {M2 M3 M7 M8 M9 Pad} -edge 0
-createPinBlkg -name side_top -edge 1
-createPinBlkg -name side_right -edge 2
-createPinBlkg -name side_bottom -edge 3
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    defIn ${handoff_dir}/${DESIGN}.def
+} else {
+    defIn $floorplan_def
+    addHaloToBlock -allMacro $HALO_WIDTH  $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH 
+    place_design -concurrent_macros
+    refine_macro_place
+    snapFPlan -pin
+}
+
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 setPlaceMode -place_detail_legalization_inst_gap 1
 setFillerMode -fitGap true
-setDesignMode -topRoutingLayer 7
+setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER 
 setDesignMode -bottomRoutingLayer 2 
 
 place_opt_design -out_dir $rptDir -prefix place
@@ -121,7 +117,6 @@ routeDesign
 saveDesign ${encDir}/${DESIGN}_route.enc
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
-source fix_route_drc.tcl
 summaryReport -noHtml -outfile summaryReport/post_route.sum
 saveDesign ${encDir}/${DESIGN}.enc
 defOut -netlist -floorplan -routing ${DESIGN}.def

Flows/ASAP7/ariane136/scripts/cadence/design_setup.tcl

@@ -4,8 +4,11 @@
 set DESIGN ariane 
 set sdc  ../../constraints/${DESIGN}.sdc
 
-# def file with die size and placed IO pins
-set floorplan_def ../../def/ariane136_fp_rows.def
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set floorplan_def ../../def/ariane136_fp_placed_macros.def
+} else {
+    set floorplan_def ../../def/ariane136_fp.def
+}
 #
 # Effort level during optimization in syn_generic -physical (or called generic) stage
 # possible values are : high, medium or low
@@ -14,3 +17,6 @@ set GEN_EFF medium
 # Effort level during optimization in syn_map -physical (or called mapping) stage
 # possible values are : high, medium or low
 set MAP_EFF high
+#
+set HALO_WIDTH 1 
+set TOP_ROUTING_LAYER 7

Flows/ASAP7/ariane136/scripts/cadence/run.sh

@@ -6,6 +6,10 @@ module load genus/21.1
 module unload innovus
 module load innovus/21.1
 
+#
+# To run the Physical Synthesis (iSpatial) flow - flow2
+export PHY_SYNTH=1
+
 mkdir log -p
-genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
-innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
+genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
+innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl

Flows/ASAP7/ariane136/scripts/cadence/run_genus_hybrid.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_mmmc mmmc_iSpatial_setup.tcl
+}
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+    read_physical -lefs $lefs
+}
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set pathi
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    set_db library $list_lib
+}
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    read_sdc $sdc
+}
+
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_def $floorplan_def
+    check_floorplan -detailed
+}
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_generic -physical
+} else {
+    syn_generic
+}
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+ 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_map -physical
+} else {
+    syn_map
+}
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_opt -spatial
+} else {
+    syn_opt
+}
+
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+} else {
+    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+}
+
+exit

Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl

@@ -7,8 +7,10 @@ source mmmc_setup.tcl
 setMultiCpuUsage -localCpu 16
 set util 0.3
 
-set netlist "./syn_handoff/$DESIGN.v"
-set sdc "./syn_handoff/$DESIGN.sdc"
+set handoff_dir  "./syn_handoff"
+
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
 
 set site "asap7sc7p5t"
 
@@ -39,7 +41,7 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
 set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
 
 set_interactive_constraint_modes {CON}
-setDesignMode -process 7
+setDesignMode -process 7 
 
 clearGlobalNets
 globalNetConnect VDD -type pgpin -pin VDD -inst * -override
@@ -56,27 +58,22 @@ generateVias
 createBasicPathGroups -expanded
 
 ## Generate the floorplan ##
-#floorPlan -r 1.0 $util 10 10 10 10
-defIn $floorplan_def 
-
-## Macro Placement ##
-#redirect mp_config.tcl {source gen_mp_config.tcl}
-#proto_design -constraints mp_config.tcl 
-addHaloToBlock -allMacro 1 1 1 1
-place_design -concurrent_macros
-refine_macro_place
-snapFPlan -pin
-saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
-## Creating Pin Blcokage for lower and upper pin layers ##
-createPinBlkg -name Layer_1 -layer {M2 M3 M7 M8 M9 Pad} -edge 0
-createPinBlkg -name side_top -edge 1
-createPinBlkg -name side_right -edge 2
-createPinBlkg -name side_bottom -edge 3
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    defIn ${handoff_dir}/${DESIGN}.def
+} else {
+    defIn $floorplan_def
+    addHaloToBlock -allMacro $HALO_WIDTH  $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH 
+    place_design -concurrent_macros
+    refine_macro_place
+    snapFPlan -pin
+}
+
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 setPlaceMode -place_detail_legalization_inst_gap 1
 setFillerMode -fitGap true
-setDesignMode -topRoutingLayer 7
+setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER 
 setDesignMode -bottomRoutingLayer 2 
 
 place_opt_design -out_dir $rptDir -prefix place

Flows/ASAP7/nvdla/README.md

+# **Synthesis, Place \& Route (SP\&R):**
+Here we provide the setup to run SP&R of NVDLA design with 128 memory macros on ASAP7 using commercial and open-source tools.
+  - [**SP\&R Flow**](#spr-flow)
+    - [**Cadence tools**](#using-cadence-genus-and-innovus)
+
+## **SP\&R Flow:**
+We implement [NVDLA](../../../Testcases/nvdla/) on the ASAP7 platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/asap7). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the ASAP7 platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/ASAP7*](../../../Enablements/ASAP7/) directory.
+  
+  
+### **Using Cadence Genus and Innovus:**
+All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.  
+**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
+```
+genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
+```  
+We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.  
+  
+**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
+```
+innovus -64 -init run_invs.tcl -log log/run.log
+```
+
+Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow.  
+<img src="./screenshots/nvdla_Innovus_asap7.png" alt="nvdla_cadence" width="400"/>  
+
+This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+
+<!--
+### **Using OpenROAD-flow-scripts:**
+Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:  
+1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
+2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
+3. To launch the SP&R job go to the flow directory and use the below command
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
+  ```
+4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
+  ```  
+  
+Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.  
+<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
+-->
\ No newline at end of file

Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc

+# ===================================================================
+# File: syn/cons/NV_NVDLA_partition_c.sdc
+# NVDLA Open Source Project
+#
+# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; see the "LICENSE.txt" file that came
+# with this distribution for more information.
+# ===================================================================
+
+set_max_area 0
+set_ideal_network [get_ports direct_reset_]
+set_ideal_network [get_ports dla_reset_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
+set_ideal_network [get_ports test_mode]
+create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
+set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
+set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
+set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
+set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
+set_false_path   -from [get_ports direct_reset_]
+set_false_path   -from [get_ports dla_reset_rstn]
+set_false_path   -from [get_ports test_mode]
+set_false_path   -from [get_ports pwrbus_ram_pd*]
+set_false_path   -from [get_ports tmc2slcg_disable_clock_gating]
+set_false_path   -from [get_ports global_clk_ovr_on]
+set_false_path   -from [get_ports nvdla_clk_ovr_on]

Flows/ASAP7/nvdla/scripts/cadence/design_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+set DESIGN NV_NVDLA_partition_c
+set sdc  ../../constraints/${DESIGN}.sdc
+
+# def file with die size and placed IO pins
+set floorplan_def ../../def/${DESIGN}_fp.def
+
+set rtl_path ../../../../../Testcases/nvdla/rtl/
+
+#
+# Effort level during optimization in syn_generic -physical (or called generic) stage
+# possible values are : high, medium or low
+set GEN_EFF medium
+
+# Effort level during optimization in syn_map -physical (or called mapping) stage
+# possible values are : high, medium or low
+set MAP_EFF high

Flows/ASAP7/nvdla/scripts/cadence/lib_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+# lib and lef, RC setup
+
+set libdir "../../../../../Enablements/ASAP7/lib"
+set lefdir "../../../../../Enablements/ASAP7/lef"
+set qrcdir "../../../../../Enablements/ASAP7/qrc"
+
+set_db init_lib_search_path { \
+    ${libdir} \
+    ${lefdir} \
+}
+
+set libworst [glob ${libdir}/*.lib]
+
+set libbest $libworst
+
+set lefs "  
+    ${lefdir}/asap7_tech_1x_201209.lef \
+    ${lefdir}/asap7sc7p5t_27_R_1x_201211.lef \
+    ${lefdir}/sram_asap7_64x256_1rw.lef \
+    "
+
+set qrc_max "${qrcdir}/ASAP7.tch"
+set qrc_min "${qrcdir}/ASAP7.tch"
+#
+# Ensures proper and consistent library handling between Genus and Innovus
+#set_db library_setup_ispatial true

Flows/ASAP7/nvdla/scripts/cadence/mmmc_iSpatial_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
+#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
+ 
+create_timing_condition -name timing_wc  -library_sets { WC_LIB }
+create_timing_condition -name timing_bc  -library_sets { BC_LIB }
+ 
+create_rc_corner -name Cmax -qrc_tech $qrc_max
+create_rc_corner -name Cmin -qrc_tech $qrc_min
+
+create_delay_corner -name WC -early_timing_condition { timing_wc } \
+                             -late_timing_condition  { timing_wc } \
+                             -early_rc_corner          Cmax        \
+                             -late_rc_corner           Cmax
+
+create_delay_corner -name BC -early_timing_condition { timing_bc } \
+                             -late_timing_condition  { timing_bc } \
+                             -early_rc_corner          Cmin        \
+                             -late_rc_corner           Cmin
+
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
+ 
+set_analysis_view -setup WC_VIEW -hold BC_VIEW

Flows/ASAP7/nvdla/scripts/cadence/mmmc_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+create_rc_corner -name Cmax -qx_tech_file $qrc_max
+create_rc_corner -name Cmin -qx_tech_file $qrc_min
+
+
+create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
+create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON

Flows/ASAP7/nvdla/scripts/cadence/rtl_list.tcl

+#-y nv_small/src
+#+incdir+nv_small/src
++libext+.v
++libext+.sv
++libext+.gv
++define+DISABLE_TESTPOINTS
++define+NV_SYNTHESIS
+//+define+RAM_INTERFACE
+
+NV_nvdla.v
+NV_NVDLA_apb2csb.v
+NV_NVDLA_partition_c.v
+NV_NVDLA_partition_a.v
+NV_NVDLA_partition_p.v
+NV_NVDLA_partition_o.v
+NV_NVDLA_partition_m.v
+NV_NVDLA_CFGROM_rom.v
+NV_NVDLA_sync3d.v
+NV_NVDLA_cfgrom.v
+NV_NVDLA_glb.v
+NV_NVDLA_core_reset.v
+NV_NVDLA_sync3d_s.v
+NV_NVDLA_mcif.v
+NV_NVDLA_cdp.v
+NV_NVDLA_csb_master.v
+NV_NVDLA_pdp.v
+NV_NVDLA_reset.v
+NV_NVDLA_PDP_rdma.v
+NV_NVDLA_CDP_rdma.v
+NV_NVDLA_CDP_DP_nan.v
+NV_NVDLA_PDP_slcg.v
+NV_NVDLA_PDP_core.v
+NV_NVDLA_CDP_slcg.v
+NV_NVDLA_MCIF_csb.v
+NV_NVDLA_PDP_nan.v
+NV_NVDLA_CDP_wdma.v
+NV_NVDLA_PDP_wdma.v
+NV_NVDLA_PDP_reg.v
+NV_NVDLA_GLB_ic.v
+NV_NVDLA_CDP_reg.v
+NV_NVDLA_GLB_csb.v
+NV_NVDLA_CDP_dp.v
+NV_NVDLA_MCIF_read.v
+NV_NVDLA_MCIF_write.v
+NV_NVDLA_MCIF_CSB_reg.v
+NV_NVDLA_MCIF_WRITE_ig.v
+NV_NVDLA_MCIF_READ_ig.v
+NV_NVDLA_MCIF_WRITE_cq.v
+NV_NVDLA_MCIF_READ_eg.v
+NV_NVDLA_MCIF_WRITE_eg.v
+NV_NVDLA_MCIF_READ_IG_arb.v
+NV_NVDLA_MCIF_READ_IG_bpt.v
+NV_NVDLA_MCIF_READ_IG_cvt.v
+NV_NVDLA_MCIF_WRITE_IG_bpt.v
+NV_NVDLA_MCIF_WRITE_IG_cvt.v
+NV_NVDLA_MCIF_WRITE_IG_arb.v
+NV_CLK_gate_power.v
+CKLNQD12.v
+CKLNQD12PO4.v
+NV_BLKBOX_SRC0_X.v
+AN2D4PO4.v
+NV_NVDLA_CDP_RDMA_eg.v
+NV_NVDLA_CDP_DP_cvtout.v
+NV_NVDLA_CDP_DP_sum.v
+NV_NVDLA_CDP_RDMA_ig.v
+NV_NVDLA_CDP_DP_lut.v
+NV_NVDLA_CDP_DP_LUT_ctrl.v
+NV_NVDLA_CDP_REG_single.v
+NV_NVDLA_CDP_RDMA_reg.v
+NV_NVDLA_CDP_DP_cvtin.v
+NV_NVDLA_CDP_RDMA_cq.v
+NV_NVDLA_CDP_DP_bufferin_tp1.v
+NV_NVDLA_CDP_DP_mul.v
+NV_NVDLA_CDP_REG_dual.v
+NV_NVDLA_CDP_DP_syncfifo.v
+NV_NVDLA_CDP_DP_intp.v
+NV_NVDLA_CDP_DP_LUT_CTRL_unit.v
+NV_NVDLA_CDP_DP_INTP_unit.v
+NV_NVDLA_CDP_DP_MUL_unit.v
+sync_reset.v
+NV_BLKBOX_SRC0.v
+OR2D1.v
+p_SSYNC2DO_C_PP.v
+MUX2D4.v
+MUX2HDD2.v
+sync3d_s_ppp.v
+sync3d.v
+p_SSYNC3DO_S_PPP.v
+p_SSYNC3DO.v
+NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v
+NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
+oneHotClk_async_read_clock.v
+p_STRICTSYNC3DOTM_C_PPP.v
+oneHotClk_async_write_clock.v
+p_SSYNC3DO_C_PPP.v
+NV_NVDLA_XXIF_libs.v
+NV_NVDLA_DMAIF_rdreq.v
+NV_BLKBOX_SINK.v
+NV_NVDLA_CDP_RDMA_lat_fifo.v
+NV_NVDLA_CDP_RDMA_REG_single.v
+NV_NVDLA_CDP_RDMA_ro_fifo.v
+NV_NVDLA_CDP_RDMA_REG_dual.v
+NV_NVDLA_DMAIF_rdrsp.v
+NV_NVDLA_CDP_WDMA_dat_fifo.v
+NV_NVDLA_DMAIF_wr.v
+HLS_cdp_ocvt.v
+HLS_cdp_icvt.v
+NV_NVDLA_CDP_DP_data_fifo.v
+NV_NVDLA_CDP_DP_intpinfo_fifo.v
+NV_NVDLA_CDP_DP_sumpd_fifo.v
+int_sum_block_tp1.v
+NV_NVDLA_HLS_shiftrightsu.v
+NV_NVDLA_PDP_CORE_preproc.v
+NV_NVDLA_PDP_WDMA_dat.v
+NV_NVDLA_PDP_CORE_cal2d.v
+NV_NVDLA_PDP_RDMA_cq.v
+NV_NVDLA_PDP_CORE_cal1d.v
+NV_NVDLA_PDP_RDMA_REG_single.v
+NV_NVDLA_PDP_RDMA_eg.v
+NV_NVDLA_PDP_WDMA_cmd.v
+NV_NVDLA_PDP_REG_dual.v
+NV_NVDLA_PDP_REG_single.v
+NV_NVDLA_PDP_RDMA_REG_dual.v
+NV_NVDLA_PDP_RDMA_ig.v
+NV_NVDLA_PDP_RDMA_reg.v
+NV_NVDLA_PDP_RDMA_lat_fifo.v
+NV_NVDLA_PDP_RDMA_ro_fifo.v
+NV_NVDLA_PDP_WDMA_DAT_fifo.v
+NV_NVDLA_PDP_CORE_unit1d.v
+NV_NVDLA_GLB_CSB_reg.v
+NV_NVDLA_sync3d_c.v
+sync3d_c_ppp.v
+NV_NVDLA_cdma.v
+NV_NVDLA_csc.v
+NV_NVDLA_cbuf.v
+NV_NVDLA_CDMA_status.v
+NV_NVDLA_CDMA_regfile.v
+NV_NVDLA_CDMA_cvt.v
+NV_NVDLA_CDMA_dc.v
+NV_NVDLA_CDMA_dma_mux.v
+NV_NVDLA_CDMA_shared_buffer.v
+NV_NVDLA_CDMA_img.v
+NV_NVDLA_CDMA_slcg.v
+NV_NVDLA_CDMA_wt.v
+NV_NVDLA_CDMA_WT_8ATMM_fifo.v
+NV_NVDLA_CDMA_CVT_cell.v
+NV_NVDLA_CDMA_IMG_ctrl.v
+NV_NVDLA_CDMA_IMG_pack.v
+NV_NVDLA_CDMA_IMG_sg.v
+NV_NVDLA_CDMA_single_reg.v
+NV_NVDLA_CDMA_WT_fifo.v
+NV_NVDLA_CDMA_dual_reg.v
+NV_NVDLA_CDMA_DC_fifo.v
+NV_NVDLA_HLS_saturate.v
+NV_NVDLA_CDMA_IMG_fifo.v
+NV_NVDLA_CDMA_IMG_sg2pack_fifo.v
+NV_NVDLA_CSC_regfile.v
+NV_NVDLA_CSC_wl.v
+NV_NVDLA_CSC_WL_dec.v
+NV_NVDLA_CSC_sg.v
+NV_NVDLA_CSC_dl.v
+NV_NVDLA_CSC_slcg.v
+NV_NVDLA_CSC_SG_dat_fifo.v
+NV_NVDLA_CSC_SG_wt_fifo.v
+NV_NVDLA_CSC_dual_reg.v
+NV_NVDLA_CSC_single_reg.v
+NV_NVDLA_CACC_assembly_ctrl.v
+NV_NVDLA_CACC_dual_reg.v
+NV_NVDLA_CMAC_CORE_slcg.v
+NV_NVDLA_CACC_assembly_buffer.v
+NV_NVDLA_CACC_slcg.v
+NV_NVDLA_cacc.v
+NV_NVDLA_CACC_single_reg.v
+NV_NVDLA_CACC_calculator.v
+NV_NVDLA_CMAC_core.v
+NV_NVDLA_CACC_delivery_buffer.v
+NV_NVDLA_CACC_CALC_int8.v
+NV_NVDLA_CACC_regfile.v
+NV_NVDLA_CMAC_CORE_rt_in.v
+NV_NVDLA_CMAC_REG_dual.v
+NV_NVDLA_CACC_delivery_ctrl.v
+NV_NVDLA_CMAC_reg.v
+NV_NVDLA_cmac.v
+NV_NVDLA_CMAC_CORE_active.v
+NV_NVDLA_CMAC_CORE_cfg.v
+NV_NVDLA_CMAC_CORE_mac.v
+NV_NVDLA_CMAC_REG_single.v
+NV_NVDLA_CMAC_CORE_rt_out.v
+NV_NVDLA_sdp.v
+NV_NVDLA_SDP_rdma.v
+NV_NVDLA_SDP_wdma.v
+NV_NVDLA_SDP_reg.v
+NV_NVDLA_SDP_core.v
+NV_NVDLA_SDP_HLS_x1_int.v
+NV_NVDLA_SDP_WDMA_cmd.v
+NV_NVDLA_SDP_RDMA_REG_dual.v
+NV_NVDLA_SDP_RDMA_reg.v
+NV_NVDLA_SDP_CORE_unpack.v
+NV_NVDLA_SDP_REG_dual.v
+NV_NVDLA_SDP_RDMA_pack.v
+NV_NVDLA_SDP_WDMA_gate.v
+NV_NVDLA_SDP_HLS_c.v
+NV_NVDLA_SDP_nrdma.v
+NV_NVDLA_SDP_WDMA_DAT_out.v
+NV_NVDLA_SDP_CORE_pack.v
+NV_NVDLA_SDP_WDMA_intr.v
+NV_NVDLA_SDP_cmux.v
+NV_NVDLA_SDP_CORE_gate.v
+NV_NVDLA_SDP_WDMA_dat.v
+NV_NVDLA_SDP_REG_single.v
+NV_NVDLA_SDP_RDMA_REG_single.v
+NV_NVDLA_SDP_brdma.v
+NV_NVDLA_SDP_WDMA_DAT_in.v
+NV_NVDLA_SDP_mrdma.v
+NV_NVDLA_SDP_HLS_x2_int.v
+NV_NVDLA_SDP_MRDMA_eg.v
+NV_NVDLA_SDP_MRDMA_gate.v
+NV_NVDLA_SDP_NRDMA_gate.v
+NV_NVDLA_SDP_MRDMA_ig.v
+NV_NVDLA_SDP_RDMA_ig.v
+NV_NVDLA_SDP_RDMA_eg.v
+NV_NVDLA_SDP_BRDMA_gate.v
+NV_NVDLA_SDP_RDMA_dmaif.v
+NV_NVDLA_SDP_HLS_X_int_relu.v
+NV_NVDLA_SDP_HLS_C_int.v
+NV_NVDLA_SDP_HLS_X_int_alu.v
+NV_NVDLA_SDP_HLS_X_int_mul.v
+NV_NVDLA_SDP_HLS_X_int_trt.v
+NV_NVDLA_SDP_HLS_relu.v
+NV_NVDLA_SDP_HLS_prelu.v
+NV_NVDLA_SDP_HLS_sync2data.v
+NV_NVDLA_HLS_shiftleftsu.v
+NV_NVDLA_HLS_shiftrightsatsu.v
+NV_NVDLA_SDP_NRDMA_cq_lib.v
+NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v
+NV_NVDLA_SDP_BRDMA_cq_lib.v
+NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v
+NV_NVDLA_SDP_MRDMA_cq_lib.v
+NV_NVDLA_SDP_MRDMA_EG_din.v
+NV_NVDLA_SDP_MRDMA_EG_dout.v
+NV_NVDLA_SDP_MRDMA_EG_cmd.v
+NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v
+NV_NVDLA_SDP_RDMA_unpack.v
+NV_NVDLA_SDP_RDMA_EG_ro.v
+NV_BLKBOX_BUFFER.v
+SDFQD1.v
+RAMDP_128X6_GL_M2_E2.v
+RAMDP_128X11_GL_M2_E2.v
+RAMDP_16X64_GL_M1_E2.v
+RAMPDP_256X64_GL_M2_D2.v
+RAMDP_16X272_GL_M1_E2.v
+RAMDP_16X66_GL_M1_E2.v
+RAMDP_16X256_GL_M1_E2.v
+RAMDP_16X14_GL_M1_E2.v
+RAMDP_16X16_GL_M1_E2.v
+ScanShareSel_JTAG_reg_ext_cg.v
+sync2d_c_pp.v
+p_SDFCNQD1PO4.v
+RAMDP_256X4_GL_M2_E2.v
+RAMDP_256X8_GL_M2_E2.v
+RAMDP_8X66_GL_M1_E2.v
+RAMDP_80X9_GL_M2_E2.v
+RAMPDP_80X17_GL_M2_D2.v
+RAMDP_60X22_GL_M1_E2.v
+RAMPDP_128X18_GL_M2_D2.v
+nv_ram_rws_128x18_logic.v
+nv_ram_rws_128x256_logic.v
+nv_ram_rws_128x64_logic.v
+nv_ram_rws_16x256_logic.v
+nv_ram_rws_16x272_logic.v
+nv_ram_rws_16x64_logic.v
+nv_ram_rws_256x3_logic.v
+nv_ram_rws_256x512_logic.v
+nv_ram_rws_256x64_logic.v
+nv_ram_rws_256x7_logic.v
+nv_ram_rws_32x16_logic.v
+nv_ram_rws_32x512_logic.v
+nv_ram_rws_32x544_logic.v
+nv_ram_rws_32x768_logic.v
+nv_ram_rws_512x256_logic.v
+nv_ram_rws_512x512_logic.v
+nv_ram_rws_512x64_logic.v
+nv_ram_rws_64x1024_logic.v
+nv_ram_rws_64x1088_logic.v
+nv_ram_rws_64x10_logic.v
+nv_ram_rws_64x116_logic.v
+nv_ram_rws_64x18_logic.v
+nv_ram_rwsp_128x11_logic.v
+nv_ram_rwsp_128x6_logic.v
+nv_ram_rwsp_160x16_logic.v
+nv_ram_rwsp_160x514_logic.v
+nv_ram_rwsp_160x65_logic.v
+nv_ram_rwsp_16x14_logic.v
+nv_ram_rwsp_16x16_logic.v
+nv_ram_rwsp_16x65_logic.v
+nv_ram_rwsp_20x289_logic.v
+nv_ram_rwsp_245x514_logic.v
+nv_ram_rwsp_256x11_logic.v
+nv_ram_rwsp_32x32_logic.v
+nv_ram_rwsp_61x514_logic.v
+nv_ram_rwsp_61x64_logic.v
+nv_ram_rwsp_61x65_logic.v
+nv_ram_rwsp_80x14_logic.v
+nv_ram_rwsp_80x16_logic.v
+nv_ram_rwsp_80x256_logic.v
+nv_ram_rwsp_80x514_logic.v
+nv_ram_rwsp_80x65_logic.v
+nv_ram_rwsp_8x65_logic.v
+nv_ram_rwst_256x8_logic.v
+nv_ram_rwsthp_19x32_logic.v
+nv_ram_rwsthp_19x4_logic.v
+nv_ram_rwsthp_19x80_logic.v
+nv_ram_rwsthp_20x4_logic.v
+nv_ram_rwsthp_60x168_logic.v
+nv_ram_rwsthp_60x21_logic.v
+nv_ram_rwsthp_80x15_logic.v
+nv_ram_rwsthp_80x17_logic.v
+nv_ram_rwsthp_80x72_logic.v
+nv_ram_rwsthp_80x9_logic.v
+nv_ram_rws_128x18.v
+nv_ram_rws_128x256.v
+nv_ram_rws_128x64.v
+nv_ram_rws_16x256.v
+nv_ram_rws_16x272.v
+nv_ram_rws_16x64.v
+nv_ram_rws_256x3.v
+nv_ram_rws_256x512.v
+nv_ram_rws_256x64.v
+nv_ram_rws_256x7.v
+nv_ram_rws_32x16.v
+nv_ram_rws_32x512.v
+nv_ram_rws_32x544.v
+nv_ram_rws_32x768.v
+nv_ram_rws_512x256.v
+nv_ram_rws_512x512.v
+nv_ram_rws_512x64.v
+nv_ram_rws_64x1024.v
+nv_ram_rws_64x1088.v
+nv_ram_rws_64x10.v
+nv_ram_rws_64x116.v
+nv_ram_rws_64x18.v
+nv_ram_rwsp_128x11.v
+nv_ram_rwsp_128x6.v
+nv_ram_rwsp_160x16.v
+nv_ram_rwsp_160x514.v
+nv_ram_rwsp_160x65.v
+nv_ram_rwsp_16x14.v
+nv_ram_rwsp_16x16.v
+nv_ram_rwsp_16x65.v
+nv_ram_rwsp_20x289.v
+nv_ram_rwsp_245x514.v
+nv_ram_rwsp_256x11.v
+nv_ram_rwsp_32x32.v
+nv_ram_rwsp_61x514.v
+nv_ram_rwsp_61x64.v
+nv_ram_rwsp_61x65.v
+nv_ram_rwsp_80x14.v
+nv_ram_rwsp_80x16.v
+nv_ram_rwsp_80x256.v
+nv_ram_rwsp_80x514.v
+nv_ram_rwsp_80x65.v
+nv_ram_rwsp_8x65.v
+nv_ram_rwst_256x8.v
+nv_ram_rwsthp_19x32.v
+nv_ram_rwsthp_19x4.v
+nv_ram_rwsthp_19x80.v
+nv_ram_rwsthp_20x4.v
+nv_ram_rwsthp_60x168.v
+nv_ram_rwsthp_60x21.v
+nv_ram_rwsthp_80x15.v
+nv_ram_rwsthp_80x17.v
+nv_ram_rwsthp_80x72.v
+nv_ram_rwsthp_80x9.v
+fakeram7_256x64_dp.v
+
+
+-v NV_NVDLA_XXIF_libs.v

Flows/ASAP7/nvdla/scripts/cadence/run.sh

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+#!/bin/tcsh
+module unload genus
+module load genus/21.1
+module unload innovus
+module load innovus/21.1
+
+mkdir log -p
+genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
+innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log

Flows/ASAP7/nvdla/scripts/cadence/run_genus.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+set_db library $list_lib
+set_db init_hdl_search_path [list . ../../../../../Testcases/nvdla/rtl/]
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+read_hdl -f rtl_list.tcl
+
+elaborate $DESIGN
+time_info Elaboration
+
+read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/ASAP7/nvdla/scripts/cadence/run_genus_iSpatial.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+read_mmmc mmmc_iSpatial_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+read_physical -lefs $lefs
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+set_db init_hdl_search_path [list . $rtl_path]
+
+# set path
+set_db auto_ungroup none
+
+#set_db library $list_lib
+
+
+#################################################
+# Load Design and Initialize
+#################################################
+read_hdl -f rtl_list.tcl
+
+elaborate $DESIGN
+time_info Elaboration
+
+#read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+read_def $floorplan_def
+check_floorplan -detailed
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic -physical
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map -physical
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt -spatial
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+source mmmc_setup.tcl
+
+setMultiCpuUsage -localCpu 16
+set util 0.3
+
+set netlist "./syn_handoff/$DESIGN.v"
+set sdc "./syn_handoff/$DESIGN.sdc"
+
+set site "asap7sc7p5t"
+
+set rptDir summaryReport/ 
+set encDir enc/
+
+if {![file exists $rptDir/]} {
+    exec mkdir $rptDir/
+}
+
+if {![file exists $encDir/]} {
+    exec mkdir $encDir/
+}
+
+# default settings
+set init_pwr_net VDD
+set init_gnd_net VSS
+
+# default settings
+set init_verilog "$netlist"
+set init_design_netlisttype "Verilog"
+set init_design_settop 1
+set init_top_cell "$DESIGN"
+set init_lef_file "$lefs"
+
+# MCMM setup
+init_design -setup {WC_VIEW} -hold {BC_VIEW}
+set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
+
+set_interactive_constraint_modes {CON}
+setDesignMode -process 7
+
+clearGlobalNets
+globalNetConnect VDD -type pgpin -pin VDD -inst * -override
+globalNetConnect VSS -type pgpin -pin VSS -inst * -override
+globalNetConnect VDD -type tiehi -inst * -override
+globalNetConnect VSS -type tielo -inst * -override
+
+
+setOptMode -powerEffort low -leakageToDynamicRatio 0.5
+setGenerateViaMode -auto true
+generateVias
+
+# basic path groups
+createBasicPathGroups -expanded
+
+## Generate the floorplan ##
+#floorPlan -r 1.0 $util 10 10 10 10
+defIn $floorplan_def 
+
+## Macro Placement ##
+#redirect mp_config.tcl {source gen_mp_config.tcl}
+#proto_design -constraints mp_config.tcl 
+addHaloToBlock -allMacro 1 1 1 1
+setFPlanMode -snapBlockGrid LayerTrack
+place_design -concurrent_macros
+refine_macro_place
+snapFPlan -pin
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
+
+## Creating Pin Blcokage for lower and upper pin layers ##
+createPinBlkg -name Layer_1 -layer {M2 M3 M7 M8 M9 Pad} -edge 0
+createPinBlkg -name side_top -edge 1
+createPinBlkg -name side_right -edge 2
+createPinBlkg -name side_bottom -edge 3
+
+setPlaceMode -place_detail_legalization_inst_gap 1
+setFillerMode -fitGap true
+setDesignMode -topRoutingLayer 7
+setDesignMode -bottomRoutingLayer 2 
+
+place_opt_design -out_dir $rptDir -prefix place
+saveDesign $encDir/${DESIGN}_placed.enc
+
+set_ccopt_property post_conditioning_enable_routing_eco 1
+set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
+setOptMode -unfixClkInstForOpt false
+
+create_ccopt_clock_tree_spec
+ccopt_design
+
+set_interactive_constraint_modes [all_constraint_modes -active]
+set_propagated_clock [all_clocks]
+set_clock_propagation propagated
+
+# ------------------------------------------------------------------------------
+# Routing
+# ------------------------------------------------------------------------------
+setNanoRouteMode -drouteVerboseViolationSummary 1
+setNanoRouteMode -routeWithSiDriven true
+setNanoRouteMode -routeWithTimingDriven true
+setNanoRouteMode -routeUseAutoVia true
+
+##Recommended by lib owners
+# Prevent router modifying M1 pins shapes
+setNanoRouteMode -routeWithViaInPin "1:1"
+setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
+
+## limit VIAs to ongrid only for VIA1 (S1)
+setNanoRouteMode -drouteOnGridOnly "via 1:1"
+setNanoRouteMode -drouteAutoStop false
+setNanoRouteMode -drouteExpAdvancedMarFix true
+setNanoRouteMode -routeExpAdvancedTechnology true
+
+#SM suggestion for solving long extraction runtime during GR
+setNanoRouteMode -grouteExpWithTimingDriven false
+
+routeDesign
+#route_opt_design
+saveDesign ${encDir}/${DESIGN}_route.enc
+defOut -netlist -floorplan -routing ${DESIGN}_route.def
+
+summaryReport -noHtml -outfile summaryReport/post_route.sum
+saveDesign ${encDir}/${DESIGN}.enc
+defOut -netlist -floorplan -routing ${DESIGN}.def
+
+exit

Flows/NanGate45/ariane133/scripts/cadence/design_setup.tcl

@@ -4,8 +4,14 @@
 set DESIGN ariane 
 set sdc  ../../constraints/${DESIGN}.sdc
 
-# def file with die size and placed IO pins
-set floorplan_def ../../def/ariane133_fp_rows.def
+#
+# DEF file for floorplan initialization
+#
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set floorplan_def ../../def/ariane133_fp_placed_macros.def
+} else {
+    set floorplan_def ../../def/ariane133_fp.def
+}
 #
 # Effort level during optimization in syn_generic -physical (or called generic) stage
 # possible values are : high, medium or low

Flows/NanGate45/ariane133/scripts/cadence/run.sh

@@ -6,6 +6,10 @@ module load genus/21.1
 module unload innovus
 module load innovus/21.1
 
+#
+# To run the Physical Synthesis (iSpatial) flow - flow2
+export PHY_SYNTH=1
+
 mkdir log -p
-genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
-innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
+genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
+innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl

Flows/NanGate45/ariane133/scripts/cadence/run_genus.tcl

@@ -31,6 +31,8 @@ set link_library $list_lib
 set target_library $list_lib
 
 # set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
 set_db auto_ungroup none
 
 set_db library $list_lib

Flows/NanGate45/ariane133/scripts/cadence/run_genus_hybrid.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_mmmc mmmc_iSpatial_setup.tcl
+}
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+    read_physical -lefs $lefs
+}
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set pathi
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    set_db library $list_lib
+}
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    read_sdc $sdc
+}
+
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_def $floorplan_def
+    check_floorplan -detailed
+}
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_generic -physical
+} else {
+    syn_generic
+}
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+ 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_map -physical
+} else {
+    syn_map
+}
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_opt -spatial
+} else {
+    syn_opt
+}
+
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+} else {
+    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+}
+
+exit

Flows/NanGate45/ariane133/scripts/cadence/run_genus_iSpatial.tcl

@@ -34,6 +34,8 @@ set link_library $list_lib
 set target_library $list_lib
 
 # set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
 set_db auto_ungroup none
 
 #set_db library $list_lib

Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl

@@ -7,8 +7,10 @@ source mmmc_setup.tcl
 setMultiCpuUsage -localCpu 16
 set util 0.3
 
-set netlist "./syn_handoff/$DESIGN.v"
-set sdc "./syn_handoff/$DESIGN.sdc"
+set handoff_dir  "./syn_handoff"
+
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
 
 set site "FreePDK45_38x28_10R_NP_162NW_34O"
 
@@ -56,25 +58,18 @@ generateVias
 createBasicPathGroups -expanded
 
 ## Generate the floorplan ##
-#floorPlan -r 1.0 $util 10 10 10 10
-defIn $floorplan_def 
-defOut -routing ${DESIGN}.def
 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    defIn ${handoff_dir}/${DESIGN}.def
+} else {
+    defIn $floorplan_def
+    addHaloToBlock -allMacro 5 5 5 5
+    place_design -concurrent_macros
+    refine_macro_place
+}
 
-## Macro Placement ##
-#redirect mp_config.tcl {source gen_mp_config.tcl}
-#proto_design -constraints mp_config.tcl 
-addHaloToBlock -allMacro 5 5 5 5
-place_design -concurrent_macros
-refine_macro_place
 saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
-## Creating Pin Blcokage for lower and upper pin layers ##
-createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
-createPinBlkg -name side_top -edge 1
-createPinBlkg -name side_right -edge 2
-createPinBlkg -name side_bottom -edge 3
-
 setPlaceMode -place_detail_legalization_inst_gap 1
 setFillerMode -fitGap true
 setDesignMode -topRoutingLayer 10

Flows/NanGate45/ariane136/scripts/cadence/design_setup.tcl

@@ -4,8 +4,14 @@
 set DESIGN ariane 
 set sdc  ../../constraints/${DESIGN}.sdc
 
-# def file with die size and placed IO pins
-set floorplan_def ../../def/ariane136_fp_rows.def
+#
+# DEF file for floorplan initialization
+#
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set floorplan_def ../../def/ariane136_fp_placed_macros.def
+} else {
+    set floorplan_def ../../def/ariane136_fp.def
+}
 #
 # Effort level during optimization in syn_generic -physical (or called generic) stage
 # possible values are : high, medium or low

Flows/NanGate45/ariane136/scripts/cadence/run.sh

@@ -6,6 +6,10 @@ module load genus/21.1
 module unload innovus
 module load innovus/21.1
 
+#
+# To run the Physical Synthesis (iSpatial) flow - flow2
+export PHY_SYNTH=1
+
 mkdir log -p
-genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
-innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
+genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
+innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl

Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_mmmc mmmc_iSpatial_setup.tcl
+}
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+    read_physical -lefs $lefs
+}
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set pathi
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    set_db library $list_lib
+}
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    read_sdc $sdc
+}
+
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_def $floorplan_def
+    check_floorplan -detailed
+}
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_generic -physical
+} else {
+    syn_generic
+}
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+ 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_map -physical
+} else {
+    syn_map
+}
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_opt -spatial
+} else {
+    syn_opt
+}
+
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+} else {
+    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+}
+
+exit

Flows/NanGate45/ariane136/scripts/cadence/run_genus_iSpatial.tcl

@@ -34,6 +34,8 @@ set link_library $list_lib
 set target_library $list_lib
 
 # set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
 set_db auto_ungroup none
 
 #set_db library $list_lib

Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl

@@ -7,8 +7,10 @@ source mmmc_setup.tcl
 setMultiCpuUsage -localCpu 16
 set util 0.3
 
-set netlist "./syn_handoff/$DESIGN.v"
-set sdc "./syn_handoff/$DESIGN.sdc"
+set handoff_dir  "./syn_handoff"
+
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
 
 set site "FreePDK45_38x28_10R_NP_162NW_34O"
 
@@ -56,22 +58,17 @@ generateVias
 createBasicPathGroups -expanded
 
 ## Generate the floorplan ##
-#floorPlan -r 1.0 $util 10 10 10 10
-defIn $floorplan_def 
-
-## Macro Placement ##
-#redirect mp_config.tcl {source gen_mp_config.tcl}
-#proto_design -constraints mp_config.tcl 
-addHaloToBlock -allMacro 5 5 5 5
-place_design -concurrent_macros
-refine_macro_place
-saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
-## Creating Pin Blcokage for lower and upper pin layers ##
-createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
-createPinBlkg -name side_top -edge 1
-createPinBlkg -name side_right -edge 2
-createPinBlkg -name side_bottom -edge 3
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    defIn ${handoff_dir}/${DESIGN}.def
+} else {
+    defIn $floorplan_def
+    addHaloToBlock -allMacro 5 5 5 5
+    place_design -concurrent_macros
+    refine_macro_place
+}
+
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 setPlaceMode -place_detail_legalization_inst_gap 1
 setFillerMode -fitGap true

Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_mmmc mmmc_iSpatial_setup.tcl
+}
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+    read_physical -lefs $lefs
+}
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set pathi
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    set_db library $list_lib
+}
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    read_sdc $sdc
+}
+
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_def $floorplan_def
+    check_floorplan -detailed
+}
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_generic -physical
+} else {
+    syn_generic
+}
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+ 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_map -physical
+} else {
+    syn_map
+}
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_opt -spatial
+} else {
+    syn_opt
+}
+
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+} else {
+    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+}
+
+exit

Flows/NanGate45/nvdla/README.md

+# **Synthesis, Place \& Route (SP\&R):**
+Here we provide the setup to run SP&R of NVDLA design with 128 macros on NanGate45 using commercial and open-source tools.
+  - [**SP\&R Flow**](#spr-flow)
+    - [**Cadence tools**](#using-cadence-genus-and-innovus)
+
+## **SP\&R Flow:**
+We implement [NVDLA](../../../Testcases/nvdla/) on the NanGate45 platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/nangate45). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the NanGate45 platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/NanGate45*](../../../Enablements/NanGate45/) directory.
+  
+  
+### **Using Cadence Genus and Innovus:**
+All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.  
+**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
+```
+genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
+```  
+We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.  
+  
+**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
+```
+innovus -64 -init run_invs.tcl -log log/run.log
+```
+
+Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow.  
+<img src="./screenshots/nvdla_Innovus_ng45.png" alt="nvdla_cadence" width="400"/>  
+
+This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+
+<!--
+### **Using OpenROAD-flow-scripts:**
+Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:  
+1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
+2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
+3. To launch the SP&R job go to the flow directory and use the below command
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
+  ```
+4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
+  ```  
+  
+Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.  
+<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
+-->
\ No newline at end of file

Flows/NanGate45/nvdla/scripts/cadence/rtl_list.tcl

@@ -371,7 +371,7 @@ nv_ram_rwsthp_80x15.v
 nv_ram_rwsthp_80x17.v
 nv_ram_rwsthp_80x72.v
 nv_ram_rwsthp_80x9.v
-fakeram45_256x64_dp.v
+fakeram_256x64_dp.v
 
 
 -v NV_NVDLA_XXIF_libs.v

Flows/README.md

@@ -4,7 +4,14 @@ The setup to run SP&R on the available test cases for the given enablements are
   - [Ariane136](./NanGate45/ariane136/)
   - [Ariane133](./NanGate45/ariane133/)
   - [MemPool tile](./NanGate45/mempool_tile/)
+  - [NVDLA](./NanGate45/nvdla/)
 - [ASAP7](../Enablements/ASAP7/)
   - [Ariane136](./ASAP7/ariane136/)
   - [Ariane133](./ASAP7/ariane133/)
-  - [MemPool tile](./ASAP7/mempool_tile/)
\ No newline at end of file
+  - [MemPool tile](./ASAP7/mempool_tile/)
+  - [NVDLA](./ASAP7/nvdla/)
+- [SKY130HD FakeStack](../Enablements/SKY130HD/)
+  - [Ariane136](./SKY130HD/ariane136/)
+  - [Ariane133](./SKY130HD/ariane133/)
+  - [MemPool tile](./SKY130HD/mempool_tile/)
+  - [NVDLA](./SKY130HD/nvdla/)
\ No newline at end of file

Flows/SKY130HD/ariane133/README.md

+# **Synthesis, Place \& Route (SP\&R):**
+Here we provide the setup to run SP&R of Ariane design with 133 macros on SKY130HD using commercial and open-source tools. First, we provide the steps for netlist preparation and then discuss the SP&R flow.
+  - [**SP\&R Flow:**](#spr-flow)
+    - [**Using Cadence Innovus:**](#using-cadence-innovus)
+    - [**Using OpenROAD-flow-scripts:**](#using-openroad-flow-scripts)
+
+## **SP\&R Flow:**
+We implement the Ariane design on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are copied into the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.  
+  
+### **Using Cadence Innovus:**
+All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.  
+We use an unnamed commercial logic synthesis tool to synthesize the Ariane 133-macro version from Verilog RTL. The synthesized gate-level (standard cells and SRAM macros) netlist is available in [*./netlist/*](./netlist/) directory.
+  
+**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the gate-level netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
+```
+innovus -64 -init run_invs.tcl -log log/run.log
+```  
+Innovus requires a configuration file to run the macro placement flow. For this we use *proto_design -constraints mp_config.tcl* command. The configuration file [*mp_config.tcl*](./scripts/cadence//mp_config.tcl) is available in the [*./scripts/cadence/*](./scripts/cadence/) directory. Some details of the configuration files are as follows:
+1. Provide the memory hierarchy name under the **SEED** section. If you do not provide the memory hierarchy here, then the macro placement constraints (e.g., cell orientation, spacing, etc.) related to that memory may be overlooked.
+2. For each macro, valid orientation and spacing rules can be provided under the **MACRO** section. For example, we set valid macro orientation as *R0* for our run, horizontal spacing as *10um*, and vertical spacing as *5um*. Also, when you provide the cell name (ref name, not instance name) add the *isCell=true* option.
+
+Below is the screenshot of the Ariane SP\&R database with 133 memory macros using the Cadence flow.  
+<img src="./screenshots/Ariane133_Innovus.png" alt="ariane133_cadence" width="400"/>  
+
+This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+<!--
+### **Using OpenROAD-flow-scripts:**
+Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:  
+1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
+2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane133* directory which contains all the files required to run SP&R using ORFS. The config file contains the *set_dont_touch* (it is called PRESERVE_CELLS in ORFS) for the memory macros.
+3. To launch the SP&R job go to the flow directory and use the below command
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane133/config_hier.mk
+  ```
+4. config_hier.mk uses the **RTL-MP** for macro placement. To run macro placement using **Triton Macro Placer** use the below command
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane133/config.mk
+  ```  
+  
+Below is a screenshot of the Ariane SP\&R database with 133 memory macros using ORFS (RTL-MP) flow.  
+<img src="./screenshots/Ariane133_ORFS.png" alt="ariane136_orfs" width="400"/>
+-->

Flows/SKY130HD/ariane133/constraints/ariane.sdc

+#period set in nano-seconds - currently: 4ns = 250 MHz freq
+create_clock [get_ports clk_i]  -name core_clock  -period 4

Flows/SKY130HD/ariane133/run/README.md

+Here we run our scripts 

Flows/SKY130HD/ariane133/scripts/cadence/design_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+set DESIGN ariane 
+set sdc  ../../constraints/${DESIGN}.sdc
+
+# def file with die size and placed IO pins
+set floorplan_def ../../def/ariane133_fp.def
+#
+# Effort level during optimization in syn_generic -physical (or called generic) stage
+# possible values are : high, medium or low
+set GEN_EFF medium
+
+# Effort level during optimization in syn_map -physical (or called mapping) stage
+# possible values are : high, medium or low
+set MAP_EFF high

Flows/SKY130HD/ariane133/scripts/cadence/lib_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+# lib and lef, RC setup
+
+set libdir "../../../../../Enablements/SKY130HD/lib"
+set lefdir "../../../../../Enablements/SKY130HD/lef"
+set qrcdir "../../../../../Enablements/SKY130HD/qrc"
+
+set_db init_lib_search_path { \
+    ${libdir} \
+    ${lefdir} \
+}
+
+set libworst "  
+    ${libdir}/sky130_fd_sc_hd__tt_025C_1v80.lib \
+    ${libdir}/fakeram130_256x16.lib \
+    "
+
+
+set libbest " 
+    ${libdir}/sky130_fd_sc_hd__tt_025C_1v80.lib \
+    ${libdir}/fakeram130_256x16.lib \
+    "
+
+set lefs "  
+    ${lefdir}/9M_li_2Ma_2Mb_2Mc_2Md_1Me.tlef \
+    ${lefdir}/sky130_fd_sc_hd_merged.lef \
+    ${lefdir}/fakeram130_256x16.lef \
+    "
+
+#set qrc_max "${qrcdir}/NG45.tch"
+#set qrc_min "${qrcdir}/NG45.tch"
+#
+# Ensures proper and consistent library handling between Genus and Innovus
+#set_db library_setup_ispatial true

Flows/SKY130HD/ariane133/scripts/cadence/mmmc_iSpatial_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
+#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
+ 
+create_timing_condition -name timing_wc  -library_sets { WC_LIB }
+create_timing_condition -name timing_bc  -library_sets { BC_LIB }
+ 
+create_rc_corner -name Cmax -qrc_tech $qrc_max
+create_rc_corner -name Cmin -qrc_tech $qrc_min
+
+create_delay_corner -name WC -early_timing_condition { timing_wc } \
+                             -late_timing_condition  { timing_wc } \
+                             -early_rc_corner          Cmax        \
+                             -late_rc_corner           Cmax
+
+create_delay_corner -name BC -early_timing_condition { timing_bc } \
+                             -late_timing_condition  { timing_bc } \
+                             -early_rc_corner          Cmin        \
+                             -late_rc_corner           Cmin
+
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
+ 
+set_analysis_view -setup WC_VIEW -hold BC_VIEW

Flows/SKY130HD/ariane133/scripts/cadence/mmmc_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+create_rc_corner -name Cmax
+create_rc_corner -name Cmin
+
+
+create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
+create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON

Flows/SKY130HD/ariane133/scripts/cadence/rtl_list.tcl

+set rtl_all {
+  ../../rtl/ariane.v
+}

Flows/SKY130HD/ariane133/scripts/cadence/run.sh

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+#!/bin/tcsh
+module unload genus
+module load genus/21.1
+module unload innovus
+module load innovus/21.1
+
+mkdir log -p
+genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
+innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log

Flows/SKY130HD/ariane133/scripts/cadence/run_genus.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+set_db library $list_lib
+
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/SKY130HD/ariane133/scripts/cadence/run_genus_iSpatial.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+setDesignMode -process 130
+read_mmmc mmmc_iSpatial_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+read_physical -lefs $lefs
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set path
+set_db auto_ungroup none
+
+#set_db library $list_lib
+
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+#read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+read_def $floorplan_def
+check_floorplan -detailed
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic -physical
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map -physical
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt -spatial
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+source mmmc_setup.tcl
+
+setMultiCpuUsage -localCpu 16
+set util 0.3
+
+set netlist "./syn_handoff/$DESIGN.v"
+set sdc "./syn_handoff/$DESIGN.sdc"
+
+set site "unithd"
+
+set rptDir summaryReport/ 
+set encDir enc/
+
+if {![file exists $rptDir/]} {
+    exec mkdir $rptDir/
+}
+
+if {![file exists $encDir/]} {
+    exec mkdir $encDir/
+}
+
+# default settings
+set init_pwr_net VDD
+set init_gnd_net VSS
+
+# default settings
+set init_verilog "$netlist"
+set init_design_netlisttype "Verilog"
+set init_design_settop 1
+set init_top_cell "$DESIGN"
+set init_lef_file "$lefs"
+
+# MCMM setup
+init_design -setup {WC_VIEW} -hold {BC_VIEW}
+set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
+
+set_interactive_constraint_modes {CON}
+setDesignMode -process 130
+
+clearGlobalNets
+globalNetConnect VDD -type pgpin -pin VDD -inst * -override
+globalNetConnect VSS -type pgpin -pin VSS -inst * -override
+globalNetConnect VDD -type tiehi -inst * -override
+globalNetConnect VSS -type tielo -inst * -override
+
+
+setOptMode -powerEffort low -leakageToDynamicRatio 0.5
+setGenerateViaMode -auto true
+generateVias
+
+# basic path groups
+createBasicPathGroups -expanded
+
+## Generate the floorplan ##
+#floorPlan -r 1.0 $util 10 10 10 10
+defIn $floorplan_def 
+
+## Macro Placement ##
+#redirect mp_config.tcl {source gen_mp_config.tcl}
+#proto_design -constraints mp_config.tcl 
+addHaloToBlock -allMacro 5 5 5 5
+place_design -concurrent_macros
+refine_macro_place
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
+
+## Creating Pin Blcokage for lower and upper pin layers ##
+createPinBlkg -name Layer_1 -layer {met2 met3 met9} -edge 0
+createPinBlkg -name side_top -edge 1
+createPinBlkg -name side_right -edge 2
+createPinBlkg -name side_bottom -edge 3
+
+setPlaceMode -place_detail_legalization_inst_gap 1
+setFillerMode -fitGap true
+setDesignMode -topRoutingLayer 9
+setDesignMode -bottomRoutingLayer 2 
+
+place_opt_design -out_dir $rptDir -prefix place
+saveDesign $encDir/${DESIGN}_placed.enc
+
+set_ccopt_property post_conditioning_enable_routing_eco 1
+set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
+setOptMode -unfixClkInstForOpt false
+
+create_ccopt_clock_tree_spec
+ccopt_design
+
+set_interactive_constraint_modes [all_constraint_modes -active]
+set_propagated_clock [all_clocks]
+set_clock_propagation propagated
+
+# ------------------------------------------------------------------------------
+# Routing
+# ------------------------------------------------------------------------------
+setNanoRouteMode -drouteVerboseViolationSummary 1
+setNanoRouteMode -routeWithSiDriven true
+setNanoRouteMode -routeWithTimingDriven true
+setNanoRouteMode -routeUseAutoVia true
+
+##Recommended by lib owners
+# Prevent router modifying M1 pins shapes
+setNanoRouteMode -routeWithViaInPin "1:1"
+setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
+
+## limit VIAs to ongrid only for VIA1 (S1)
+setNanoRouteMode -drouteOnGridOnly "via 1:1"
+setNanoRouteMode -drouteAutoStop false
+setNanoRouteMode -drouteExpAdvancedMarFix true
+setNanoRouteMode -routeExpAdvancedTechnology true
+
+#SM suggestion for solving long extraction runtime during GR
+setNanoRouteMode -grouteExpWithTimingDriven false
+
+routeDesign
+#route_opt_design
+saveDesign ${encDir}/${DESIGN}_route.enc
+defOut -netlist -floorplan -routing ${DESIGN}_route.def
+
+summaryReport -noHtml -outfile summaryReport/post_route.sum
+saveDesign ${encDir}/${DESIGN}.enc
+defOut -netlist -floorplan -routing ${DESIGN}.def
+
+exit

Flows/SKY130HD/ariane136/README.md

+# **Synthesis, Place \& Route (SP\&R):**
+Here we provide the setup to run SP&R of Ariane design with 136 macros on SKY130HD using commercial and open-source tools.
+  - [**SP\&R Flow**](#spr-flow)
+    - [**Cadence tools**](#using-cadence-genus-and-innovus)
+
+## **SP\&R Flow:**
+We implement Ariane design with [136 macros](../../../Testcases/ariane136/) on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.  
+  
+  
+### **Using Cadence Genus and Innovus:**
+All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.  
+**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .sv files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/ariane.sdc*](./constraints/ariane.sdc) file. To launch the synthesis run please use the below command
+```
+genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
+```  
+We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.  
+  
+**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
+```
+innovus -64 -init run_invs.tcl -log log/run.log
+```
+
+Below is the screenshot of the Ariane SP\&R database with 136 memory macros using Cadence flow.  
+<img src="./screenshots/Ariane136_Innovus_Genus.png" alt="ariane136_cadence" width="400"/>  
+
+
+This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+
+<!--
+### **Using OpenROAD-flow-scripts:**
+Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:  
+1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
+2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
+3. To launch the SP&R job go to the flow directory and use the below command
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
+  ```
+4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
+  ```
+  make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
+  ```  
+  
+Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.  
+<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
+-->
\ No newline at end of file

Flows/SKY130HD/ariane136/constraints/ariane.sdc

+# ####################################################################
+
+#  Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Fri Jul 01 20:44:40 PDT 2022
+
+# ####################################################################
+
+set sdc_version 2.0
+
+set_units -capacitance 1000fF
+set_units -time 1000ps
+
+# Set the current design
+current_design ariane
+
+create_clock -name "core_clock" -period 8.0 -waveform {0.0 4.0} [get_ports clk_i]
+set_clock_gating_check -setup 0.0 
+set_wire_load_mode "top"

Flows/SKY130HD/ariane136/rtl/alu.sv

+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Author: Matthias Baer <baermatt@student.ethz.ch>
+// Author: Igor Loi <igor.loi@unibo.it>
+// Author: Andreas Traber <atraber@student.ethz.ch>
+// Author: Lukas Mueller <lukasmue@student.ethz.ch>
+// Author: Florian Zaruba <zaruabf@iis.ee.ethz.ch>
+//
+// Date: 19.03.2017
+// Description: Ariane ALU based on RI5CY's ALU
+
+import ariane_pkg::*;
+
+module alu (
+    input  logic                     clk_i,          // Clock
+    input  logic                     rst_ni,         // Asynchronous reset active low
+    input  fu_data_t                 fu_data_i,
+    output logic [63:0]              result_o,
+    output logic                     alu_branch_res_o
+);
+
+    logic [63:0] operand_a_rev;
+    logic [31:0] operand_a_rev32;
+    logic [64:0] operand_b_neg;
+    logic [65:0] adder_result_ext_o;
+    logic        less;  // handles both signed and unsigned forms
+
+    // bit reverse operand_a for left shifts and bit counting
+    generate
+      genvar k;
+      for(k = 0; k < 64; k++)
+        assign operand_a_rev[k] = fu_data_i.operand_a[63-k];
+
+      for (k = 0; k < 32; k++)
+        assign operand_a_rev32[k] = fu_data_i.operand_a[31-k];
+    endgenerate
+
+    // ------
+    // Adder
+    // ------
+    logic        adder_op_b_negate;
+    logic        adder_z_flag;
+    logic [64:0] adder_in_a, adder_in_b;
+    logic [63:0] adder_result;
+
+    always_comb begin
+      adder_op_b_negate = 1'b0;
+
+      unique case (fu_data_i.operator)
+        // ADDER OPS
+        EQ,  NE,
+        SUB, SUBW: adder_op_b_negate = 1'b1;
+
+        default: ;
+      endcase
+    end
+
+    // prepare operand a
+    assign adder_in_a    = {fu_data_i.operand_a, 1'b1};
+
+    // prepare operand b
+    assign operand_b_neg = {fu_data_i.operand_b, 1'b0} ^ {65{adder_op_b_negate}};
+    assign adder_in_b    =  operand_b_neg ;
+
+    // actual adder
+    assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
+    assign adder_result       = adder_result_ext_o[64:1];
+    assign adder_z_flag       = ~|adder_result;
+
+    // get the right branch comparison result
+    always_comb begin : branch_resolve
+        // set comparison by default
+        alu_branch_res_o      = 1'b1;
+        case (fu_data_i.operator)
+            EQ:       alu_branch_res_o = adder_z_flag;
+            NE:       alu_branch_res_o = ~adder_z_flag;
+            LTS, LTU: alu_branch_res_o = less;
+            GES, GEU: alu_branch_res_o = ~less;
+            default:  alu_branch_res_o = 1'b1;
+        endcase
+    end
+
+    // ---------
+    // Shifts
+    // ---------
+
+    // TODO: this can probably optimized significantly
+    logic        shift_left;          // should we shift left
+    logic        shift_arithmetic;
+
+    logic [63:0] shift_amt;           // amount of shift, to the right
+    logic [63:0] shift_op_a;          // input of the shifter
+    logic [31:0] shift_op_a32;        // input to the 32 bit shift operation
+
+    logic [63:0] shift_result;
+    logic [31:0] shift_result32;
+
+    logic [64:0] shift_right_result;
+    logic [32:0] shift_right_result32;
+
+    logic [63:0] shift_left_result;
+    logic [31:0] shift_left_result32;
+
+    assign shift_amt = fu_data_i.operand_b;
+
+    assign shift_left = (fu_data_i.operator == SLL) | (fu_data_i.operator == SLLW);
+
+    assign shift_arithmetic = (fu_data_i.operator == SRA) | (fu_data_i.operator == SRAW);
+
+    // right shifts, we let the synthesizer optimize this
+    logic [64:0] shift_op_a_64;
+    logic [32:0] shift_op_a_32;
+
+    // choose the bit reversed or the normal input for shift operand a
+    assign shift_op_a    = shift_left ? operand_a_rev   : fu_data_i.operand_a;
+    assign shift_op_a32  = shift_left ? operand_a_rev32 : fu_data_i.operand_a[31:0];
+
+    assign shift_op_a_64 = { shift_arithmetic & shift_op_a[63], shift_op_a};
+    assign shift_op_a_32 = { shift_arithmetic & shift_op_a[31], shift_op_a32};
+
+    assign shift_right_result     = $unsigned($signed(shift_op_a_64) >>> shift_amt[5:0]);
+
+    assign shift_right_result32   = $unsigned($signed(shift_op_a_32) >>> shift_amt[4:0]);
+    // bit reverse the shift_right_result for left shifts
+    genvar j;
+    generate
+      for(j = 0; j < 64; j++)
+        assign shift_left_result[j] = shift_right_result[63-j];
+
+      for(j = 0; j < 32; j++)
+        assign shift_left_result32[j] = shift_right_result32[31-j];
+
+    endgenerate
+
+    assign shift_result = shift_left ? shift_left_result : shift_right_result[63:0];
+    assign shift_result32 = shift_left ? shift_left_result32 : shift_right_result32[31:0];
+
+    // ------------
+    // Comparisons
+    // ------------
+
+    always_comb begin
+        logic sgn;
+        sgn = 1'b0;
+
+        if ((fu_data_i.operator == SLTS) ||
+            (fu_data_i.operator == LTS)  ||
+            (fu_data_i.operator == GES))
+            sgn = 1'b1;
+
+        less = ($signed({sgn & fu_data_i.operand_a[63], fu_data_i.operand_a})  <  $signed({sgn & fu_data_i.operand_b[63], fu_data_i.operand_b}));
+    end
+
+    // -----------
+    // Result MUX
+    // -----------
+    always_comb begin
+        result_o   = '0;
+
+        unique case (fu_data_i.operator)
+            // Standard Operations
+            ANDL:  result_o = fu_data_i.operand_a & fu_data_i.operand_b;
+            ORL:   result_o = fu_data_i.operand_a | fu_data_i.operand_b;
+            XORL:  result_o = fu_data_i.operand_a ^ fu_data_i.operand_b;
+
+            // Adder Operations
+            ADD, SUB: result_o = adder_result;
+            // Add word: Ignore the upper bits and sign extend to 64 bit
+            ADDW, SUBW: result_o = {{32{adder_result[31]}}, adder_result[31:0]};
+            // Shift Operations
+            SLL,
+            SRL, SRA: result_o = shift_result;
+            // Shifts 32 bit
+            SLLW,
+            SRLW, SRAW: result_o = {{32{shift_result32[31]}}, shift_result32[31:0]};
+
+            // Comparison Operations
+            SLTS,  SLTU: result_o = {63'b0, less};
+
+            default: ; // default case to suppress unique warning
+        endcase
+    end
+endmodule

Flows/SKY130HD/ariane136/rtl/amo_alu.sv

+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Author: Florian Zaruba, ETH Zurich
+// Date: 15.09.2018
+// Description: Combinatorial AMO unit
+module amo_alu (
+        // AMO interface
+        input  ariane_pkg::amo_t  amo_op_i,
+        input  logic [63:0]       amo_operand_a_i,
+        input  logic [63:0]       amo_operand_b_i,
+        output logic [63:0]       amo_result_o // result of atomic memory operation
+);
+
+    logic [64:0] adder_sum;
+    logic [64:0] adder_operand_a, adder_operand_b;
+
+    assign adder_sum = adder_operand_a + adder_operand_b;
+
+    always_comb begin
+
+        adder_operand_a = $signed(amo_operand_a_i);
+        adder_operand_b = $signed(amo_operand_b_i);
+
+        amo_result_o = amo_operand_b_i;
+
+        unique case (amo_op_i)
+            // the default is to output operand_b
+            ariane_pkg::AMO_SC:;
+            ariane_pkg::AMO_SWAP:;
+            ariane_pkg::AMO_ADD: amo_result_o = adder_sum[63:0];
+            ariane_pkg::AMO_AND: amo_result_o = amo_operand_a_i & amo_operand_b_i;
+            ariane_pkg::AMO_OR:  amo_result_o = amo_operand_a_i | amo_operand_b_i;
+            ariane_pkg::AMO_XOR: amo_result_o = amo_operand_a_i ^ amo_operand_b_i;
+            ariane_pkg::AMO_MAX: begin
+                adder_operand_b = -$signed(amo_operand_b_i);
+                amo_result_o = adder_sum[64] ? amo_operand_b_i : amo_operand_a_i;
+            end
+            ariane_pkg::AMO_MIN: begin
+                adder_operand_b = -$signed(amo_operand_b_i);
+                amo_result_o = adder_sum[64] ? amo_operand_a_i : amo_operand_b_i;
+            end
+            ariane_pkg::AMO_MAXU: begin
+                adder_operand_a = $unsigned(amo_operand_a_i);
+                adder_operand_b = -$unsigned(amo_operand_b_i);
+                amo_result_o = adder_sum[64] ? amo_operand_b_i : amo_operand_a_i;
+            end
+            ariane_pkg::AMO_MINU: begin
+                adder_operand_a = $unsigned(amo_operand_a_i);
+                adder_operand_b = -$unsigned(amo_operand_b_i);
+                amo_result_o = adder_sum[64] ? amo_operand_a_i : amo_operand_b_i;
+            end
+            default: amo_result_o = '0;
+        endcase
+    end
+endmodule

Flows/SKY130HD/ariane136/rtl/amo_buffer.sv

+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Author: Florian Zaruba, ETH Zurich
+// Date: 20.09.2018
+// Description: Buffers AMO requests
+// This unit buffers an atomic memory operations for the cache subsyste.
+// Furthermore it handles interfacing with the commit stage
+
+module amo_buffer (
+    input  logic clk_i,              // Clock
+    input  logic rst_ni,             // Asynchronous reset active low
+    input  logic flush_i,            // pipeline flush
+
+    input  logic             valid_i,            // AMO is valid
+    output logic             ready_o,            // AMO unit is ready
+    input  ariane_pkg::amo_t amo_op_i,           // AMO Operation
+    input  logic [63:0]      paddr_i,            // physical address of store which needs to be placed in the queue
+    input  logic [63:0]      data_i,             // data which is placed in the queue
+    input  logic [1:0]       data_size_i,        // type of request we are making (e.g.: bytes to write)
+    // D$
+    output ariane_pkg::amo_req_t  amo_req_o,          // request to cache subsytem
+    input  ariane_pkg::amo_resp_t amo_resp_i,         // response from cache subsystem
+    // Auxiliary signals
+    input  logic amo_valid_commit_i, // We have a vaild AMO in the commit stage
+    input  logic no_st_pending_i     // there is currently no store pending anymore
+);
+    logic flush_amo_buffer;
+    logic amo_valid;
+
+    typedef struct packed {
+        ariane_pkg::amo_t        op;
+        logic [63:0] paddr;
+        logic [63:0] data;
+        logic [1:0]  size;
+    } amo_op_t ;
+
+    amo_op_t amo_data_in, amo_data_out;
+
+    // validate this request as soon as all stores have drained and the AMO is in the commit stage
+    assign amo_req_o.req = no_st_pending_i & amo_valid_commit_i & amo_valid;
+    assign amo_req_o.amo_op = amo_data_out.op;
+    assign amo_req_o.size = amo_data_out.size;
+    assign amo_req_o.operand_a = amo_data_out.paddr;
+    assign amo_req_o.operand_b = amo_data_out.data;
+
+    assign amo_data_in.op = amo_op_i;
+    assign amo_data_in.data = data_i;
+    assign amo_data_in.paddr = paddr_i;
+    assign amo_data_in.size = data_size_i;
+
+    // only flush if we are currently not committing the AMO
+    // e.g.: it is not speculative anymore
+    assign flush_amo_buffer = flush_i & !amo_valid_commit_i;
+
+    fifo_v2 #(
+        .DEPTH        ( 1                ),
+        .ALM_EMPTY_TH ( 0                ),
+        .ALM_FULL_TH  ( 0                ),
+        .dtype        ( amo_op_t         )
+    ) i_amo_fifo (
+        .clk_i        ( clk_i            ),
+        .rst_ni       ( rst_ni           ),
+        .flush_i      ( flush_amo_buffer ),
+        .testmode_i   ( 1'b0             ),
+        .full_o       ( amo_valid        ),
+        .empty_o      ( ready_o          ),
+        .alm_full_o   (  ), // left open
+        .alm_empty_o  (  ), // left open
+        .data_i       ( amo_data_in      ),
+        .push_i       ( valid_i          ),
+        .data_o       ( amo_data_out     ),
+        .pop_i        ( amo_resp_i.ack   )
+    );
+
+endmodule
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