Updated README.md

Signed-off-by: sakundu <sakundu@ucsd.edu>

Flows/README.md

@@ -82,7 +82,7 @@ The command to launch the P&R run is as follows.
 innovus -64 -init run_invs.tcl -log log/run.log
 ```  
 
-The screenshot of the Ariane 136 testcase using the Cadence Flow-1 on NanGate45 enablement is given below.  
+The screenshot of the Ariane 136 testcase using the Cadence Flow-1 on NanGate45 enablement is shown below.  
 <img src="./NanGate45/ariane136/screenshots/Ariane136_Innovus_Genus.png" alt="ariane136_cadence" width="400"/>
 
 This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.  
@@ -100,5 +100,5 @@ Clone ORFS and build OpenROAD tools following the steps given [here](https://git
   make DESIGN_CONFIG=./designs/<enablement>/<design>/config.mk
   ```
   
-The screenshot of the Ariane 136 testcase using the ORFS (RTL-MP) on NanGate45 enablement is given below.  
+The screenshot of the Ariane 136 testcase using the ORFS (RTL-MP) on NanGate45 enablement is shown below.  
 <img src="./NanGate45/ariane136/screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
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README.md

@@ -194,11 +194,12 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
 
 
 ## **Related Links**
-- R. Cheng and J. Yan, "On joint learning for solving placement and routing in chip design",
-*Proc. NeurIPS*, 2021. \[[paper](https://arxiv.org/pdf/2111.00234v1.pdf)\] \[[code](https://github.com/Thinklab-SJTU/EDA-AI)\]
 - F. -C. Chang, Y. -W. Tseng, Y. -W. Yu, S. -R. Lee, A. Cioba, et al., 
 "Flexible multiple-objective reinforcement learning for chip placement",
 *arXiv:2204.06407*, 2022. \[[paper](https://arxiv.org/pdf/2204.06407.pdf)\]
+- S. Yue, E. M. Songhori, J. W. Jiang, T. Boyd, A. Goldie, A. Mirhoseini and S. Guadarrama, "Scalability and Generalization of Circuit Training for Chip Floorplanning", *ISPD*, 2022. \[[paper](https://dl.acm.org/doi/abs/10.1145/3505170.3511478)\]\[[ppt](http://www.ispd.cc/slides/2021/protected/2_2_Goldie_Mirhoseini.pdf)\]
+- R. Cheng and J. Yan, "On joint learning for solving placement and routing in chip design",
+*Proc. NeurIPS*, 2021. \[[paper](https://arxiv.org/pdf/2111.00234v1.pdf)\] \[[code](https://github.com/Thinklab-SJTU/EDA-AI)\]
 - S. Guadarrama, S. Yue, T. Boyd, J. Jiang,  E. Songhori, et al.,
 "Circuit training: an open-source framework for generating chip floor plans with distributed deep reinforcement learning", 2021. \[[code](https://github.com/google-research/circuit_training)\]
 - A. Mirhoseini, A. Goldie, M. Yazgan, J. Jiang, E. Songhori, et al.,
@@ -207,7 +208,6 @@ while allowing soft macros (standard-cell clusters) to also find good locations.
 - A. Mirhoseini, A. Goldie, M. Yazgan, J. Jiang, E. Songhori, et al.,
 "Chip Placement with Deep Reinforcement Learning",
 *arXiv:2004.10746*, 2020. \[[paper](https://arxiv.org/pdf/2004.10746.pdf)\]
-- S. Yue, E. M. Songhori, J. W. Jiang, T. Boyd, A. Goldie, A. Mirhoseini and S. Guadarrama, "Scalability and Generalization of Circuit Training for Chip Floorplanning", *ISPD*, 2022. \[[paper](https://dl.acm.org/doi/abs/10.1145/3505170.3511478)\]\[[ppt](http://www.ispd.cc/slides/2021/protected/2_2_Goldie_Mirhoseini.pdf)\]
 - Z. Jiang, E. Songhori, S. Wang, A. Goldie, A. Mirhoseini, et al., "Delving into Macro Placement with Reinforcement Learning", *MLCAD*, 2021. \[[paper](https://arxiv.org/pdf/2109.02587)\]
 - A Gentle Introduction to Graph Neural Networks. [[Link](https://distill.pub/2021/gnn-intro/)]
 - TILOS AI Institute. \[[link](https://tilos.ai/)\]
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