Added protocol buffer format for synthesized netlist

Signed-off-by: sakundu <sakundu@ucsd.edu>

Flows/util/gen_pb.tcl

+#############################################################################
+# This script was written and developed by ABKGroup students at UCSD.
+# However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help 
+# promote and foster the next generation of innovators.
+# Author: Sayak Kundu, ABKGroup, UCSD
+#############################################################################
+
+#### Print the design header ####
+proc print_header { fp } {
+  set design [dbget top.name]
+  set user [exec whoami]
+  set date [exec date]
+  set run_dir [exec pwd]
+  set fp_box [dbget top.fplan.box]
+
+  puts $fp "# User: $user"
+  puts $fp "# Date: $date"
+  puts $fp "# Run area: $run_dir"
+  puts $fp "# Current_design: $design"
+  puts $fp "# FP bbox: $fp_box"
+}
+
+#### Print helper ####
+proc print_placeholder { fp key value } {
+  puts $fp "  attr {"
+  puts $fp "    key: \"$key\""
+  puts $fp "    value {"
+  puts $fp "      placeholder: \"$value\""
+  puts $fp "    }"
+  puts $fp "  }"
+}
+
+proc print_float { fp key value } {
+  puts $fp "  attr {"
+  puts $fp "    key: \"$key\""
+  puts $fp "    value {"
+  puts $fp "      f: $value"
+  puts $fp "    }"
+  puts $fp "  }"
+}
+
+### Helper to convert Orientation format ###
+proc get_orient { tmp_orient } {
+  set orient "N"
+  if { $tmp_orient == "R0"} {
+    set orient "N"
+  } elseif { $tmp_orient == "R180" } {
+    set orient "S"
+  } elseif { $tmp_orient == "R90" } {
+    set orient "W"
+  } elseif { $tmp_orient == "R270" } {
+    set orient "E"
+  } elseif { $tmp_orient == "MY" } {
+    set oreint "FN"
+  } elseif { $tmp_orient == "MX" } {
+    set oreint "FS"
+  } elseif { $tmp_orient == "MX90" } {
+    set orient "FW" 
+  } elseif { $tmp_orient == "MY90" } {
+    set orient "FE"
+  }
+
+  return $orient
+}
+
+#### Procedure to print the sinks ####
+proc print_net { net_ptr fp } {
+  ### Print Terms ###
+  foreach term [dbget [dbget ${net_ptr}.terms.isOutput 1 -p ].name -e] {
+    puts $fp "  input: \"${term}\""
+  }
+  
+  ### Print Macro Pins ###
+  foreach macro_pin [dbget [dbget [dbget ${net_ptr}.instTerms.isInput 1 -p \
+                    ].inst.isHaloBlock 1 -p2 ].name -e] {
+    puts $fp "  input: \"${macro_pin}\""
+  }
+  
+  ### Print Stdcells ###
+  foreach inst [dbget [dbget [dbget ${net_ptr}.instTerms.isInput 1 -p \
+                    ].inst.isHaloBlock 0 -p ].name -e] {
+    puts $fp "  input: \"${inst}\""
+  }
+}
+
+#### Procedure to write Ports ####
+proc write_node_port { port_ptr fp } {
+  puts $fp "node {"
+  
+  set name [lindex [dbget ${port_ptr}.name] 0]
+  puts $fp "  name: \"${name}\""
+  
+  set net_ptr [dbget ${port_ptr}.net]
+  print_net $net_ptr $fp
+
+  ### Attribute: type ###
+  print_placeholder $fp "type" "port"
+
+  ### Attribute: Side ###
+  set tmp_side [dbget ${port_ptr}.side]
+  set side ""
+  if {$tmp_side == "West"} {
+    set side "left"
+  } elseif {$tmp_side == "East"} {
+    set side "right"
+  } elseif {$tmp_side == "North"} {
+    set side "top"
+  } elseif {$tmp_side == "South"} {
+    set side "bottom"
+  } else {
+    puts "Error: Wrong Direction. Port Name: $name"
+  }
+  print_placeholder $fp "side" $side
+
+  ### Attribute: X ###
+  set X1 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 0]
+  set X2 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 2]
+  set X [expr ($X1 + $X2)/2]
+  print_float $fp "x" $X
+
+  ### Attribute: Y ###
+  set Y1 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 1]
+  set Y2 [lindex [dbget ${port_ptr}.pinShapes.rect] 0 3]
+  set Y [expr ($Y1 + $Y2)/2]
+  print_float $fp "y" $Y
+  
+  puts $fp "}"
+}
+
+#### Procedure to write Macros ####
+proc write_node_macro { macro_ptr fp } {
+  puts $fp "node {"
+
+  set name [lindex [dbget ${macro_ptr}.name] 0]
+  puts $fp "  name: \"${name}\""
+
+  ### Attribute: ref_name ###
+  set ref_name [dbget ${macro_ptr}.cell.name]
+  print_placeholder $fp "ref_name" ${ref_name}
+
+  ### Attribute: Width ###
+  set width [dbget ${macro_ptr}.box_sizex]
+  print_float $fp "width" $width
+
+  ### Attribute: Height ###
+  set height [dbget ${macro_ptr}.box_sizey]
+  print_float $fp "height" $height
+
+  ### Attribute: type ###
+  print_placeholder $fp "type" "macro"
+
+  ### Attribute: X ###
+  set X1 [lindex [dbget ${macro_ptr}.box] 0 0]
+  set X2 [lindex [dbget ${macro_ptr}.box] 0 2]
+  set X [expr ($X1 + $X2)/2]
+  print_float $fp "x" $X
+
+  ### Attribute: Y ###
+  set Y1 [lindex [dbget ${macro_ptr}.box] 0 1]
+  set Y2 [lindex [dbget ${macro_ptr}.box] 0 3]
+  set Y [expr ($Y1 + $Y2)/2]
+  print_float $fp "y" $Y
+  
+  ### Attribute: Y ###
+  set tmp_orient [dbget ${macro_ptr}.orient]
+  set orient [get_orient $tmp_orient]
+  print_placeholder $fp "orientation" $orient
+
+  puts $fp "}"
+}
+
+#### Procedure to Write Macro Pins ####
+proc write_node_macro_pin { macro_pin_ptr fp } {
+  puts $fp "node {"
+
+  set name [lindex [dbget ${macro_pin_ptr}.name] 0]
+  puts $fp "  name: \"${name}\""
+
+  ### Print all the sinks ###
+  if { [dbget ${macro_pin_ptr}.isOutput] == 1} {
+    set net_ptr [dbget ${macro_pin_ptr}.net]
+    print_net $net_ptr $fp
+  }
+
+  ### Attribute: Macro Name ###
+  set macro_name [lindex [dbget ${macro_pin_ptr}.inst.name] 0]
+  print_placeholder $fp "macro_name" $macro_name
+
+  ### Attribute: type ###
+  print_placeholder $fp "type" "macro_pin"
+  
+  set macro_x1 [lindex [dbget ${macro_pin_ptr}.inst.box] 0 0]
+  set macro_x2 [lindex [dbget ${macro_pin_ptr}.inst.box] 0 2]
+  set macro_y1 [lindex [dbget ${macro_pin_ptr}.inst.box] 0 1]
+  set macro_y2 [lindex [dbget ${macro_pin_ptr}.inst.box] 0 3]
+  set macro_x [expr ($macro_x1 + $macro_x2)/2]
+  set macro_y [expr ($macro_y1 + $macro_y2)/2]
+  set X [dbget ${macro_pin_ptr}.pt_x]
+  set Y [dbget ${macro_pin_ptr}.pt_y]
+  set x_offset [expr $X - $macro_x]
+  set y_offset [expr $Y - $macro_y]
+
+  ### Attribute: x_offset ###
+  print_float $fp "x_offset" $x_offset
+  
+  ### Attribute: y_offset ###
+  print_float $fp "y_offset" $y_offset
+
+  ### Attribute: X ###
+  print_float $fp "x" $X
+  
+  ### Attribute: Y ###
+  print_float $fp "y" $Y
+  
+  puts $fp "}"
+}
+
+#### Procedure to Write Std-cell ###
+proc write_node_stdcell { inst_ptr fp } {
+  puts $fp "node {"
+
+  set name [lindex [dbget ${inst_ptr}.name] 0]
+  puts $fp "  name: \"${name}\""
+
+  ### Print all the sinks ###
+  foreach net_ptr [dbget [dbget ${inst_ptr}.instTerms.isOutput 1 -p ].net -e ] {
+    print_net $net_ptr $fp
+  }
+
+  ### Attribute: ref_name ###
+  set ref_name [dbget ${inst_ptr}.cell.name]
+  print_placeholder $fp "ref_name" $ref_name
+
+  ### Attribute: Width ###
+  set width [dbget ${inst_ptr}.box_sizex]
+  print_float $fp "width" $width
+
+  ### Attribute: Height ###
+  set height [dbget ${inst_ptr}.box_sizey]
+  print_float $fp "height" $height
+
+  ### Attribute: type ###
+  print_placeholder $fp "type" "stdcell"
+
+  ### Attribute: X ###
+  set X1 [lindex [dbget ${inst_ptr}.box] 0 0]
+  set X2 [lindex [dbget ${inst_ptr}.box] 0 2]
+  set X [expr ($X1 + $X2)/2]
+  print_float $fp "x" $X
+
+  ### Attribute: Y ###
+  set Y1 [lindex [dbget ${inst_ptr}.box] 0 1]
+  set Y2 [lindex [dbget ${inst_ptr}.box] 0 3]
+  set Y [expr ($Y1 + $Y2)/2]
+  print_float $fp "y" $Y
+  
+  puts $fp "}"
+}
+
+#### Generate protobuff format netlist ####
+proc gen_pb_netlist { } {
+  set design [dbget top.name]
+  set out_file "${design}.pb.txt"
+  set fp [open $out_file w+]
+
+  print_header $fp
+
+  foreach port_ptr [dbget top.terms] {  
+    write_node_port $port_ptr $fp
+  }
+
+  foreach macro_ptr [dbget top.insts.isHaloBlock 1 -p] {
+    write_node_macro $macro_ptr $fp
+    foreach macro_pin_ptr [dbget ${macro_ptr}.instTerms] {
+      write_node_macro_pin $macro_pin_ptr $fp
+    }
+  }
+
+  foreach inst_ptr [dbget top.insts.isHaloBlock 0 -p] {
+    write_node_stdcell $inst_ptr $fp
+  }
+
+  close $fp
+  puts "Output netlist: $out_file"
+}

Flows/util/place_pin.tcl

+set y [dbget top.fplan.box_sizey]
+set y1 [expr $y*0.175]
+set y2 [expr $y - $y1]
+set layers [dbget [dbget head.layers.direction Horizontal -p ].name]
+set layer1 [lindex $layers 1]
+set layer2 [lindex $layers 2]
+
+set pin_layer [list $layer1 $layer2]
+set pt1 [list 0 $y1]
+set pt2 [list 0 $y2]
+set pin_list [dbget top.terms.name]
+editPin -pin $pin_list -edge 0 -start $pt1 -end $pt2 -fixedPin -layer $pin_layer -spreadDirection clockwise -pattern fill_optimised

Flows/util/run_grp.sh

+source /home/tool/anaconda3/etc/profile.d/conda.sh
+conda activate /home/zf4_projects/RTML/sakundu/env/sk-py
+export PYTHONPATH=$PYTHONPATH:$CT_PATH
+python -m circuit_training.grouping.grouper_main \
+--output_dir=$OUTPUT_DIR \
+--netlist_file=$NETLIST_FILE \
+--block_name=$BLOCK_NAME \
+--hmetis_dir=$HMETIS_DIR \
+--plc_wrapper_main=$PLC_WRAPPER_MAIN

Flows/util/run_grp_main.sh

+#!/usr/bin/env bash
+if [ $PHY_SYNTH -eq 1 ]; then
+    export BLOCK_NAME=`echo $PWD | awk -F'/' '{print $(NF-2)}'`
+    export TECH=`echo $PWD | awk -F'/' '{print $(NF-3)}'`
+    export OUTPUT_DIR="./output_${BLOCK_NAME}_${TECH}"
+    export NETLIST_FILE=`readlink -f *.pb.txt`
+    export HMETIS_DIR="/home/zf4_projects/DREAMPlace/sakundu/GB/CT/hmetis-1.5-linux"
+    export PLC_WRAPPER_MAIN="/home/zf4_projects/DREAMPlace/sakundu/GB/CT/plc_wrapper_main"
+    export CT_PATH="/home/zf4_projects/DREAMPlace/sakundu/GB/CT/circuit_training"
+    bash -i ../../../../util/run_grp.sh 2>&1 | tee log/grouping.log
+fi

Flows/util/write_required_def.tcl

+deselectAll
+set top_module [dbget top.name]
+
+if {[dbget top.terms.pStatus -v -e fixed] == "" } {
+    source ../../../../util/place_pin.tcl
+}
+
+exec mkdir -p def
+select_obj [dbget top.terms ]
+defOut -selected -floorplan ./def/${top_module}_fp.def
+
+dbset [dbget top.insts.isHaloBlock 1 -p ].pStatus placed
+selectInst [dbget [dbget top.insts.isHaloBlock 1 -p ].name]
+
+defOut -selected -floorplan ./def/${top_module}_fp_macro_placed.def
+dbset [dbget top.insts.isHaloBlock 1 -p ].pStatus fixed
+deselectAll
+
+#### Below files can be used in the Code element to generate clustered netlist ####
+defOut -netlist ./def/${top_module}.def
+saveNetlist -removePowerGround ./def/${top_module}.v
+saveNetlist -flat -removePowerGround ./def/${top_module}_flat.v

Testcases/ariane136/rtl/lzc.sv

+// Copyright (c) 2018 ETH Zurich, University of Bologna
+// All rights reserved.
+//
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+//
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+
+/// A trailing zero counter / leading zero counter.
+/// Set LZC to 0 for trailing zero counter => cnt_o is the number of trailing zeroes (from the LSB)
+/// Set LZC to 1 for leading zero counter  => cnt_o is the number of leading zeroes  (from the MSB)
+module lzc #(
+  /// The width of the input vector.
+  parameter int unsigned WIDTH = 2,
+  parameter int unsigned MODE  = 0
+) (
+  input  logic [WIDTH-1:0]         in_i,
+  output logic [$clog2(WIDTH)-1:0] cnt_o,
+  output logic                     empty_o // asserted if all bits in in_i are zero
+);
+
+  localparam int NUM_LEVELS = $clog2(WIDTH);
+
+  // pragma translate_off
+  initial begin
+    assert(WIDTH > 0) else $fatal("input must be at least one bit wide");
+  end
+  // pragma translate_on
+
+  logic [WIDTH-1:0][NUM_LEVELS-1:0]          index_lut;
+  logic [2**NUM_LEVELS-1:0]                  sel_nodes;
+  logic [2**NUM_LEVELS-1:0][NUM_LEVELS-1:0]  index_nodes;
+
+  logic [WIDTH-1:0] in_tmp;
+
+  // reverse vector if required
+  // assign in_tmp = MODE ? {<<{in_i}} : in_i;
+  always_comb begin : flip_vector
+    for (int unsigned i = 0; i < WIDTH; i++) begin
+      in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i];
+    end
+  end
+
+
+  for (genvar j = 0; j < WIDTH; j++) begin : g_index_lut
+    assign index_lut[j] = j;
+  end
+
+  for (genvar level = 0; level < NUM_LEVELS; level++) begin : g_levels
+    if (level == NUM_LEVELS-1) begin : g_last_level
+      for (genvar k = 0; k < 2**level; k++) begin : g_level
+        // if two successive indices are still in the vector...
+        if (k * 2 < WIDTH-1) begin
+          assign sel_nodes[2**level-1+k]   = in_tmp[k*2] | in_tmp[k*2+1];
+          assign index_nodes[2**level-1+k] = (in_tmp[k*2] == 1'b1) ? index_lut[k*2] :
+                                                                     index_lut[k*2+1];
+        end
+        // if only the first index is still in the vector...
+        if (k * 2 == WIDTH-1) begin
+          assign sel_nodes[2**level-1+k]   = in_tmp[k*2];
+          assign index_nodes[2**level-1+k] = index_lut[k*2];
+        end
+        // if index is out of range
+        if (k * 2 > WIDTH-1) begin
+          assign sel_nodes[2**level-1+k]   = 1'b0;
+          assign index_nodes[2**level-1+k] = '0;
+        end
+      end
+    end else begin
+      for (genvar l = 0; l < 2**level; l++) begin : g_level
+        assign sel_nodes[2**level-1+l]   = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1];
+        assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ? index_nodes[2**(level+1)-1+l*2] :
+                                                                                     index_nodes[2**(level+1)-1+l*2+1];
+      end
+    end
+  end
+
+  assign cnt_o   = NUM_LEVELS > 0 ? index_nodes[0] : '0;
+  assign empty_o = NUM_LEVELS > 0 ? ~sel_nodes[0]  : ~(|in_i);
+
+endmodule : lzc