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macroplacement
Commit 1f52e75e by sakundu
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Added protocol buffer format for synthesized netlist 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent d115d3d7
Showing with 60 additions and 13 deletions
Flows/ASAP7/ariane133/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/ASAP7/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -91,6 +91,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
......@@ -59,6 +59,8 @@ createBasicPathGroups -expanded
setFPlanMode -snapBlockGrid LayerTrack
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -77,7 +79,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/ASAP7/ariane136/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/ASAP7/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -91,6 +91,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
......@@ -59,6 +59,8 @@ createBasicPathGroups -expanded
setFPlanMode -snapBlockGrid LayerTrack
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -77,7 +79,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/ASAP7/mempool_tile/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -59,6 +59,8 @@ createBasicPathGroups -expanded
setFPlanMode -snapBlockGrid LayerTrack
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -77,7 +79,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/ASAP7/nvdla/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/ASAP7/nvdla/scripts/cadence/run_genus_hybrid.tcl
......@@ -92,6 +92,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
......@@ -59,6 +59,8 @@ createBasicPathGroups -expanded
setFPlanMode -snapBlockGrid LayerTrack
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -77,7 +79,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/NanGate45/ariane133/rtl/ariane.v
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Flows/NanGate45/ariane133/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
......@@ -58,6 +58,8 @@ createBasicPathGroups -expanded
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -75,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/NanGate45/ariane136/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
......@@ -58,6 +58,8 @@ createBasicPathGroups -expanded
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -75,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/NanGate45/mempool_tile/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -58,6 +58,8 @@ createBasicPathGroups -expanded
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -75,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/NanGate45/nvdla/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
......@@ -58,6 +58,8 @@ createBasicPathGroups -expanded
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -75,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/SKY130HD/ariane133/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/SKY130HD/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -91,6 +91,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
......@@ -57,12 +57,15 @@ createBasicPathGroups -expanded
## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
source ../../../../util/write_required_def.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc
......@@ -74,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/SKY130HD/ariane136/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/SKY130HD/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -91,6 +91,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
......@@ -57,6 +57,8 @@ createBasicPathGroups -expanded
## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -64,6 +66,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
source ../../../../util/write_required_def.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
......@@ -74,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/SKY130HD/mempool_tile/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/SKY130HD/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
......@@ -92,6 +92,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -57,6 +57,8 @@ createBasicPathGroups -expanded
## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
......@@ -64,6 +66,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place
}
source ../../../../util/write_required_def.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
......@@ -74,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/SKY130HD/nvdla/scripts/cadence/run.sh
......@@ -13,3 +13,4 @@ export PHY_SYNTH=0
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh
Flows/SKY130HD/nvdla/scripts/cadence/run_genus_hybrid.tcl
......@@ -93,6 +93,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
......@@ -57,12 +57,15 @@ createBasicPathGroups -expanded
## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl
gen_pb_netlist
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
source ../../../../util/write_required_def.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc
......@@ -74,7 +77,7 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
......
Flows/util/genJobList.py
......@@ -7,7 +7,7 @@ import time
testcases = ['ariane136', 'ariane133', 'mempool_tile', 'nvdla']
enablements = ['NanGate45', 'ASAP7', 'SKY130HD']
flows = [1, 2]
job_file = "all_jobs"
job_file = "./job/all_jobs"
fp = open(job_file, "w")
run_dir_name= f"run-{time.strftime('%Y%m%d-%H%M%S')}"
......
Testcases/ariane133/rtl/ariane.v
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