Added bp_quad testcase and updated the README

Flows/util/gen_macro_place_def.sh

 #!/bin/tcsh
 
 ## Set to 1 to run refine_macro_place ##
-setenv run_refine_macro_place 1
+setenv run_refine_macro_place 0
 
 setenv SYN_HANDOFF $argv[1]
 

Flows/util/run_grp_main.sh

@@ -11,7 +11,7 @@ if [ $PHY_SYNTH -eq 1 ]; then
     export HMETIS_DIR="/home/zf4_projects/DREAMPlace/sakundu/GB/CT/hmetis-1.5-linux"
     export PLC_WRAPPER_MAIN="/home/zf4_projects/DREAMPlace/sakundu/GB/CT/plc_wrapper_main"
     #export CT_PATH="${PROJ_DIR}/../../../GB/CT/circuit_training"
-    #export CT_PATH="/home/zf4_projects/DREAMPlace/sakundu/ABK_MP/CT/09092022/circuit_training"
-    export CT_PATH="/home/zf4_projects/macro_placer/google_brain/TILOS_repo/grouping/circuit_training"
+    export CT_PATH="/home/zf4_projects/DREAMPlace/sakundu/ABK_MP/CT/09092022/circuit_training"
+    #export CT_PATH="/home/zf4_projects/macro_placer/google_brain/TILOS_repo/grouping/circuit_training"
     bash -i ../../../../util/run_grp.sh 2>&1 | tee log/grouping.log
 fi

README.md

@@ -67,7 +67,7 @@ We provide flop count, macro type and macro count for all the testcases in the t
     <td class="tg-0lax">(256x64-bit SRAM) x 128</td>
   </tr>
   <tr>
-    <td class="tg-0lax"><a href="./Testcases/bp_quad">Black Parror</a></td>
+    <td class="tg-0lax"><a href="./Testcases/bp_quad">BlackParror</a></td>
     <td class="tg-0lax">214441</td>
     <td class="tg-0lax">(512x64-bit SRAM) x 128 + (64x62-bit SRAM) x 32 + (32x32-bit SRAM) x 32 + (64x124-bit SRAM) x 16 + (128x16-bit SRAM) x 8 + (256x48-bit SRAM) x 4</td>
   </tr>
@@ -208,16 +208,16 @@ In the following table, we provide the status details of each testcase on each o
   </tr>
   <tr>
     <td class="tg-0lax">black parrot</td>
-    <td class="tg-0lax"><a href="./Flows/NanGate45/nvdla">Link</a></td>
-    <td class="tg-0lax"><a href="./Flows/NanGate45/nvdla">Link</a></td>
+    <td class="tg-0lax"><a href="./Flows/NanGate45/bp_quad">Link</a></td>
+    <td class="tg-0lax"><a href="./Flows/NanGate45/bp_quad">Link</a></td>
+    <td class="tg-0lax">N/A</td>
+    <td class="tg-0lax">N/A</td>
+    <td class="tg-0lax">N/A</td>
+    <td class="tg-0lax">N/A</td>
     <td class="tg-0lax">N/A</td>
     <td class="tg-0lax">N/A</td>
-    <td class="tg-0lax"><a href="./Flows/ASAP7/nvdla">Link</a></td>
-    <td class="tg-0lax"><a href="./Flows/ASAP7/nvdla">Link</a></td>
     <td class="tg-0lax">N/A</td>
     <td class="tg-0lax">N/A</td>
-    <td class="tg-0lax"><a href="./Flows/SKY130HD/nvdla">Link</a></td>
-    <td class="tg-0lax"><a href="./Flows/SKY130HD/nvdla">Link</a></td>
     <td class="tg-0lax">N/A</td>
     <td class="tg-0lax">N/A</td>
   </tr>

Testcases/bp_quad/README.md

+# Netlist preparation of BlackParrot quad core
+BlackParrot is a RISC-V multicore design. We use the verilog netlist of BlackParrot quad core design from the [OpenROAD GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/src/black_parrot) repo. We will provide details setup to prepare netlist from the [BlackParrot GitHub](https://github.com/black-parrot/black-parrot) repo.
\ No newline at end of file

Testcases/mempool/README.md

-# Netlist preparation of mempool tile 
+# Netlist preparation of MemPool tile and MemPool group
 MemPool tile is part of MemPool which is an open-source many-core system targeting image processing applications. We downloaded the netlist from the [mempool](https://github.com/pulp-platform/mempool) GitHub repository. All the required SystemVerilog files are copied into the *./rtl* directory.
\ No newline at end of file