Add design bp_quad for Nangate45

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>

Flows/NanGate45/bp_quad/scripts/cadence/design_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+set DESIGN bsg_chip
+set sdc  ./sdc/bsg_chip.sdc
+set rtldir ./rtl
+
+#
+# DEF file for floorplan initialization
+#
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set floorplan_def ./def/bsg_chip_fp_placed_macros.def
+} else {
+    set floorplan_def ./def/bsg_chip_fp.def
+}
+#
+# Effort level during optimization in syn_generic -physical (or called generic) stage
+# possible values are : high, medium or low
+set GEN_EFF medium
+
+# Effort level during optimization in syn_map -physical (or called mapping) stage
+# possible values are : high, medium or low
+set MAP_EFF high
+#
+set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
+set HALO_WIDTH 5
+set TOP_ROUTING_LAYER 10

Flows/NanGate45/bp_quad/scripts/cadence/lib_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+# lib and lef, RC setup
+
+set platformdir "../../../../../Enablements/NanGate45/"
+
+set libdir "${platformdir}/lib"
+set lefdir "${platformdir}/lef"
+set qrcdir "${platformdir}/qrc"
+
+set_db init_lib_search_path { \
+    ${libdir} \
+    ${lefdir} \
+}
+
+
+set libworst "  
+    ${libdir}/NangateOpenCellLibrary_typical.lib \
+    ${libdir}/fakeram45_32x32.lib \
+    ${libdir}/fakeram45_128x116.lib \
+    ${libdir}/fakeram45_256x48.lib \
+    ${libdir}/fakeram45_512x64.lib \
+    ${libdir}/fakeram45_64x62.lib \
+    ${libdir}/fakeram45_64x124.lib \
+    "
+
+
+set libbest " 
+    ${libdir}/NangateOpenCellLibrary_typical.lib \
+    ${libdir}/fakeram45_32x32.lib \
+    ${libdir}/fakeram45_128x116.lib \
+    ${libdir}/fakeram45_256x48.lib \
+    ${libdir}/fakeram45_512x64.lib \
+    ${libdir}/fakeram45_64x62.lib \
+    ${libdir}/fakeram45_64x124.lib \
+    "
+
+set lefs "
+    ${lefdir}/NangateOpenCellLibrary.tech.lef \
+    ${lefdir}/NangateOpenCellLibrary.macro.mod.lef \
+    ${lefdir}/fakeram45_32x32.lef \
+    ${lefdir}/fakeram45_128x116.lef \
+    ${lefdir}/fakeram45_256x48.lef \
+    ${lefdir}/fakeram45_512x64.lef \
+    ${lefdir}/fakeram45_64x62.lef \
+    ${lefdir}/fakeram45_64x124.lef \
+    "
+
+set qrc_max "${qrcdir}/NG45.tch"
+set qrc_min "${qrcdir}/NG45.tch"
+#
+# Ensures proper and consistent library handling between Genus and Innovus
+#set_db library_setup_ispatial true
+setDesignMode -process 45 

Flows/NanGate45/bp_quad/scripts/cadence/mmmc_iSpatial_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
+#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
+ 
+create_timing_condition -name timing_wc  -library_sets { WC_LIB }
+create_timing_condition -name timing_bc  -library_sets { BC_LIB }
+ 
+create_rc_corner -name Cmax -qrc_tech $qrc_max
+create_rc_corner -name Cmin -qrc_tech $qrc_min
+
+create_delay_corner -name WC -early_timing_condition { timing_wc } \
+                             -late_timing_condition  { timing_wc } \
+                             -early_rc_corner          Cmax        \
+                             -late_rc_corner           Cmax
+
+create_delay_corner -name BC -early_timing_condition { timing_bc } \
+                             -late_timing_condition  { timing_bc } \
+                             -early_rc_corner          Cmin        \
+                             -late_rc_corner           Cmin
+
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
+ 
+set_analysis_view -setup WC_VIEW -hold BC_VIEW

Flows/NanGate45/bp_quad/scripts/cadence/mmmc_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+create_rc_corner -name Cmax
+create_rc_corner -name Cmin
+
+
+create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
+create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON

Flows/NanGate45/bp_quad/scripts/cadence/rtl_list.tcl

+set rtl_all {
+  ./rtl/bsg_chip_block.sv2v.v
+}

Flows/NanGate45/bp_quad/scripts/cadence/run.sh

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+#!/bin/tcsh
+module unload genus
+module load genus/21.1
+module unload innovus
+module load innovus/21.1
+
+#
+# To run the Physical Synthesis (iSpatial) flow - flow2
+export PHY_SYNTH=0
+
+mkdir log -p
+genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
+#innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
+#../../../../util/run_CodeFlow.sh

Flows/NanGate45/bp_quad/scripts/cadence/run_genus.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+set_db library $list_lib
+
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/NanGate45/bp_quad/scripts/cadence/run_genus_hybrid.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_mmmc mmmc_iSpatial_setup.tcl
+}
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+    read_physical -lefs $lefs
+}
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set pathi
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    set_db library $list_lib
+}
+
+#################################################
+# Load Design and Initialize
+#################################################
+set_db init_hdl_search_path $rtldir 
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
+    #read_sdc $sdc
+    source $sdc
+}
+
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    read_def $floorplan_def
+    check_floorplan -detailed
+}
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_generic -physical
+} else {
+    syn_generic
+    write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
+}
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+ 
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_map -physical
+} else {
+    syn_map
+}
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    syn_opt -spatial
+} else {
+    syn_opt
+}
+
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+} else {
+    write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+    write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+}
+
+exit

Flows/NanGate45/bp_quad/scripts/cadence/run_genus_iSpatial.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+read_mmmc mmmc_iSpatial_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+read_physical -lefs $lefs
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+#set_db library $list_lib
+
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+#read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+read_def $floorplan_def
+check_floorplan -detailed
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic -physical
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map -physical
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt -spatial
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/NanGate45/bp_quad/scripts/cadence/run_invs.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+source mmmc_setup.tcl
+
+setMultiCpuUsage -localCpu 16
+set util 0.3
+
+set handoff_dir  "./syn_handoff"
+
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
+
+set rptDir summaryReport/ 
+set encDir enc/
+
+if {![file exists $rptDir/]} {
+    exec mkdir $rptDir/
+}
+
+if {![file exists $encDir/]} {
+    exec mkdir $encDir/
+}
+
+# default settings
+set init_pwr_net VDD
+set init_gnd_net VSS
+
+# default settings
+set init_verilog "$netlist"
+set init_design_netlisttype "Verilog"
+set init_design_settop 1
+set init_top_cell "$DESIGN"
+set init_lef_file "$lefs"
+
+# MCMM setup
+init_design -setup {WC_VIEW} -hold {BC_VIEW}
+set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
+
+set_interactive_constraint_modes {CON}
+
+clearGlobalNets
+globalNetConnect VDD -type pgpin -pin VDD -inst * -override
+globalNetConnect VSS -type pgpin -pin VSS -inst * -override
+globalNetConnect VDD -type tiehi -inst * -override
+globalNetConnect VSS -type tielo -inst * -override
+
+
+setOptMode -powerEffort low -leakageToDynamicRatio 0.5
+setGenerateViaMode -auto true
+generateVias
+
+# basic path groups
+createBasicPathGroups -expanded
+
+## Generate the floorplan ##
+if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
+    defIn ${handoff_dir}/${DESIGN}.def
+    source ../../../../util/gen_pb.tcl
+    gen_pb_netlist
+} else {
+    defIn $floorplan_def
+    addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
+    place_design -concurrent_macros
+    refine_macro_place
+}
+
+### Write out the def files ###
+source ../../../../util/write_required_def.tcl
+
+### Add power plan ###
+source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
+source ../../../../util/pdn_flow.tcl
+
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
+
+setPlaceMode -place_detail_legalization_inst_gap 1
+setFillerMode -fitGap true
+setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
+setDesignMode -bottomRoutingLayer 2 
+
+place_opt_design -out_dir $rptDir -prefix place
+saveDesign $encDir/${DESIGN}_placed.enc
+
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_pre_cts [extract_report preCTS]
+echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
+
+set_ccopt_property post_conditioning_enable_routing_eco 1
+set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
+setOptMode -unfixClkInstForOpt false
+
+create_ccopt_clock_tree_spec
+ccopt_design
+
+set_interactive_constraint_modes [all_constraint_modes -active]
+set_propagated_clock [all_clocks]
+set_clock_propagation propagated
+
+saveDesign $encDir/${DESIGN}_cts.enc
+set rpt_post_cts [extract_report postCTS]
+echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
+
+# ------------------------------------------------------------------------------
+# Routing
+# ------------------------------------------------------------------------------
+setNanoRouteMode -drouteVerboseViolationSummary 1
+setNanoRouteMode -routeWithSiDriven true
+setNanoRouteMode -routeWithTimingDriven true
+setNanoRouteMode -routeUseAutoVia true
+
+##Recommended by lib owners
+# Prevent router modifying M1 pins shapes
+setNanoRouteMode -routeWithViaInPin "1:1"
+setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
+
+## limit VIAs to ongrid only for VIA1 (S1)
+setNanoRouteMode -drouteOnGridOnly "via 1:1"
+setNanoRouteMode -drouteAutoStop false
+setNanoRouteMode -drouteExpAdvancedMarFix true
+setNanoRouteMode -routeExpAdvancedTechnology true
+
+#SM suggestion for solving long extraction runtime during GR
+setNanoRouteMode -grouteExpWithTimingDriven false
+
+routeDesign
+#route_opt_design
+saveDesign ${encDir}/${DESIGN}_route.enc
+
+### Run DRC and LVS ###
+verify_connectivity -error 0 -geom_connect -no_antenna
+verify_drc -limit 0
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
+defOut -netlist -floorplan -routing ${DESIGN}_route.def
+
+summaryReport -noHtml -outfile summaryReport/post_route.sum
+saveDesign ${encDir}/${DESIGN}.enc
+defOut -netlist -floorplan -routing ${DESIGN}.def
+
+exit