The list of available [testcases](./Testcases) is as follows.
- Ariane (RTL)
-[RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist available in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
-[RTL files for Ariane design with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connections of the 136 macro version.
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@@ -23,7 +23,39 @@ The list of available testcases is as follows.
-[RTL files for NVDLA Partition *c*](./Testcases/nvdla/)
In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps to instantiate the memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's memory macros count [here](./Testcases/ariane133/).
We provide flop count, macro type and macro count for all the testcases in the the following table.
<tableclass="tg">
<thead>
<tr>
<thclass="tg-0lax">Testcase</th>
<thclass="tg-0lax">Flop Count</th>
<thclass="tg-0lax">Macro Details (macro type x macro count)</th>
