Updated the README.md

README.md

@@ -11,7 +11,7 @@
   - [Related Links](#related-links)
 
 ## **Testcases**  
-The list of avaialbe test cases
+The list of avaialbe testcases
 - Ariane (RTL)
   - [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
   - [RTL files for Ariane designs with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connection of 136 macro version.
@@ -19,12 +19,12 @@ The list of avaialbe test cases
   - [RTL files for Mempool tile design](./Testcases/mempool_tile/)
   - RTL files for Mempool group design
   
-In this [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), authors have used Ariane design with 133 memory (256x16, single ported SRAM) macros as one of the test cases. We noticed synthesizing the available Ariane netlist in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository with 256x16 memory results in Ariane design with 136 memory macros ([Here](./Testcases/ariane136/) we show how we instantiate memories for Ariane 136). [Here](./Testcases/ariane133/) we show how we convert the Ariane 136 design to Ariane 133 design. So, we added these two versions to our testcase list. 
+In this [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), authors have used Ariane design with 133 memory (256x16, single ported SRAM) macros as one of the testcases. We noticed synthesizing the available Ariane netlist in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository with 256x16 memory results in Ariane design with 136 memory macros ([Here](./Testcases/ariane136/) we show how we instantiate memories for Ariane 136). [Here](./Testcases/ariane133/) we show how we convert the Ariane 136 design to Ariane 133 design. So, we added these two versions to our testcase list. 
 MemPool tile design is another testcase and we will be adding MemPool group in this list.  
   
 
-Here we provide the detailed steps to generate the netlist for each test case. This netlist is used for the SP&R runs. The directory structure is as follows *./Testcases/\<testcase\>/<rtl\|sv2v>/*. 
-  - *rtl* directory contains all the required rtl files to synthesize the test case.
+Here we provide the detailed steps to generate the netlist for each testcase. This netlist is used for the SP&R runs. The directory structure is as follows *./Testcases/\<testcase\>/<rtl\|sv2v>/*. 
+  - *rtl* directory contains all the required rtl files to synthesize the testcase.
   - If the main repository contains only the SystemVerilog files, we add the converted Verilog file to the sv2v directory.
 
 ## **Enablements**
@@ -39,14 +39,14 @@ The list of available enablements
 Also, we provide steps to generate the fakerams.
 
 ## **Flows**
-Synthesis, place and route (SP&R) flow is available for each test case on each enablement. Here is the list
+Synthesis, place and route (SP&R) flow is available for each testcase on each enablement. Here is the list
 - NanGate45
   - [SP&R flows for Ariane design with 136 macros](./Flows/NanGate45/ariane136/)
   - [SP&R flows for Ariane design with 133 macros](./Flows/NanGate45/ariane133/)
   - [SP&R flows for MemPool tile design](./Flows/NanGate45/mempool_tile/)
   - MemPool group
 
-Here we provide detailed information to run SP&R for each test case using the open-source tools Yosys (synthesis) and OpenROAD (P&R), and the commercial tools Cadence Genus (synthesis) and Innovus (P&R).  
+Here we provide detailed information to run SP&R for each testcase using the open-source tools Yosys (synthesis) and OpenROAD (P&R), and the commercial tools Cadence Genus (synthesis) and Innovus (P&R).  
 The directory structure is as follows *./FLows/\<enablement\>/\<testcase\>/<constraint\|def\|netlist\|scripts\|run>/*. Here
 - *constraint* directory contains the *.sdc* file.
 - *def* directory contains the def file with pin placement and die area information.