The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases.
In this enablement each of the five routing layers and four cut layers has different lef properties (.e.g, minimum spacing, width, enclosure, etc.). Consider the five layrs of the metal stack are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as our one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x<sub>1</sub>Ma_x<sub>2</sub>Mb_x<sub>3</sub>Mc_x<sub>4</sub>Md_1Me, where x<sub>i</sub> is greater or equal to one.
In this enablement, each of the five routing layers and four cut layers have different lef properties (.e.g, minimum spacing, width, enclosure, etc.). Consider the five layers of the metal stack are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x<sub>1</sub>Ma_x<sub>2</sub>Mb_x<sub>3</sub>Mc_x<sub>4</sub>Md_1Me, where x<sub>i</sub> is greater or equal to one.
We use the bsg_fakeram memory generator available in the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) GitHub repo to generate the required SRAMs. The [sky130hd.cfg](./util/sky130hd.cfg) is the configuration file used to generate all the required memories.
With this combined enablement, testcases with SRAMs can be synthesized, placed and routed using both proprietary (commercial) tools such as Cadence Genus/Innovus, and open-source tools such as OpenROAD.
The [*./lef*](./lef) directory contains the technology, standard cell and macro lef files, the [*./lib*](./lib/) directory contains the standard cell and macro liberty files and the [*./qrc*](./qrc/) directory contains the qrc technology file.
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The [*./lef*](./lef) directory contains the technology, standard cell and macro lef files, the [*./lib*](./lib/) directory contains the standard cell and macro liberty files.
-[RTL files for Mempool tile design](./Testcases/mempool_tile/)
- RTL files for Mempool group design
- NVDLA (RTL)
-[RTL files for NVDLA Partition *c*](./Testcases/nvdla/)
In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps instantiate memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's SRAM count [here](./Testcases/ariane133/).
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@@ -30,7 +32,7 @@ All the testcases are available under the [Testcases](./Testcases/) directory. D
The list of available enablements
-[NanGate45](./Enablements/NanGate45/)
-[ASAP7](./Enablements/ASAP7/)
-SKY130HD
-[SKY130HD FakeStack](./Enablements/SKY130HD/)
Open-source enablements NanGate45 and ASAP7 are utilized in our SP&R flow. All the enablements are available under [Enablements](./Enablements) directory. Details of the sub-directories of each enablements:
-*lib* directory contains all the required liberty files.
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@@ -62,7 +64,7 @@ In the table below, we provide the details of each testcase on each of the enabl
