Upddate scripts for ariane133

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>

Flows/NanGate45/ariane133/scripts/cadence/design_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+set DESIGN ariane 
+set sdc  ../../constraints/${DESIGN}.sdc
+
+# def file with die size and placed IO pins
+set floorplan_def ../../def/ariane133_fp.def
+#
+# Effort level during optimization in syn_generic -physical (or called generic) stage
+# possible values are : high, medium or low
+set GEN_EFF medium
+
+# Effort level during optimization in syn_map -physical (or called mapping) stage
+# possible values are : high, medium or low
+set MAP_EFF high

Flows/NanGate45/ariane133/scripts/cadence/lib_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+# lib and lef, RC setup
+
+set libdir "../../../../../Enablements/NanGate45/lib"
+set lefdir "../../../../../Enablements/NanGate45/lef"
+
+set_db init_lib_search_path { \
+    ${libdir} \
+    ${lefdir} \
+}
+
+set libworst "  
+    ${libdir}/NangateOpenCellLibrary_typical.lib \
+    ${libdir}/fakeram45_256x16.lib \
+    ${libdir}/fakeram45_256x64.lib \
+    "
+
+
+set libbest " 
+    ${libdir}/NangateOpenCellLibrary_typical.lib \
+    ${libdir}/fakeram45_256x16.lib \
+    ${libdir}/fakeram45_256x64.lib \
+    "
+
+set lefs "  
+    ${lefdir}/NangateOpenCellLibrary.tech.lef \
+    ${lefdir}/NangateOpenCellLibrary.macro.mod.lef \
+    ${lefdir}/fakeram45_256x16.lef \
+    ${lefdir}/fakeram45_256x64.lef \
+    "
+#
+# Ensures proper and consistent library handling between Genus and Innovus
+#set_db library_setup_ispatial true
+
+
+#set qrc_max "SigCmax/qrcTechFile"
+#set qrc_min "SigCmin/qrcTechFile"

Flows/NanGate45/ariane133/scripts/cadence/mmmc_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+create_rc_corner -name Cmax
+create_rc_corner -name Cmin
+
+
+create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
+create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON

Flows/NanGate45/ariane133/scripts/cadence/rtl_list.tcl

+set rtl_all {
+  ../../rtl/ariane.v
+}

Flows/NanGate45/ariane133/scripts/cadence/run.sh

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 #!/bin/tcsh
 module unload genus
@@ -8,4 +8,4 @@ module load innovus/21.1
 
 mkdir log -p
 genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
-innovus -64 -init run_invs.tcl -log log/run.log
+#innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log

Flows/NanGate45/ariane133/scripts/cadence/run_genus.tcl

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
-set top_module ariane 
-set_db max_cpus_per_server 16
-set libdir "../../../../../Enablements/NanGate45/lib/"
+source lib_setup.tcl
+source design_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
 
-set libworst "
-    ${libdir}/NangateOpenCellLibrary_typical.lib \
-    ${libdir}/fakeram45_256x16.lib \
-    ${libdir}/fakeram45_256x64.lib \
-    "
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
 
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
 set list_lib "$libworst"
 
 # Target library
@@ -17,51 +31,70 @@ set link_library $list_lib
 set target_library $list_lib
 
 # set path
-set_db auto_ungroup none 
-set_db init_lib_search_path $libdir
-set_db init_hdl_search_path "../../rtl/"
+set_db auto_ungroup none
 
 set_db library $list_lib
-set_dont_touch fakeram45_256x16
 
-# Start
-if {[file exists template]} {
-	exec rm -rf template
-}
 
-exec mkdir template
-if {![file exists gate]} {
-	exec mkdir gate
-}
+#################################################
+# Load Design and Initialize
+#################################################
 
-if {![file exists rpt]} {
-	exec mkdir rpt
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -sv $rtl_file
 }
 
-# Compiler drectives
-set compile_effort "high"
-set compile_flatten_all 1
-set compile_no_new_cells_at_top_level false
+elaborate $DESIGN
+time_info Elaboration
 
-# read RTL
-read_hdl ../../rtl/ariane.v 
+read_sdc $sdc
+init_design
 
-elaborate $top_module 
+check_design -unresolved
 
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
 
-# Default SDC Constraints
-read_sdc ../../constraints/${top_module}.sdc
+# keep hierarchy during synthesis
+set_db auto_ungroup none
 
 syn_generic
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
 syn_map
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
 
-write_sdc > gate/${top_module}.sdc
-write_hdl > gate/${top_module}.v
-write_script > constraints.g
+syn_opt
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
 
-# Write Reports
-redirect [format "%s%s%s" rpt/ $top_module _area.rep] { report_area }
-redirect [format "%s%s%s" rpt/ $top_module _cell.rep] { report_gates }
-redirect [format "%s%s%s" rpt/ $top_module _timing.rep] { report_timing }
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
 
 exit
+

Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl

-# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+source mmmc_setup.tcl
+
 setMultiCpuUsage -localCpu 16
-set design ariane 
 set util 0.3
 
-set dir "../../../../../Enablements/NanGate45/"
-set netlist "./gate/$design.v"
-set sdc "../../constraints/$design.sdc"
-set lef "${dir}/lef/NangateOpenCellLibrary.tech.lef \
-        ${dir}/lef/NangateOpenCellLibrary.macro.mod.lef \
-        ${dir}/lef/fakeram45_256x16.lef \
-        ${dir}/lef/fakeram45_256x64.lef"
-
-set wc_lib_list [list $dir/lib/NangateOpenCellLibrary_typical.lib $dir/lib/fakeram45_256x16.lib $dir/lib/fakeram45_256x64.lib]
-set bc_lib_list [list $dir/lib/NangateOpenCellLibrary_typical.lib $dir/lib/fakeram45_256x16.lib $dir/lib/fakeram45_256x64.lib]
+set netlist "./syn_handoff/$DESIGN.v"
+set sdc "./syn_handoff/$DESIGN.sdc"
 
-create_library_set -name WC_LIB -timing $wc_lib_list
-create_library_set -name BC_LIB -timing $bc_lib_list
-	
 set site "FreePDK45_38x28_10R_NP_162NW_34O"
 
 set rptDir summaryReport/ 
@@ -35,22 +27,12 @@ if {![file exists $encDir/]} {
 set init_pwr_net VDD
 set init_gnd_net VSS
 
-create_rc_corner -name Cmax
-create_rc_corner -name Cmin
-create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
-create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
-
-create_constraint_mode -name CON -sdc_file [list $sdc]
-
-create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
-create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
-
 # default settings
 set init_verilog "$netlist"
 set init_design_netlisttype "Verilog"
 set init_design_settop 1
-set init_top_cell "$design"
-set init_lef_file "$lef"
+set init_top_cell "$DESIGN"
+set init_lef_file "$lefs"
 
 # MCMM setup
 init_design -setup {WC_VIEW} -hold {BC_VIEW}
@@ -74,13 +56,16 @@ generateVias
 createBasicPathGroups -expanded
 
 ## Generate the floorplan ##
-floorPlan -r 1.0 $util 10 10 10 10
+#floorPlan -r 1.0 $util 10 10 10 10
+defIn $floorplan_def 
 
 ## Macro Placement ##
-redirect mp_config.tcl {source gen_mp_config.tcl}
-proto_design -constraints mp_config.tcl 
+#redirect mp_config.tcl {source gen_mp_config.tcl}
+#proto_design -constraints mp_config.tcl 
+addHaloToBlock -allMacro 5 5 5 5
+place_design -concurrent_macros
 refine_macro_place
-saveDesign ${encDir}/${design}_floorplan.enc
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 ## Creating Pin Blcokage for lower and upper pin layers ##
 createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
@@ -97,10 +82,10 @@ setNanoRouteMode -drouteVerboseViolationSummary 1
 setNanoRouteMode -routeWithSiDriven true
 setNanoRouteMode -routeWithTimingDriven true
 setNanoRouteMode -routeExpUseAutoVia true
-setPlaceMode -placeIoPins true
+#setPlaceMode -placeIoPins true
 
 place_opt_design -out_dir $rptDir -prefix place
-saveDesign $encDir/${design}_placed.enc
+saveDesign $encDir/${DESIGN}_placed.enc
 
 ## Creating Pin Blcokage for lower and upper pin layers ##
 createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
@@ -119,8 +104,8 @@ setNanoRouteMode -routeExpUseAutoVia true
 setPlaceMode -placeIoPins true
 
 place_opt_design -out_dir $rptDir -prefix place
-saveDesign $encDir/${design}_placed.enc
-defOut -netlist -floorplan ${design}_placed.def
+saveDesign $encDir/${DESIGN}_placed.enc
+defOut -netlist -floorplan ${DESIGN}_placed.def
 
 set_ccopt_property post_conditioning_enable_routing_eco 1
 set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
@@ -160,8 +145,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
 
 
 routeDesign
-saveDesign ${encDir}/${design}_route.enc
-defOut -netlist -floorplan -routing ${design}_route.def
+saveDesign ${encDir}/${DESIGN}_route.enc
+defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
 setDelayCalMode -reset 
 setDelayCalMode -SIAware true
@@ -169,15 +154,15 @@ setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
 setAnalysisMode -analysisType onChipVariation -cppr both
 
 # routeOpt
-optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
+#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
 
-extractRC
+#extractRC
 deselectAll
 selectNet -clock
 reportSelect  > summaryReport/clock_net_length.post_route
 deselectAll
 summaryReport -noHtml -outfile summaryReport/post_route.sum
-saveDesign ${encDir}/${design}.enc
-defOut -netlist -floorplan -routing ${design}.def
+saveDesign ${encDir}/${DESIGN}.enc
+defOut -netlist -floorplan -routing ${DESIGN}.def
 
 exit