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Commit 939d058b by sakundu
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Added Process node to lib_setup.tcl, Updated MemPool tile-ASAP7 Def, updated read sdc to source sdc 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent bfd4e5d3
Showing with 31 additions and 23 deletions
Flows/ASAP7/ariane133/scripts/cadence/lib_setup.tcl
......@@ -26,3 +26,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/ASAP7/ariane136/scripts/cadence/lib_setup.tcl
......@@ -26,3 +26,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/ASAP7/mempool_tile/def/mempool_tile_wrap_fp.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/mempool_tile/def/mempool_tile_wrap_fp_placed_macros.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/mempool_tile/scripts/cadence/lib_setup.tcl
......@@ -27,3 +27,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc
......@@ -7,7 +7,7 @@
# with this distribution for more information.
# ===================================================================
set_max_area 0
#set_max_area 0
set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
......
Flows/ASAP7/nvdla/def/NV_NVDLA_partition_c_fp.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/nvdla/def/NV_NVDLA_partition_c_fp_placed_macros.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/nvdla/scripts/cadence/lib_setup.tcl
......@@ -26,3 +26,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/nvdla/scripts/cadence/run_genus_hybrid.tcl
......@@ -65,7 +65,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/NanGate45/ariane133/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 45
Flows/NanGate45/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/NanGate45/ariane136/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 45
Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/NanGate45/mempool_group/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set lefs "
#set qrc_max "SigCmax/qrcTechFile"
#set qrc_min "SigCmin/qrcTechFile"
setDesignMode -process 45
Flows/NanGate45/mempool_group/scripts/cadence/run_invs.tcl
......@@ -41,7 +41,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/NanGate45/mempool_tile/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set lefs "
set qrc_max "${qrcdir}/NG45.tch"
set qrc_min "${qrcdir}/NG45.tch"
setDesignMode -process 45
Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/NanGate45/nvdla/constraints/NV_NVDLA_partition_c.sdc
......@@ -7,7 +7,7 @@
# with this distribution for more information.
# ===================================================================
set_max_area 0
#set_max_area 0
set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
......
Flows/NanGate45/nvdla/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 45
Flows/NanGate45/nvdla/scripts/cadence/run_genus_hybrid.tcl
......@@ -67,7 +67,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/SKY130HD/ariane133/scripts/cadence/lib_setup.tcl
......@@ -33,3 +33,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 130
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/SKY130HD/ariane136/scripts/cadence/lib_setup.tcl
......@@ -33,3 +33,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 130
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/SKY130HD/mempool_tile/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 130
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/SKY130HD/nvdla/scripts/cadence/lib_setup.tcl
......@@ -33,3 +33,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 130
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
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