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Commit 87b9aeb4 by sakundu
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Added Hier-RTLMP GF12 results 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent e52d1b6f
Showing with 85 additions and 1 deletions
Docs/OurProgress/README.md
...@@ -4464,7 +4464,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo ...@@ -4464,7 +4464,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<img width="300" src="./images/Ariane133_GF12_AutoDMP_Place.png" alg="Ariane133_GF12_AutoDMP_Place"> <img width="300" src="./images/Ariane133_GF12_AutoDMP_Place.png" alg="Ariane133_GF12_AutoDMP_Place">
<img width="300" src="./images/Ariane133_GF12_AutoDMP_Route.png" alg="Ariane133_GF12_AutoDMP_Route"> <img width="300" src="./images/Ariane133_GF12_AutoDMP_Route.png" alg="Ariane133_GF12_AutoDMP_Route">
</p> </p>
<a id="Ariane133_GF12_HierRTLMP"></a> <a id="Ariane133_GF12_HierRTLMP"></a>
- (Updated on April 30, 2023) The following table and screenshots provide details of Ariane133-GF12 implementation when Hier-RTLMP is used to generate the macro placement. - (Updated on April 30, 2023) The following table and screenshots provide details of Ariane133-GF12 implementation when Hier-RTLMP is used to generate the macro placement.
...@@ -5085,6 +5085,83 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo ...@@ -5085,6 +5085,83 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<img width="300" src="./images/BlackParrot_GF12_Tuned_CMP_Route.png" alg="BlackParrot_GF12_Tuned_CMP_Route"> <img width="300" src="./images/BlackParrot_GF12_Tuned_CMP_Route.png" alg="BlackParrot_GF12_Tuned_CMP_Route">
</p> </p>
- **BlackParrot (Quad-Core)-GF12-68% CT**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by CT.
<table>
<thead>
<tr>
<th colspan="10"><p align="center">BlackParrot-GF12-68% CT (wirelength cost: 0.0756, congestion cost: 0.7329, density cost: 0.6526, proxy cost: 0.7684) (<a href="https://tensorboard.dev/experiment/a7nJdlJ5QYaK064Es1w7CQ/#scalars">Link</a> to tensorboard)</p></th>
</tr>
</thead>
<tbody>
<tr>
<td>Physical Design Stage</td>
<td>Core Area (um^2)</td>
<td>Standard Cell Area (um^2)</td>
<td>Macro Area (um^2)</td>
<td>Total Power (mW)</td>
<td>Wirelength (um)</td>
<td>WS (ns)</td>
<td>TNS (ns)</td>
<td>Congestion (H)</td>
<td>Congestion (V)</td>
</tr>
<tr>
<td>preCTS</td>
<td>1</td>
<td>0.190</td>
<td>0.498</td>
<td>1.083</td>
<td>1.568</td>
<td>-0.108</td>
<td>-244.624</td>
<td>2.00</td>
<td>1.80</td>
</tr>
<tr>
<td>postCTS</td>
<td>1</td>
<td>0.192</td>
<td>0.498</td>
<td>1.238</td>
<td>1.572</td>
<td>-0.087</td>
<td>-115.327</td>
<td>2.00</td>
<td>2.00</td>
</tr>
<tr>
<td>postRoute</td>
<td>1</td>
<td>0.192</td>
<td>0.498</td>
<td>1.223</td>
<td>1.605</td>
<td>-0.209</td>
<td>-270.951</td>
<td></td>
<td></td>
</tr>
<tr>
<td>postRouteOpt</td>
<td>1</td>
<td>0.191</td>
<td>0.498</td>
<td>1.219</td>
<td>1.606</td>
<td>-0.089</td>
<td>-66.473</td>
<td></td>
<td></td>
</tr>
</tbody>
</table>
<p align="center">
<img width="300" src="./images/BlackParrot_GF12_Tuned_CT_Place.png" alg="BlackParrot_GF12_Tuned_CT_Place">
<img width="300" src="./images/BlackParrot_GF12_Tuned_CT_Route.png" alg="BlackParrot_GF12_Tuned_CT_Route">
</p>
- **BlackParrot (Quad-Core)-GF12-68% SA**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by SA. - **BlackParrot (Quad-Core)-GF12-68% SA**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by SA.
<table> <table>
...@@ -5316,6 +5393,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo ...@@ -5316,6 +5393,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<img width="300" src="./images/BlackParrot_GF12_Tuned_AutoDMP_Route.png" alg="BlackParrot_GF12_Tuned_AutoDMP_Route"> <img width="300" src="./images/BlackParrot_GF12_Tuned_AutoDMP_Route.png" alg="BlackParrot_GF12_Tuned_AutoDMP_Route">
</p> </p>
<a id="BlackParrot_GF12_HierRTLMP"></a>
- **BlackParrot (Quad-Core)-GF12-68% Hier-RTLMP**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by Hier-RTLMP. - **BlackParrot (Quad-Core)-GF12-68% Hier-RTLMP**: The subsequent table and screenshots presents the post P\&R details of BlackParrot (Quad-Core) design on GF12 enablement when the macro placement is generated by Hier-RTLMP.
<table> <table>
...@@ -5779,6 +5857,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo ...@@ -5779,6 +5857,7 @@ We have run CT to generate macro placements for Ariane133, BlackParrot and MemPo
<img width="300" src="./images/MemPool_Group_GF12_Tuned_AutoDMP_Route.png" alg="MemPool_Group_GF12_Tuned_AutoDMP_Route"> <img width="300" src="./images/MemPool_Group_GF12_Tuned_AutoDMP_Route.png" alg="MemPool_Group_GF12_Tuned_AutoDMP_Route">
</p> </p>
<a id="MemPool_Group_GF12_HierRTLMP"></a>
- **MemPool Group-GF12-68% Hier-RTLMP**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by Hier-RTLMP. - **MemPool Group-GF12-68% Hier-RTLMP**: The subsequent table and screenshots presents the post P\&R details of MemPool Group design on GF12 enablement when the macro placement is generated by Hier-RTLMP.
<table> <table>
...@@ -7602,6 +7681,8 @@ We have run Hier-RTLMP macro placer, as described in the [arXiv paper](https://a ...@@ -7602,6 +7681,8 @@ We have run Hier-RTLMP macro placer, as described in the [arXiv paper](https://a
<img height="300" src="./images/Ariane_NG45_HierRTLMP_Route.png" alg="Ariane133_Route_HierRTLMP"> <img height="300" src="./images/Ariane_NG45_HierRTLMP_Route.png" alg="Ariane133_Route_HierRTLMP">
</p> </p>
- **Ariane133-GF12-68%**: [Link](#Ariane133_GF12_HierRTLMP) to the HierRTLMP macro placement details of Ariane on GF12 enablement.
- **BlackParrot (Quad-Core)-NG45-68%-1.3ns**: Following table and screenshots show the macro placement result of BlackParrot (Quad-Core) on NG45, generated using Hier-RTLMP. - **BlackParrot (Quad-Core)-NG45-68%-1.3ns**: Following table and screenshots show the macro placement result of BlackParrot (Quad-Core) on NG45, generated using Hier-RTLMP.
<table> <table>
...@@ -7679,6 +7760,8 @@ We have run Hier-RTLMP macro placer, as described in the [arXiv paper](https://a ...@@ -7679,6 +7760,8 @@ We have run Hier-RTLMP macro placer, as described in the [arXiv paper](https://a
<img height="300" src="./images/BP_Quad_NG45_HierRTLMP_Route.png" alg="BP_Quad_Route_HierRTLMP"> <img height="300" src="./images/BP_Quad_NG45_HierRTLMP_Route.png" alg="BP_Quad_Route_HierRTLMP">
</p> </p>
- **BlackParrot (Quad-Core)-GF12-68%**: [Link](#BlackParrot_GF12_HierRTLMP) to the HierRTLMP macro placement details of BlackParrot (Quad-Core) on GF12 enablement.
- **MemPool Group-NG45-68%-4ns**: Following table and screenshots show the macro placement result of MemPool Group on NG45, generated using Hier-RTLMP. - **MemPool Group-NG45-68%-4ns**: Following table and screenshots show the macro placement result of MemPool Group on NG45, generated using Hier-RTLMP.
<table> <table>
...@@ -7756,6 +7839,7 @@ We have run Hier-RTLMP macro placer, as described in the [arXiv paper](https://a ...@@ -7756,6 +7839,7 @@ We have run Hier-RTLMP macro placer, as described in the [arXiv paper](https://a
<img height="300" src="./images/MemPool_Group_NG45_HierRTLMP_Route.png" alg="MemPool_Group_Route_HierRTLMP"> <img height="300" src="./images/MemPool_Group_NG45_HierRTLMP_Route.png" alg="MemPool_Group_Route_HierRTLMP">
</p> </p>
- **MemPool Group-GF12-68%**: [Link](#MemPool_Group_GF12_HierRTLMP) to the HierRTLMP macro placement details of MemPool Group on GF12 enablement.
## **Pinned (to bottom) question list:** ## **Pinned (to bottom) question list:**
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