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Unverified Commit 8583f7c1 by Sayak Kundu Committed by GitHub
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Merge pull request #5 from TILOS-AI-Institute/flow_scripts 

Flow scripts
parents ad4a5646 5f8314c1
Showing with 809 additions and 272 deletions
.gitignore
Flows/*/*/run/*/
\ No newline at end of file
Flows/*/*/run/*/
Flows/job
Enablements/ASAP7/lef/sram_asap7_16x256_1rw.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO sram_asap7_16x256_1rw
FOREIGN sram_asap7_16x256_1rw 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 8.360 BY 16.800 ;
CLASS BLOCK ;
PIN rd_out[0]
......
Enablements/ASAP7/lef/sram_asap7_32x256_1rw.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO sram_asap7_32x256_1rw
FOREIGN sram_asap7_32x256_1rw 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 16.720 BY 16.800 ;
CLASS BLOCK ;
PIN rd_out[0]
......
Enablements/ASAP7/lef/sram_asap7_64x256_1rw.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO sram_asap7_64x256_1rw
FOREIGN sram_asap7_64x256_1rw 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 16.720 BY 33.600 ;
CLASS BLOCK ;
PIN rd_out[0]
......
Enablements/ASAP7/lef/sram_asap7_64x64_1rw.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO sram_asap7_64x64_1rw
FOREIGN sram_asap7_64x64_1rw 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 8.360 BY 16.800 ;
CLASS BLOCK ;
PIN rd_out[0]
......
Enablements/NanGate45/lef/fakeram45_256x16.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_256x16
FOREIGN fakeram45_256x16 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 57.570 BY 133.000 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/NanGate45/lef/fakeram45_256x32.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_256x32
FOREIGN fakeram45_256x32 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 60.610 BY 169.400 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/NanGate45/lef/fakeram45_256x64.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_256x64
FOREIGN fakeram45_256x64 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 109.060 BY 166.600 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/NanGate45/lef/fakeram45_64x256.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_64x256
FOREIGN fakeram45_64x256 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 108.870 BY 175.000 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/NanGate45/lef/fakeram45_64x64.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram45_64x64
FOREIGN fakeram45_64x64 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 56.050 BY 102.200 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/SKY130HD/lef/fakeram130_256x16.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram130_256x16
FOREIGN fakeram130_256x16 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 285.660 BY 187.680 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/SKY130HD/lef/fakeram130_256x32.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram130_256x32
FOREIGN fakeram130_256x32 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 293.940 BY 349.520 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/SKY130HD/lef/fakeram130_256x512.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram130_256x512
FOREIGN fakeram130_256x512 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 834.440 BY 1052.640 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/SKY130HD/lef/fakeram130_256x64.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram130_256x64
FOREIGN fakeram130_256x64 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 1010.160 BY 160.480 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Enablements/SKY130HD/lef/fakeram130_64x64.lef
......@@ -2,7 +2,7 @@ VERSION 5.7 ;
BUSBITCHARS "[]" ;
MACRO fakeram130_64x64
FOREIGN fakeram130_64x64 0 0 ;
SYMMETRY X Y R90 ;
SYMMETRY X Y ;
SIZE 189.980 BY 232.560 ;
CLASS BLOCK ;
PIN w_mask_in[0]
......
Flows/ASAP7/ariane133/def/ariane133_fp.def
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Flows/ASAP7/ariane133/def/ariane133_fp_rows.def deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/ariane133/scripts/cadence/design_setup.tcl
......@@ -3,6 +3,7 @@
set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../rtl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/ariane133_fp_placed_macros.def
......@@ -18,5 +19,6 @@ set GEN_EFF medium
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "asap7sc7p5t"
set HALO_WIDTH 2
set TOP_ROUTING_LAYER 7
Flows/ASAP7/ariane133/scripts/cadence/lib_setup.tcl
......@@ -26,3 +26,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/ariane133/scripts/cadence/run.sh 100644 → 100755
File mode changed from 100644 to 100755
Flows/ASAP7/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
......@@ -12,8 +12,6 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set rptDir summaryReport/
set encDir enc/
......@@ -41,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -58,12 +55,12 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
setFPlanMode -snapBlockGrid LayerTrack
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
......@@ -73,7 +70,7 @@ saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/ASAP7/ariane136/def/ariane136_fp_rows.def deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/ariane136/scripts/cadence/design_setup.tcl
......@@ -3,6 +3,7 @@
set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../rtl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/ariane136_fp_placed_macros.def
......@@ -18,5 +19,6 @@ set GEN_EFF medium
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "asap7sc7p5t"
set HALO_WIDTH 1
set TOP_ROUTING_LAYER 7
Flows/ASAP7/ariane136/scripts/cadence/lib_setup.tcl
......@@ -26,3 +26,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/ariane136/scripts/cadence/run.sh 100644 → 100755
File mode changed from 100644 to 100755
Flows/ASAP7/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......
Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
......@@ -12,8 +12,6 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set site "asap7sc7p5t"
set rptDir summaryReport/
set encDir enc/
......@@ -41,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -58,12 +55,12 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
setFPlanMode -snapBlockGrid LayerTrack
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
......@@ -73,7 +70,7 @@ saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/ASAP7/mempool_tile/constraints/mempool_tile_wrap.sdc
......@@ -1299,4 +1299,4 @@ set_clock_uncertainty -setup 0.08 [get_clocks clk_i]
set_clock_uncertainty -hold 0.08 [get_clocks clk_i]
set_clock_latency 0.07 [get_clocks vclk_i]
## List of unsupported SDC commands ##
set_critical_range 0.100 [current_design]
#set_critical_range 0.100 [current_design]
Flows/ASAP7/mempool_tile/def/mempool_tile_wrap_fp.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/mempool_tile/def/mempool_tile_wrap_fp_placed_macros.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/mempool_tile/def/mempool_tile_wrap_mp_fp.def deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/mempool_tile/run/README.md 0 → 100644
Here you run can run flow scripts
Flows/ASAP7/mempool_tile/scripts/cadence/design_setup.tcl
......@@ -6,7 +6,11 @@ set rtldir ../../../../../Testcases/mempool/rtl
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/mempool_tile_wrap_fp.def
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......@@ -15,3 +19,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "asap7sc7p5t"
set HALO_WIDTH 1
set TOP_ROUTING_LAYER 7
Flows/ASAP7/mempool_tile/scripts/cadence/lib_setup.tcl
......@@ -27,3 +27,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/mempool_tile/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/ASAP7/mempool_tile/scripts/cadence/run.sh 100644 → 100755
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/ASAP7/mempool_tile/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -7,12 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
#set netlist "../../netlist/$DESIGN.v"
#set sdc "../../constraints/$DESIGN.sdc"
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "asap7sc7p5t"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -41,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -58,52 +55,26 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 1 1 1 1
setFPlanMode -snapBlockGrid LayerTrack
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {M2 M3 M7 M8 M9 Pad} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 7
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
#setPlaceMode -placeIoPins true
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
}
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 7
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setPlaceMode -placeIoPins true
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
defOut -netlist -floorplan ${DESIGN}_placed.def
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
......@@ -119,12 +90,10 @@ set_clock_propagation propagated
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -routeTopRoutingLayer 7
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
......@@ -133,7 +102,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -dbCheckRule true
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
......@@ -141,25 +109,11 @@ setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
setDelayCalMode -reset
setDelayCalMode -SIAware true
setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
setAnalysisMode -analysisType onChipVariation -cppr both
# routeOpt
#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
source fix_route_drc.tcl
#extractRC
deselectAll
selectNet -clock
reportSelect > summaryReport/clock_net_length.post_route
deselectAll
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc
......@@ -7,7 +7,7 @@
# with this distribution for more information.
# ===================================================================
set_max_area 0
#set_max_area 0
set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
......
Flows/ASAP7/nvdla/def/NV_NVDLA_partition_c_fp.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/nvdla/def/NV_NVDLA_partition_c_fp_placed_macros.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/nvdla/run/README.md 0 → 100644
You can run the flow scripts here
Flows/ASAP7/nvdla/scripts/cadence/design_setup.tcl
......@@ -3,11 +3,14 @@
set DESIGN NV_NVDLA_partition_c
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../../../../Testcases/nvdla/rtl
# def file with die size and placed IO pins
set floorplan_def ../../def/${DESIGN}_fp.def
set rtl_path ../../../../../Testcases/nvdla/rtl/
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
......@@ -17,3 +20,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "asap7sc7p5t"
set HALO_WIDTH 2
set TOP_ROUTING_LAYER 7
Flows/ASAP7/nvdla/scripts/cadence/lib_setup.tcl
......@@ -26,3 +26,4 @@ set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 7
Flows/ASAP7/nvdla/scripts/cadence/run.sh 100644 → 100755
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/ASAP7/nvdla/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
read_hdl -f rtl_list.tcl
#source rtl_list.tcl
#
#foreach rtl_file $rtl_all {
# read_hdl -sv $rtl_file
#}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
......@@ -7,10 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "asap7sc7p5t"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -56,28 +55,22 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 1 1 1 1
setFPlanMode -snapBlockGrid LayerTrack
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
saveDesign ${encDir}/${DESIGN}_floorplan.enc
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
}
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {M2 M3 M7 M8 M9 Pad} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 7
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/NanGate45/ariane133/def/ariane133_fp.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/ariane133/rtl/ariane.v
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/ariane133/scripts/cadence/design_setup.tcl
......@@ -3,6 +3,7 @@
set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../../../../Testcases/ariane133/rtl
#
# DEF file for floorplan initialization
......@@ -20,3 +21,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/ariane133/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 45
Flows/NanGate45/ariane133/scripts/cadence/run.sh 100644 → 100755
File mode changed from 100644 to 100755
Flows/NanGate45/ariane133/scripts/cadence/run_genus_hybrid.tcl
......@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......@@ -90,6 +91,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
......@@ -12,8 +12,6 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set rptDir summaryReport/
set encDir enc/
......@@ -41,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -63,7 +60,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro 5 5 5 5
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
......@@ -72,7 +69,7 @@ saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 10
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/NanGate45/ariane136/scripts/cadence/design_setup.tcl
......@@ -3,6 +3,7 @@
set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../../../../Testcases/ariane136/rtl
#
# DEF file for floorplan initialization
......@@ -20,3 +21,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/ariane136/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 45
Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl
......@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
......@@ -64,7 +64,8 @@ elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......@@ -90,6 +91,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
......@@ -12,8 +12,6 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set rptDir summaryReport/
set encDir enc/
......@@ -41,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -63,7 +60,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro 5 5 5 5
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
......@@ -72,7 +69,7 @@ saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 10
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/NanGate45/mempool_group/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set lefs "
#set qrc_max "SigCmax/qrcTechFile"
#set qrc_min "SigCmin/qrcTechFile"
setDesignMode -process 45
Flows/NanGate45/mempool_group/scripts/cadence/run_invs.tcl
......@@ -41,7 +41,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/NanGate45/mempool_tile/constraints/mempool_tile_wrap.sdc
......@@ -20,7 +20,7 @@ set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
# Create virtual clock.
create_clock -name "vclk_i" -period $clock_cycle
set_clock_uncertainty $clk_uncertainty [get_clocks vclk_i]
set_clock_uncertainty $uncertainty [get_clocks vclk_i]
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
......@@ -34,26 +34,26 @@ set_max_fanout $maxFanout [current_design]
set_false_path -from tile_id_i
# TCDM Master
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_master_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*req_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_master_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*resp_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_master_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
# TCDM Slave
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_slave_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*req_*"]
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*req_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ tcdm_slave_*resp_*"]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
# Refill port
set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "hierarchical_name =~ refill_*"]
set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ refill_*"]
#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs] "name =~ refill_*"]
#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
# Reset
set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
# Critical range
# Depending on the synthesis tool used, this can be helpful.
set_critical_range 0.100 [current_design]
#set_critical_range 0.100 [current_design]
Flows/NanGate45/mempool_tile/def/mempool_tile_wrap_fp.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/mempool_tile/def/mempool_tile_wrap_fp_placed_macros.def
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/mempool_tile/run/README.md 0 → 100644
Here you can run the flow scripts
Flows/NanGate45/mempool_tile/scripts/cadence/design_setup.tcl
......@@ -6,7 +6,11 @@ set rtldir ../../../../../Testcases/mempool/rtl
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/mempool_tile_wrap_fp.def
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
......@@ -15,3 +19,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/mempool_tile/scripts/cadence/lib_setup.tcl
......@@ -4,6 +4,7 @@
set libdir "../../../../../Enablements/NanGate45/lib"
set lefdir "../../../../../Enablements/NanGate45/lef"
set qrcdir "../../../../../Enablements/NanGate45/qrc"
set_db init_lib_search_path { \
${libdir} \
......@@ -33,6 +34,6 @@ set lefs "
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
#set qrc_max "SigCmax/qrcTechFile"
#set qrc_min "SigCmin/qrcTechFile"
set qrc_max "${qrcdir}/NG45.tch"
set qrc_min "${qrcdir}/NG45.tch"
setDesignMode -process 45
Flows/NanGate45/mempool_tile/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/NanGate45/mempool_tile/scripts/cadence/run deleted 100644 → 0
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload innovus
module load innovus/21.1
mkdir -p log
innovus -64 -init run_invs.tcl -log log/run.log
Flows/NanGate45/mempool_tile/scripts/cadence/run.sh 100644 → 100755
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
......@@ -53,18 +53,19 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
#read_sdc $sdc
source $sdc
}
init_design
......@@ -90,6 +91,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
......
Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -7,12 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "../../netlist/$DESIGN.v"
set sdc "../../constraints/$DESIGN.sdc"
#set netlist "./syn_handoff/$DESIGN.v"
#set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -41,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -58,56 +55,25 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
#setPlaceMode -placeIoPins true
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name Layer_2 -edge 1
createPinBlkg -name Layer_3 -edge 2
createPinBlkg -name Layer_4 -edge 3
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setPlaceMode -placeIoPins true
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
defOut -netlist -floorplan ${DESIGN}_placed.def
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
......@@ -123,12 +89,10 @@ set_clock_propagation propagated
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
......@@ -137,7 +101,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -dbCheckRule true
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
......@@ -145,24 +108,11 @@ setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
setDelayCalMode -reset
setDelayCalMode -SIAware true
setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
setAnalysisMode -analysisType onChipVariation -cppr both
# routeOpt
#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
#extractRC
deselectAll
selectNet -clock
reportSelect > summaryReport/clock_net_length.post_route
deselectAll
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/NanGate45/nvdla/constraints/NV_NVDLA_partition_c.sdc
......@@ -7,7 +7,7 @@
# with this distribution for more information.
# ===================================================================
set_max_area 0
#set_max_area 0
set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
......
Flows/NanGate45/nvdla/def/NV_NVDLA_partition_c_fp_placed_macros.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/NanGate45/nvdla/run/README.md 0 → 100644
Here you can run the flow scripts
Flows/NanGate45/nvdla/scripts/cadence/design_setup.tcl
......@@ -2,12 +2,15 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN NV_NVDLA_partition_c
set rtldir ../../../../../Testcases/nvdla/rtl
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/${DESIGN}_fp.def
set rtl_path ../../../../../Testcases/nvdla/rtl/
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
......@@ -17,3 +20,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/nvdla/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set qrc_min "${qrcdir}/NG45.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 45
Flows/NanGate45/nvdla/scripts/cadence/rtl_list.tcl
......@@ -5,6 +5,7 @@
+libext+.gv
+define+DISABLE_TESTPOINTS
+define+NV_SYNTHESIS
+define+SYNTHESIS
//+define+RAM_INTERFACE
NV_nvdla.v
......@@ -371,7 +372,7 @@ nv_ram_rwsthp_80x15.v
nv_ram_rwsthp_80x17.v
nv_ram_rwsthp_80x72.v
nv_ram_rwsthp_80x9.v
fakeram_256x64_dp.v
fakeram45_256x64_dp.v
-v NV_NVDLA_XXIF_libs.v
Flows/NanGate45/nvdla/scripts/cadence/run.sh 100644 → 100755
......@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus
module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/NanGate45/nvdla/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
set_db init_hdl_search_path $rtldir
read_hdl -f rtl_list.tcl
#source rtl_list.tcl
#
#foreach rtl_file $rtl_all {
# read_hdl -language sv $rtl_file
#}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
#read_sdc $sdc
source $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
......@@ -7,10 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set handoff_dir "./syn_handoff"
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/
set encDir enc/
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......@@ -56,26 +55,21 @@ generateVias
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 10
setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
......
Flows/README.md
......@@ -14,4 +14,91 @@ The setup to run SP&R on the available test cases for the given enablements are
- [Ariane136](./SKY130HD/ariane136/)
- [Ariane133](./SKY130HD/ariane133/)
- [MemPool tile](./SKY130HD/mempool_tile/)
- [NVDLA](./SKY130HD/nvdla/)
\ No newline at end of file
- [NVDLA](./SKY130HD/nvdla/)
Inside each directory are the following sub-directories that contain all of the files required to run the full SP&R flow.
- *constraints* directory contians the SDC constraint file for current design and enablement.
- *def* directory contains the floorplan DEF file that is used in the SP&R flow. We provide two DEF files one with just the core.
area and pin placements that is used for the logical synthesis flow [Flow-1](./figures/flow-1.PNG) and another DEF file that also inlcudes macro placements that
is used in the physical synthesis iSpatial flow [Flow-2](./figures/flow-2.PNG).
- *netlist* directory contains the synthesized netlist from [Flow-1](./figures/flow-1.PNG).
- *scripts* directory contains the setup and scripts to run the full SP&R flow using both commercial and open-source tools.
- *run* directory to peform the SP&R runs using the runscripts available in the *scripts* direcotry.
The runscripts for all the flows are available in the *./\<enablement\>/\<testcase\>/scripts/* directory. Inside *script* directory are the following sub-directories.
- *cadence* directory contains all the runscripts related to [Flow-1](./figures/flow-1.PNG), [Flow-2](./figures/flow-2.PNG). We will also add [Flow-4](./figures/flow-4.PNG) scripts here.
- *OpenROAD* directory contains the *<testcase>.tar.gz* file, which includes all the required files to run [Flow-3](./figures/flow-3.PNG) using OpenROAD-flow-scripts ([ORFS](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/)).
All the flows uses the *RTL* from the [*Testcases*](../Testcases/) directory and the *.lef*, *.lib* and *qrc* files from the [*Enablements*](../Enablements/) directory. The required SRAM models for each testcase are generated and also available under the [*Enablements*](../Enablements/) directory. The detailed steps for different tools are as follows.
- [**Cadence tools**](#using-cadence-genus-and-innovus)
- [**OpenROAD tools**](#using-openroad-flow-scripts)
## **Using Cadence Genus and Innovus:**
All the required runscripts are available in the *./\<enablement\>/\<testcase\>/scripts/cadence/* directory. The steps to modify *run.sh* to launch SP&R runs for Flow-1 and Flow-2 are as follows.
- To launch Flow-1 set the **PHY_SYNTH** environment variable to *0* in the *run.sh* file.
``` export PHY_SYNTH=0 ```
- To laucnh Flow-2 set the **PHY_SYNTH** environment variable to *1* in the *run.sh* file.
``` export PHY_SYNTH=1 ```
- To start the SP&R run use the following command.
``` ./run.sh ```
**Synthesis:** The *run_genus_hybrid.tcl* is used to run the logical synthesis using Genus and physical synthesis using Genus iSpatial. It utilizes the **PHY_SYNTH** environment variable to determine the flow. Minor details of each synthesis flow are as follows.
- Logical synthesis using Genus (Flow-1): We use the *elaborate*, *syn_generic*, *syn_map* and *syn_opt* commands to generate the synthesized netlist. This synthesized netlist is copied into the *netlist* directory.
- Physical synthesis using Genus iSpatial (Flow-2): We use the *elaborate*, *syn_generic -physical*, *syn_map -physical* and *syn_opt -iSpatial* commands to generate the sunthesized netlist. In this step we provide the floorplan def with placed macros and pins as an additional input compared to Flow-1. This def file is generate in Flow-1.
- Physical synthesis using Genus iSpatial for Circuit Training (Flow-4): This is same as Flow-2 synthesis flow. The only difference is that the input def file does not include macro placement information.
The command to launch only the synthesis run is as follows.
```
# export PHY_SYNTH=0 #For Flow-1 uncomment this line
# export PHY_SYNTH=1 #For Flow-2 uncomment this line
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
```
<!-- We use the constraint file available in the *constraint* directory for the synthesis run. We set the target clock period to a reasonable value that is not too easy or hard for the tool to achieve. -->
**P\&R:** The *run_invs.tcl* is used to run the place and route using Cadence Innovus. The netlist and constraint generated during synthesis flow are used in this step. It also utilizes the **PHY_SYNTH** environment variable to choose which flow to run. Minor details of each P&R flow are as follows.
- Flow-1
- We use aspect ratio 1 and a utilization value in the range of 40% to 60%. All the pins are placed on the left side of the floorplan and the floorplan def file *\<design\>_fp.def* is created and copied into the def directory for place and route. The following command is used to place the pins.
```
### pin_list contains the name of all the top level pins. Here Y1 < Y2. LAYER1 and LAYER2 are two horizontal layer above M1 or metal1 or met1 ###
editPin -pin $pin_list -edge 0 -start {0 Y1} -end {0 Y2} -fixedPin -layer {LAYER1 LAYER2} -spreadDirection clockwise -pattern fill_optimised
```
- We use default HALO width based on the enablement for all the macros using the following command.
```
### HALO_WIDTH is 2um for ASAP7 and 5um for NanGate45 and SKY130HD FakeStack enablements ###
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
```
- The *place_design -concurrent_macros* command is used to place the macros and the def file *\<design\>_fp_placed_macros.def* is created and copied into the def directory for synthesis using Flow-2.
- It uses *place_opt_design*, *ccopt_design* and *routeDesign* commands for placement, CTS and routing of the design.
- Flow-2
- The *run_invs.tcl* script utilizes the *.def* file generated by the Genus iSpatial flow as a starting point.
- Similar to Flow-1 it uses *place_opt_design*, *ccopt_design* and *routeDesign* commands for placement, CTS and routing of the design.
The command to launch the P&R run is as follows.
```
### Make sure you have run the synthesis synthesis step. run_invs.tcl uses the output files generated synthesis ###
# export PHY_SYNTH=0 #For Flow-1 uncomment this line
# export PHY_SYNTH=1 #For Flow-2 uncomment this line
innovus -64 -init run_invs.tcl -log log/run.log
```
The screenshot of the Ariane 136 testcase using the Cadence Flow-1 on NanGate45 enablement is given below.
<img src="./NanGate45/ariane136/screenshots/Ariane136_Innovus_Genus.png" alt="ariane136_cadence" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
## **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). Use the following steps to run SP&R using OpenROAD tools:
1. Copy *./\<enablement\>/\<testcase\>/scripts/OpenROAD/\<design\>.tar.gz* file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/\<enablement\>* area.
2. Use the command *tar -xvf \<design\>.tar.gz* to untar *\<design\>.tar.gz*. This will generate *\<design\>* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the make command
```
make DESIGN_CONFIG=./designs/<enablement>/<design>/config_hier.mk
```
4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
```
make DESIGN_CONFIG=./designs/<enablement>/<design>/config.mk
```
The screenshot of the Ariane 136 testcase using the ORFS (RTL-MP) on NanGate45 enablement is given below.
<img src="./NanGate45/ariane136/screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
\ No newline at end of file
Flows/SKY130HD/ariane133/rtl/ariane.v
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Flows/SKY130HD/ariane133/scripts/cadence/lib_setup.tcl
......@@ -33,3 +33,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/ariane133/scripts/cadence/run.sh
......@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 130
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/SKY130HD/ariane136/scripts/cadence/lib_setup.tcl
......@@ -33,3 +33,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/ariane136/scripts/cadence/run.sh 100644 → 100755
......@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 130
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/SKY130HD/mempool_tile/constraints/mempool_tile_wrap.sdc
......@@ -56,4 +56,4 @@ set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
# Critical range
# Depending on the synthesis tool used, this can be helpful.
set_critical_range 0.100 [current_design]
#set_critical_range 0.100 [current_design]
Flows/SKY130HD/mempool_tile/scripts/cadence/lib_setup.tcl
......@@ -36,3 +36,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -39,7 +39,6 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 130
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
......
Flows/SKY130HD/nvdla/scripts/cadence/lib_setup.tcl
......@@ -33,3 +33,4 @@ set lefs "
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
setDesignMode -process 130
Flows/SKY130HD/nvdla/scripts/cadence/run.sh
......@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Testcases/ariane133/rtl/ariane.v
This source diff could not be displayed because it is too large. You can view the blob instead.
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