Merge branch 'flow_scripts' of github.com:TILOS-AI-Institute/MacroPlacement into flow_scripts

Flows/NanGate45/ariane133/README.md

@@ -2,28 +2,28 @@ We implement [Ariane design with 133 macros](../../../Testcases/ariane133) on th
 
 
 ## *Macro Placement Generated by Cadence Flow-1*
-The screenshot of the design using Cadence Flow-1 on Nangate45 enablement is shown below   
+The screenshot of the design using Cadence Flow-1 on Nangate45 enablement is shown below.   
 <img src="./screenshots/Ariane133_Innovus.png" alt="ariane133_cadence" width="400"/>  
   
 ## *Macro Placement Generated by ORFS*
-The screenshot of the design using ORFS on Nangate45 enablement is shown below  
+The screenshot of the design using ORFS on Nangate45 enablement is shown below.  
 <img src="./screenshots/Ariane133_ORFS.png" alt="ariane136_orfs" width="400"/>
 
 ## *Baseline Macro Placement Generated by Human*
-The screenshot of the design using Cadence tool for standard cell placement and routing on Nangate45 enablement is shown below   
+The screenshot of the design using the Cadence Innovus tool for standard-cell placement and routing on Nangate45 enablement is shown below.   
 <img src="./screenshots/manual_ariane133_Innovus.png" alt="ariane133_cadence" width="400"/>  
 The manual macro placement is provided in [manual_floorplan.def](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/Flows/NanGate45/ariane133/def/manual_floorplan.def).
 We generate the manual macro placement in two steps:  
-(1) we call the [gridding](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Gridding) scripts to generate grid cells (27 x 27 in our case); (2) we manually place macros on the center of grid cells.
+(1) we call the [gridding](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Gridding) scripts to generate grid cells (in this case, we end up with a 27 x 27 grid); (2) we manually place macros so that their centers lie on centers of grid cells, with no overlap between macros or overflow of macros beyond the layout canvas.
 
-The macro placement can be a competitive baseline for [Circuit Training](https://github.com/google-research/circuit_training).
-The metrics after different physical design stages are shown below. 
+Note that this human-constructed macro placement can be a competitive baseline for [Circuit Training](https://github.com/google-research/circuit_training).
+The metrics reported by the Innovus tool after different physical design stages are shown below. 
 Note that (1) we set the activity factor to 0.2 in our flow; (2) the standard cell area does not include physical cells; (3) In order to match [Nature paper](https://www.nature.com/articles/s41586-021-03544-w), we adjust the pin positions to occupy about 60% of the left boundary. 
 
 <table class="tg">
 <thead>
   <tr>
-    <th class="tg-0lax">Stage in Physcial Design</th>
+    <th class="tg-0lax">Stage in Physical Design</th>
     <th class="tg-0lax">Core Area (um^2)</th>
     <th class="tg-0lax">Standard Cell Area (um^2)</th>
     <th class="tg-0lax">Total Power (mW)</th>

Flows/util/extract_report.tcl

+proc extract_from_timing_rpt {timing_rpt} {
+    set wns ""
+    set tns ""
+    set hc ""
+    set vc ""
+    set flag "0"
+    # puts "File name $timing_rpt"
+    set fp [open $timing_rpt r]
+    zlib push gunzip $fp
+    while { [gets $fp line] >= 0 } {
+        # puts "Lins is : $line"
+        if { $flag == 0 } {
+            set words [split $line "|"]
+        } else {
+            set words [split $line]
+        }
+        if {[string map {" " "" } [lindex $words 1]] == "WNS(ns):"} {
+            set wns [string map {" " "" } [lindex $words 2]]
+        } elseif {[string map {" " "" } [lindex $words 1]] == "TNS(ns):"} {
+            set tns [string map {" " "" } [lindex $words 2]]
+            set flag 1
+        } elseif { [lindex $words 0] == "Routing" && [llength $words] == 7} {
+            set hc [lindex $words 2]
+            set vc [lindex $words 5]
+            break
+        }
+    }
+    close $fp
+    set ans [list $wns $tns $hc $vc]
+    return $ans
+}
+
+proc extract_from_power_rpt {power_rpt} {
+    set power ""
+    set fp [open $power_rpt r]
+    while { [gets $fp line] >= 0 } {
+        if { [lindex $line 0] == "Total" && [llength $line] == 3 } {
+            set power [lindex $line 2]
+            break
+        }
+    }
+    return $power
+}
+
+proc extract_cell_area {} {
+    set macro_area [expr  [join [dbget [dbget top.insts.cell.name *ram* -p2 ].area ] +]]
+    set std_cell_area [expr  [join [dbget [dbget top.insts.cell.name *ram* -v -p2 ].area ] +]]
+    return [list $macro_area $std_cell_area]
+}
+
+proc extract_wire_length {} {
+    set wire_length [expr [join [dbget top.nets.wires.length ] + ]]
+}
+
+proc extract_report {stage} {
+    if { $stage == "preCTS" } {
+       timeDesign -preCTS -prefix ${stage} 
+    } elseif { $stage == "postCTS" } {
+       timeDesign -postCTS -prefix ${stage} 
+    } elseif { $stage == "postRoute" } {
+        setAnalysisMode -analysisType onChipVariatio -cppr both
+        timeDesign -postRoute -prefix ${stage}
+    }  
+    set rpt1 [extract_from_timing_rpt timingReports/${stage}.summary.gz]
+    report_power > power_${stage}.rpt
+    set rpt2 [extract_from_power_rpt power_${stage}.rpt]
+    set rpt3 [extract_cell_area]
+    set rpt4 [extract_wire_length]
+    # stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c
+    set ans "$stage,[dbget top.fplan.coreBox_area],[lindex $rpt3 1],[lindex $rpt3 0],$rpt2,$rpt4,[lindex $rpt1 0],[lindex $rpt1 1],[lindex $rpt1 2],[lindex $rpt1 3]"
+    return $ans
+}