Updated nvdla rtl and SKY130HD readme

Signed-off-by: sakundu <sakundu@ucsd.edu>

Enablements/SKY130HD/README.md

 # SKY130HD FakeStack (SKY130HD library, bsg_fakeram memory generation, 9M FkaeStack)
 
-The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. Memory macro has blockage till metal four so five-metal stack is not enough to route our macro dominant testcases. In this enablement each of the five routing layers and four cut layers has different lef property (.e.g, minimum spacing, width, enclosuer etc.).
+The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases. In this enablement each of the five routing layers and four cut layers has different lef properties (.e.g, minimum spacing, width, enclosure, etc.).
 
-Consider the five metal stacks are Ma, Mb, Mc, Md and Me, and this stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to genearte the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as our one of the enablement. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x1Ma_x2Mb_x3Mc_x4Md_1Me, where xi is greater or equal to one.  
+Consider the five metal stacks are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as our one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x1Ma_x2Mb_x3Mc_x4Md_1Me, where xi is greater or equal to one.  
 
 We use the bsg_fakeram memory generator available in the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) GitHub repo to generate the required SRAMs. The [sky130hd.cfg](./util/sky130hd.cfg) is the configuration file used to generate all the required memories.
 

Testcases/nvdla/rtl/fakeram130_256x64_dp.v

+module fakeram_256x64_dp 
+(
+  QA, 
+  CLKA, 
+  CENA, 
+  AA, 
+  CLKB,
+  CENB, 
+  AB, 
+  DB, 
+  STOV, 
+  EMAA, 
+  EMASA, 
+  EMAB, 
+  RET1N
+);
+
+input CLKA;
+input CLKB;
+
+input CENA;
+input [7:0]  AA;
+output [63:0] QA;
+
+input CENB;
+input [7:0]  AB;
+input [63:0] DB;
+
+input STOV;
+input [2:0] EMAA; 
+input EMASA;
+input [2:0] EMAB;
+input RET1N;
+
+wire [63:0] QB;
+wire [63:0] QA1;
+
+fakeram130_256x64 rmod_a
+(
+   .rd_out(QA1),
+   .addr_in(AA),
+   .we_in(~CENA),
+   .wd_in(DB), //dummy
+   .w_mask_in(DB), //dummy
+   .clk(CLKA),
+   .ce_in(CENA)
+);
+
+fakeram130_256x64 rmod_b
+(
+   .rd_out(QB), //dummy
+   .addr_in(AB),
+   .we_in(CENB),
+   .wd_in(DB), 
+   .w_mask_in(DB),
+   .clk(CLKB),
+   .ce_in(CENB)
+);
+
+genvar k;
+generate
+    for (k = 0; k < 64; k=k+1) begin
+        assign QA[k] = (~CENB & QB[k]) | (CENB & QA1[k]);
+    end
+endgenerate
+
+endmodule
+

Testcases/nvdla/rtl/fakeram7_256x64_dp.v

+module fakeram_256x64_dp 
+(
+  QA, 
+  CLKA, 
+  CENA, 
+  AA, 
+  CLKB,
+  CENB, 
+  AB, 
+  DB, 
+  STOV, 
+  EMAA, 
+  EMASA, 
+  EMAB, 
+  RET1N
+);
+
+input CLKA;
+input CLKB;
+
+input CENA;
+input [7:0]  AA;
+output [63:0] QA;
+
+input CENB;
+input [7:0]  AB;
+input [63:0] DB;
+
+input STOV;
+input [2:0] EMAA; 
+input EMASA;
+input [2:0] EMAB;
+input RET1N;
+
+assign STOV = 1'b0;
+assign EMASA = 1'b0;	
+assign EMAA = 3'b010;	// Extra margin adjustment A: Default for 0.8V
+assign EMAB = 3'b010;	// Extra margin adjustment B: Default for 0.8V
+assign RET1N = 1'b1;	
+wire [63:0] QB;
+wire [63:0] QA1;
+
+sram_asap7_64x256_1rw rmod_a
+(
+   .rd_out(QA1),
+   .addr_in(AA),
+   .we_in(~CENA),
+   .wd_in(DB), //dummy
+   .clk(CLKA),
+   .ce_in(CENA)
+);
+
+sram_asap7_64x256_1rw rmod_b
+(
+   .rd_out(QB), //dummy
+   .addr_in(AB),
+   .we_in(CENB),
+   .wd_in(DB), 
+   .clk(CLKB),
+   .ce_in(CENB)
+);
+
+genvar k;
+generate
+    for (k = 0; k < 64; k=k+1) begin
+        assign QA[k] = (~CENB & QB[k]) | (CENB & QA1[k]);
+    end
+endgenerate
+
+endmodule
+