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Commit 62f9f70e by sakundu
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Updated run_invs and run.sh to include pdn flow and enable Flow-4 using CodeElement 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent 9136472f
Showing with 211 additions and 35 deletions
Enablements/ASAP7/util/pdn_config.tcl
...@@ -20,15 +20,15 @@ ...@@ -20,15 +20,15 @@
################################################################# #################################################################
set minCh 2 set minCh 2
set offset [expr 2.88 - [expr 0.081 + [dbget top.fplan.coreBox_llx ]] ] set offset [expr 1.44*2 - [expr 0.117 + [dbget top.fplan.coreBox_llx ]] ]
set layers "M1 M2 M3 M5 M6 M7" set layers "M1 M2 M3 M5 M6 M7"
set width "0 0.018 0.162 0.312 0.416 0.544" set width "0 0.018 0.234 0.312 0.416 0.544"
set pitch "0 0 2.88 2.016 12.8 7.2" set pitch "0 0 3.60 2.016 12.8 7.2"
set spacing "0 0 0.27 0.504 0.672 0.672" set spacing "0 0 0.342 0.504 0.672 0.672"
set ldir "0 0 1 1 0 1" set ldir "0 0 1 1 0 1"
set isMacro "0 0 0 1 0 0" set isMacro "0 0 0 1 0 0"
set isBM "1 1 1 0 0 0" set isBM "1 1 1 0 0 0"
set isAM "0 0 0 0 1 1" set isAM "0 0 0 0 1 1"
set isFP "1 1 0 0 0 0" set isFP "1 1 0 0 0 0"
set soffset "0 0 $offset 0.254 0.416 0.544" set soffset "0 0 $offset 0.254 0.416 0.544"
set addch "0 0 1 0 0 0" set addch "0 0 1 0 1 0"
\ No newline at end of file \ No newline at end of file
Flows/ASAP7/ariane133/def/ariane133_fp.def
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Flows/ASAP7/ariane133/def/ariane133_fp_placed_macros.def
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Flows/ASAP7/ariane133/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros place_design -concurrent_macros
refine_macro_place refine_macro_place
snapFPlan -pin #snapFPlan -pin
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/ASAP7/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -126,6 +133,15 @@ routeDesign ...@@ -126,6 +133,15 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Add V1 vias ###
setViaGenMode -reset
editPowerVia -top_layer M2 -bottom_layer M1 -orthogonal_only 0 -add_vias 1
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/ASAP7/ariane136/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros place_design -concurrent_macros
refine_macro_place refine_macro_place
snapFPlan -pin #snapFPlan -pin
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/ASAP7/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -99,6 +106,7 @@ saveDesign $encDir/${DESIGN}_cts.enc ...@@ -99,6 +106,7 @@ saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS] set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
# Routing # Routing
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
...@@ -125,6 +133,15 @@ routeDesign ...@@ -125,6 +133,15 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Add V1 vias ###
setViaGenMode -reset
editPowerVia -top_layer M2 -bottom_layer M1 -orthogonal_only 0 -add_vias 1
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/ASAP7/mempool_tile/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl
...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros place_design -concurrent_macros
refine_macro_place refine_macro_place
snapFPlan -pin #snapFPlan -pin
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/ASAP7/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -126,6 +133,15 @@ routeDesign ...@@ -126,6 +133,15 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Add V1 vias ###
setViaGenMode -reset
editPowerVia -top_layer M2 -bottom_layer M1 -orthogonal_only 0 -add_vias 1
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/ASAP7/nvdla/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -66,9 +66,16 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros place_design -concurrent_macros
refine_macro_place refine_macro_place
snapFPlan -pin #snapFPlan -pin
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/ASAP7/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -99,6 +106,7 @@ saveDesign $encDir/${DESIGN}_cts.enc ...@@ -99,6 +106,7 @@ saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS] set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
# Routing # Routing
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
...@@ -125,6 +133,15 @@ routeDesign ...@@ -125,6 +133,15 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Add V1 vias ###
setViaGenMode -reset
editPowerVia -top_layer M2 -bottom_layer M1 -orthogonal_only 0 -add_vias 1
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/NanGate45/ariane133/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
...@@ -55,7 +55,6 @@ generateVias ...@@ -55,7 +55,6 @@ generateVias
createBasicPathGroups -expanded createBasicPathGroups -expanded
## Generate the floorplan ## ## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl source ../../../../util/gen_pb.tcl
...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false ...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def defOut -netlist -floorplan -routing ${DESIGN}_route.def
......
Flows/NanGate45/ariane136/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
...@@ -55,7 +55,6 @@ generateVias ...@@ -55,7 +55,6 @@ generateVias
createBasicPathGroups -expanded createBasicPathGroups -expanded
## Generate the floorplan ## ## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl source ../../../../util/gen_pb.tcl
...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false ...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def defOut -netlist -floorplan -routing ${DESIGN}_route.def
......
Flows/NanGate45/mempool_group/scripts/cadence/run.sh
...@@ -9,3 +9,4 @@ module load innovus/21.1 ...@@ -9,3 +9,4 @@ module load innovus/21.1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
../../../../util/run_grp_main.sh
Flows/NanGate45/mempool_tile/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl
...@@ -55,7 +55,6 @@ generateVias ...@@ -55,7 +55,6 @@ generateVias
createBasicPathGroups -expanded createBasicPathGroups -expanded
## Generate the floorplan ## ## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl source ../../../../util/gen_pb.tcl
...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false ...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def defOut -netlist -floorplan -routing ${DESIGN}_route.def
......
Flows/NanGate45/nvdla/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=1 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
...@@ -55,7 +55,6 @@ generateVias ...@@ -55,7 +55,6 @@ generateVias
createBasicPathGroups -expanded createBasicPathGroups -expanded
## Generate the floorplan ## ## Generate the floorplan ##
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def defIn ${handoff_dir}/${DESIGN}.def
source ../../../../util/gen_pb.tcl source ../../../../util/gen_pb.tcl
...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -67,6 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/NanGate45/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false ...@@ -122,6 +128,11 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def defOut -netlist -floorplan -routing ${DESIGN}_route.def
......
Flows/SKY130HD/ariane133/scripts/cadence/run.sh
...@@ -13,4 +13,4 @@ export PHY_SYNTH=0 ...@@ -13,4 +13,4 @@ export PHY_SYNTH=0
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
../../../../util/run_grp_main.sh ../../../../util/run_CodeFlow.sh
Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
...@@ -65,8 +65,14 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -65,8 +65,14 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
place_design -concurrent_macros place_design -concurrent_macros
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/SKY130HD/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -123,6 +129,10 @@ routeDesign ...@@ -123,6 +129,10 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
...@@ -66,7 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -66,7 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/SKY130HD/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -123,6 +129,10 @@ routeDesign ...@@ -123,6 +129,10 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl
...@@ -66,7 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -66,7 +66,13 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/SKY130HD/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -123,6 +129,10 @@ routeDesign ...@@ -123,6 +129,10 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
...@@ -65,8 +65,14 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -65,8 +65,14 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
place_design -concurrent_macros place_design -concurrent_macros
refine_macro_place refine_macro_place
} }
### Write out the def files ###
source ../../../../util/write_required_def.tcl source ../../../../util/write_required_def.tcl
### Add power plan ###
source ../../../../../Enablements/SKY130HD/util/pdn_config.tcl
source ../../../../util/pdn_flow.tcl
saveDesign ${encDir}/${DESIGN}_floorplan.enc saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
...@@ -123,6 +129,10 @@ routeDesign ...@@ -123,6 +129,10 @@ routeDesign
#route_opt_design #route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
### Run DRC and LVS ###
verify_connectivity -error 0 -geom_connect -no_antenna
verify_drc -limit 0
set rpt_post_route [extract_report postRoute] set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
......
Flows/util/run_CodeFlow.sh
#!/bin/bash -i #!/bin/bash -i
if [[ -z $PHY_SYNTH ]];
then
echo "Not Running Clustering"
exit
fi
if [ $PHY_SYNTH -eq 0 ]; then
echo "Not Running Clustering"
exit
fi
echo "Running Clustering"
source /home/tool/anaconda3/etc/profile.d/conda.sh source /home/tool/anaconda3/etc/profile.d/conda.sh
conda activate py-tf conda activate py-tf
export PROJ_DIR=`pwd | grep -o '\S*/MacroPlacement'` export PROJ_DIR=`pwd | grep -o '\S*/MacroPlacement'`
......
Flows/util/write_required_def.tcl
## Make sure all the Macro has HALO ## ## Make sure all the Macro has HALO ##
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
deselectAll deselectAll
set top_module [dbget top.name] set top_module [dbget top.name]
...@@ -8,16 +7,6 @@ if {[dbget top.terms.pStatus -v -e fixed] == "" } { ...@@ -8,16 +7,6 @@ if {[dbget top.terms.pStatus -v -e fixed] == "" } {
} }
exec mkdir -p def exec mkdir -p def
select_obj [dbget top.terms ]
defOut -selected -floorplan ./def/${top_module}_fp.def
dbset [dbget top.insts.isHaloBlock 1 -p ].pStatus placed
selectInst [dbget [dbget top.insts.isHaloBlock 1 -p ].name]
defOut -selected -floorplan ./def/${top_module}_fp_macro_placed.def
dbset [dbget top.insts.isHaloBlock 1 -p ].pStatus fixed
deselectAll
### Remove Halo as OR do not support ### ### Remove Halo as OR do not support ###
deleteHaloFromBlock -allBlock deleteHaloFromBlock -allBlock
...@@ -26,5 +15,29 @@ defOut -netlist ./def/${top_module}.def ...@@ -26,5 +15,29 @@ defOut -netlist ./def/${top_module}.def
saveNetlist -removePowerGround ./def/${top_module}.v saveNetlist -removePowerGround ./def/${top_module}.v
saveNetlist -flat -removePowerGround ./def/${top_module}_flat.v saveNetlist -flat -removePowerGround ./def/${top_module}_flat.v
### Add halo again ###
### Add halo ###
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
#### Unplace the standard cells ###
dbset [dbget top.insts.cell.subClass core -p2 ].pStatus unplaced
#### Write out Macro Placed def ####
dbset [dbget top.insts.cell.subClass block -p2 ].pStatus placed
defOut -floorplan ./def/${top_module}_fp_placed_macros.def
#### Unplace the macros ###
dbset [dbget top.insts.cell.subClass block -p2 ].pStatus unplaced
### Write out Pin Placed def only ###
defOut -floorplan ./def/${top_module}_fp.def
### Read the Macro Def ###
defIn ./def/${top_module}_fp_placed_macros.def
### Fix macros ###
dbset [dbget top.insts.cell.subClass block -p2 ].pStatus fixed
### run global place during place opt ###
setPlaceMode -place_opt_run_global_place full
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