Merge pull request #32 from TILOS-AI-Institute/flow_scripts

Flow scripts

.gitignore

@@ -9,4 +9,5 @@ CodeElements/Plc_client/plc_client_os.py
 CodeElements/Plc_client/__pycache__/*
 CodeElements/Plc_client/proto_reader.py
 CodeElements/Plc_client/plc_client.py
-CodeElements/Plc_client/failed_proxy_plc/*
+CodeElements/Plc_client/failed_proxy_plc/*
\ No newline at end of file
+GF12/

Flows/NanGate45/bp_quad/scripts/cadence/mmmc_setup.tcl

@@ -4,8 +4,8 @@
 create_library_set -name WC_LIB -timing $libworst
 create_library_set -name BC_LIB -timing $libbest
  
-create_rc_corner -name Cmax
-create_rc_corner -name Cmin
+create_rc_corner -name Cmax -qx_tech_file $qrc_max
+create_rc_corner -name Cmin -qx_tech_file $qrc_min
 
 
 create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax

Flows/NanGate45/bp_quad/scripts/cadence/run_invs.tcl

@@ -2,15 +2,15 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 source lib_setup.tcl
 source design_setup.tcl
+set handoff_dir  "./syn_handoff"
+
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
 source mmmc_setup.tcl
 
 setMultiCpuUsage -localCpu 16
 set util 0.3
 
-set handoff_dir  "./syn_handoff"
-
-set netlist ${handoff_dir}/${DESIGN}.v
-set sdc ${handoff_dir}/${DESIGN}.sdc 
 
 set rptDir summaryReport/ 
 set encDir enc/
@@ -39,6 +39,8 @@ init_design -setup {WC_VIEW} -hold {BC_VIEW}
 set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
 
 set_interactive_constraint_modes {CON}
+setAnalysisMode -reset
+setAnalysisMode -analysisType onChipVariation -cppr both
 
 clearGlobalNets
 globalNetConnect VDD -type pgpin -pin VDD -inst * -override
@@ -66,6 +68,12 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
     refine_macro_place
 }
 
+### Write postSynth report ###
+echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
+source ../../../../util/extract_report.tcl
+set rpt_post_synth [extract_report postSynth]
+echo "$rpt_post_synth" >> ${DESIGN}_DETAILS.rpt
+
 ### Write out the def files ###
 source ../../../../util/write_required_def.tcl
 
@@ -83,8 +91,6 @@ setDesignMode -bottomRoutingLayer 2
 place_opt_design -out_dir $rptDir -prefix place
 saveDesign $encDir/${DESIGN}_placed.enc
 
-echo "Physical Design Stage, Core Area (um^2), Standard Cell Area (um^2), Macro Area (um^2), Total Power (mW), Wirelength(um), WS(ns), TNS(ns), Congestion(H), Congestion(V)" > ${DESIGN}_DETAILS.rpt
-source ../../../../util/extract_report.tcl
 set rpt_pre_cts [extract_report preCTS]
 echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
 
@@ -126,16 +132,21 @@ setNanoRouteMode -routeExpAdvancedTechnology true
 setNanoRouteMode -grouteExpWithTimingDriven false
 
 routeDesign
-#route_opt_design
 saveDesign ${encDir}/${DESIGN}_route.enc
+defOut -netlist -floorplan -routing ${DESIGN}_route.def
+
+set rpt_post_route [extract_report postRoute]
+echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
 
 ### Run DRC and LVS ###
 verify_connectivity -error 0 -geom_connect -no_antenna
 verify_drc -limit 0
 
-set rpt_post_route [extract_report postRoute]
+#route_opt_design
+optDesign -postRoute
+set rpt_post_route [extract_report postRouteOpt]
 echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
-defOut -netlist -floorplan -routing ${DESIGN}_route.def
+
 
 summaryReport -noHtml -outfile summaryReport/post_route.sum
 saveDesign ${encDir}/${DESIGN}.enc

Flows/util/place_pin.tcl

-set y [dbget top.fplan.box_sizey]
-set y1 [expr $y*0.175]
-set y2 [expr $y - $y1]
-set layers [dbget [dbget head.layers.direction Horizontal -p ].name]
-set layer1 [lindex $layers 1]
-set layer2 [lindex $layers 2]
-
-set pin_layer [list $layer1 $layer2]
-set pt1 [list 0 $y1]
-set pt2 [list 0 $y2]
-set pin_list [dbget top.terms.name]
-editPin -pin $pin_list -edge 0 -start $pt1 -end $pt2 -fixedPin -layer $pin_layer -spreadDirection clockwise -pattern fill_optimised
+proc place_pins { {side 0} {pin_list ""} {perc 0.6}} {
+  if { $pin_list == "" } {
+    set pin_list [dbget top.terms.name]
+  }
+
+  if { $perc > 1 || $perc < 0 } {
+    set perc 0.6
+  }
+
+  set height [dbget top.fplan.box_sizey]
+  set width [dbget top.fplan.box_sizex]
+
+  set x1 0
+  set x2 $width
+  set y1 0
+  set y2 $height
+
+  if { $side == 0 } {
+    set x2 $x1
+    set y1 [expr $height*(1- $perc)/2]
+    set y2 [expr $height - $y1]  
+  } elseif { $side == 1 } {
+    set y1 $y2
+    set x1 [expr $width*(1 - $perc)/2]
+    set x2 [expr $width - $x1]
+  } elseif { $side == 2 } {
+    set x1 $x2
+    set y2 [expr $height*(1- $perc)/2]
+    set y1 [expr $height - $y2]
+  } elseif { $side == 3 } {
+    set y2 $y1
+    set x2 [expr $width*(1 - $perc)/2]
+    set x1 [expr $width - $x2]
+  } else {
+    puts "Side is not correct"
+    return
+  }
+
+  if { $side == 0 || $side == 2 } {
+    set layers [dbget [dbget head.layers.direction Horizontal -p ].name]
+  } else {
+    set layers [dbget [dbget head.layers.direction Vertical -p ].name]
+  }
+
+  set layer1 [lindex $layers 1]
+  set layer2 [lindex $layers 2]
+  set pin_layer [list $layer1 $layer2]
+
+  set pt1 [list $x1 $y1]
+  set pt2 [list $x2 $y2]
+
+  editPin -pin $pin_list -edge $side -start $pt1 -end $pt2 -fixedPin -layer $pin_layer -spreadDirection clockwise -pattern fill_optimised  
+}
\ No newline at end of file