Added Bookshelf to Protobuf format translator. LEF / DEF to Protobuf format…

Added Bookshelf to Protobuf format translator. LEF / DEF to Protobuf format translator using OpenROAD. Scripts for shuffling experiment

Signed-off-by: sakundu <sakundu@ucsd.edu>

.gitignore

@@ -12,6 +12,7 @@ CodeElements/Plc_client/plc_client.py
 CodeElements/Plc_client/failed_proxy_plc/*
 __pycache__/
 __pycache__
+try.ipynb
 run
 run-*
 GF12/

Flows/NanGate45/ariane133/README.md

@@ -84,7 +84,7 @@ The following screenshot shows the placed and routed Ariane133-NG45 design gener
 <img height="400" src="./screenshots/CT_Routing.png">
 </p>
 
-The following table shows the different metrics, when [Flow-2](../../figures/flow-2.PNG) is used when initial macro placement is generated using CT.  
+The following table shows the different metrics, when [Flow-2](../../figures/flow-2.PNG) is used and the initial macro placement is generated using CT.  
 | Physical Design Stage | Core Area (um^2) | Standard Cell Area (um^2) | Macro Area (um^2) | Total Power (mW) | Wirelength (um) | WS (ns) | TNS (ns) | Congestion (H) | Congestion (V) |
 |-----------------------|------------------|---------------------------|-------------------|------------------|-----------------|---------|----------|----------------|----------------|
 | postSynth             | 1814274          | 244614                    | 1018356           | 761.754          | 4884882         | -0.764  | -533.519 |                |                |

Flows/NanGate45/bp_quad/scripts/cadence/rtl_list.tcl

 set rtl_all {
-  ./rtl/bsg_chip_block.sv2v.v
-  ./rtl/fakeram45_32x32_dp.v
+  ../../rtl/bsg_chip_block.sv2v.v
+  ../../rtl/fakeram45_32x32_dp.v
 }

Flows/util/gen_shuffle_macro_def.sh

+#!/bin/tcsh
+
+## Set to 1 to run refine_macro_place ##
+
+setenv SYN_HANDOFF $argv[1]
+setenv SEED $argv[2]
+set util_dir="/home/fetzfs_projects/MacroPlacement/flow_scripts_run/MacroPlacement/Flows/util/"
+
+if ($#argv != 3) then
+    echo "Required Physical synthesis handoff path and seed to run shuffle macro"
+endif
+
+module unload innovus
+module load innovus/21.1
+
+innovus -64 -overwrite -log log/macro_shuffle_innovus.log -files ${util_dir}/gen_shuffle_macro_def.tcl
+
+## Edit the design file to make sure flow2 reads the new macro placed def instead of the default one
+set def_file=`ls *_fp_shuffled_macros.def | head -n1`
+sed -i "s@\S*_fp_placed_macros.def@${def_file}@" design_setup.tcl
+

Flows/util/gen_shuffle_macro_def.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+set handoff_dir $::env(SYN_HANDOFF)
+
+set netlist ${handoff_dir}/${DESIGN}.v
+set sdc ${handoff_dir}/${DESIGN}.sdc 
+source mmmc_setup.tcl
+
+setMultiCpuUsage -localCpu 16
+set util 0.3
+
+# default settings
+set init_pwr_net VDD
+set init_gnd_net VSS
+
+# default settings
+set init_verilog "$netlist"
+set init_design_netlisttype "Verilog"
+set init_design_settop 1
+set init_top_cell "$DESIGN"
+set init_lef_file "$lefs"
+
+# MCMM setup
+init_design -setup {WC_VIEW} -hold {BC_VIEW}
+set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
+
+set_interactive_constraint_modes {CON}
+setAnalysisMode -reset
+setAnalysisMode -analysisType onChipVariation -cppr both
+
+clearGlobalNets
+globalNetConnect VDD -type pgpin -pin VDD -inst * -override
+globalNetConnect VSS -type pgpin -pin VSS -inst * -override
+globalNetConnect VDD -type tiehi -inst * -override
+globalNetConnect VSS -type tielo -inst * -override
+
+
+setOptMode -powerEffort low -leakageToDynamicRatio 0.5
+setGenerateViaMode -auto true
+generateVias
+
+# basic path groups
+createBasicPathGroups -expanded
+
+## Generate the floorplan ##
+defIn ${handoff_dir}/${DESIGN}.def
+
+#### Unplace the standard cells ###
+dbset [dbget top.insts.cell.subClass core -p2 ].pStatus unplaced
+
+source ../../../../util/shuffle_macro.tcl
+shuffle_macros $::env(SEED)
+
+defOut -floorplan ./${DESIGN}_fp_shuffled_macros.def
+
+exit