| **Test Cases** |Ariane<br> - [136 macro](./Testcases/ariane136/)<br> - [133 macro](./Testcases/ariane133/)<br>MemPool<br> - [tile](./Testcases/mempool_tile/)<br> - Group |Here we discuss the detailed steps to generate the netlist for each version. This netlist is used for SP&R runs. <br> The directory structure is as followed *./Testcases/design/<rtl\|sv2v>/*. Here<br> - *rtl* directory contains all the required rtl files to synthesize the test case.<br>- If the main repository contains only the SystemVerilog files, we add the converted Verilog file to the sv2v directory.|
| **Enablements** | - [NanGate45](./Enablements/NanGate45/)<br> - [ASAP7](./Enablements/ASAP7/) | We use open-source enablements NanGate45 and ASAP7 for our SP&R flow. The directory structure is *./Enablements/<NanGate45\|ASAP7>/<lib\|lef>/*. Here<br>- *lib* directory contains all the required liberty files.<br>- *lef* directory contains all the required lef files.<br> Also, we provide steps to generate the fakerams. |
| **Flows** | [NanGate45](./Flows/NanGate45/)<br>\-[Ariane 136](./Flows/NanGate45/ariane136/)<br>\-[Ariane 133](./Flows/NanGate45/ariane133/)<br>\-[MemPool tile](./Flows/NanGate45/mempool_tile/)<br>\- MemPool Group | Here we provide detailed information to run SP&R for each test case using the open-source tool OpenROAD and the commercial tools Cadence Genus (synthesis) and Innovus (P&R). <br> The directory structure is as follows *./FLows/Enablement/design/<constraint\|def\|netlist\|scripts\|run>/*. Here<br>- *constraint* directory contains the *.sdc* file. <br>- *def* directory contains the def file with pin placement and die area information.<br>- *scripts* directory contains required scripts to run SP&R using the Cadence and OpenROAD tools.<br>- *netlist* directory contains the synthesized netlist. We provide a synthesized netlist that can be used to run P&R.<br>- Also, we provide the *run* directory to run the scripts provided in the *scripts* directory. |
| **Flows** | [NanGate45](./Flows/NanGate45/)<br>\-[Ariane 136](./Flows/NanGate45/ariane136/)<br>\-[Ariane 133](./Flows/NanGate45/ariane133/)<br>\-[MemPool tile](./Flows/NanGate45/mempool_tile/)<br>\- MemPool group | Here we provide detailed information to run SP&R for each test case using the open-source tool OpenROAD and the commercial tools Cadence Genus (synthesis) and Innovus (P&R). <br> The directory structure is as follows *./FLows/Enablement/design/<constraint\|def\|netlist\|scripts\|run>/*. Here<br>- *constraint* directory contains the *.sdc* file. <br>- *def* directory contains the def file with pin placement and die area information.<br>- *scripts* directory contains required scripts to run SP&R using the Cadence and OpenROAD tools.<br>- *netlist* directory contains the synthesized netlist. We provide a synthesized netlist that can be used to run P&R.<br>- Also, we provide the *run* directory to run the scripts provided in the *scripts* directory. |
- We hope to show significant progress at the DAC-2022 Birds-of-a-Feather meeting (Open-Source EDA and Benchmarking Summit) on July 12, 2022, 7-10pm in Room 3000 of Moscone West in San Francisco.
