Update clock period in SDC to be be set by an env variable to enable sweeps

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>

Flows/ASAP7/ariane133/constraints/ariane.sdc

 #period set in nano-seconds - currently: 4ns = 250 MHz freq
-create_clock [get_ports clk_i]  -name core_clock  -period 4000
+set clk_period 4000
+if { [info exists ::env(CLK_PERIOD)] } {
+  set clk_period   $::env(CLK_PERIOD)
+}
+create_clock [get_ports clk_i]  -name core_clock  -period $clk_period 

Flows/ASAP7/ariane136/constraints/ariane.sdc

 #period set in nano-seconds - currently: 2ns = 500 MHz freq
-create_clock [get_ports clk_i]  -name core_clock  -period 900
+set clk_period 900
+if { [info exists ::env(CLK_PERIOD)] } {
+  set clk_period   $::env(CLK_PERIOD)
+}
+create_clock [get_ports clk_i]  -name core_clock  -period $clk_period 

Flows/ASAP7/mempool_tile/constraints/mempool_tile_wrap.sdc

@@ -12,9 +12,14 @@ set_units -capacitance 1000fF
 # Set the current design
 current_design mempool_tile_wrap
 
+set clk_period 6000
+if { [info exists ::env(CLK_PERIOD)] } {
+  set clk_period   $::env(CLK_PERIOD)
+}
+
 set_case_analysis 0 [get_ports scan_enable_i]
-create_clock -name "clk_i" -period 6000.0 -waveform {0.0 3000.0} [get_ports clk_i]
-create_clock -name "vclk_i" -period 6000.0 -waveform {0.0 3000.0} 
+create_clock -name "clk_i" -period $clk_period -waveform {0.0 [expr $clk_period / 2.0]} [get_ports clk_i]
+create_clock -name "vclk_i" -period $clk_period -waveform {0.0 [expr $clk_period / 2.0]} 
 set_false_path -from [list \
   [get_ports {tile_id_i[1]}]  \
   [get_ports {tile_id_i[0]}] ]

Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc

@@ -7,12 +7,17 @@
 # with this distribution for more information.
 # ===================================================================
 
+set clk_period 900
+if { [info exists ::env(CLK_PERIOD)] } {
+  set clk_period   $::env(CLK_PERIOD)
+}
+
 #set_max_area 0
 set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
 set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 set_ideal_network [get_ports test_mode]
-create_clock [get_ports nvdla_core_clk]  -period 900.0  -waveform {0 450.0}
+create_clock [get_ports nvdla_core_clk]  -period $clk_period  -waveform {0 [expr $clk_period / 2.0]}
 set_clock_transition -max -rise 50 [get_clocks nvdla_core_clk]
 set_clock_transition -max -fall 50 [get_clocks nvdla_core_clk]
 set_clock_transition -min -rise 50 [get_clocks nvdla_core_clk]