Updated run_invs.tcl

Signed-off-by: sakundu <sakundu@ucsd.edu>

Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl

@@ -63,8 +63,10 @@ defIn $floorplan_def
 #redirect mp_config.tcl {source gen_mp_config.tcl}
 #proto_design -constraints mp_config.tcl 
 addHaloToBlock -allMacro 1 1 1 1
+setFPlanMode -snapBlockGrid LayerTrack
 place_design -concurrent_macros
 refine_macro_place
+snapFPlan -pin
 saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 ## Creating Pin Blcokage for lower and upper pin layers ##
@@ -119,6 +121,7 @@ routeDesign
 saveDesign ${encDir}/${DESIGN}_route.enc
 defOut -netlist -floorplan -routing ${DESIGN}_route.def
 
+source fix_route_drc.tcl
 summaryReport -noHtml -outfile summaryReport/post_route.sum
 saveDesign ${encDir}/${DESIGN}.enc
 defOut -netlist -floorplan -routing ${DESIGN}.def

Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl

@@ -65,6 +65,7 @@ defIn $floorplan_def
 addHaloToBlock -allMacro 1 1 1 1
 place_design -concurrent_macros
 refine_macro_place
+snapFPlan -pin
 saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 ## Creating Pin Blcokage for lower and upper pin layers ##

Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl

@@ -65,8 +65,10 @@ defIn $floorplan_def
 #redirect mp_config.tcl {source gen_mp_config.tcl}
 #proto_design -constraints mp_config.tcl 
 addHaloToBlock -allMacro 1 1 1 1
+setFPlanMode -snapBlockGrid LayerTrack
 place_design -concurrent_macros
 refine_macro_place
+snapFPlan -pin
 saveDesign ${encDir}/${DESIGN}_floorplan.enc
 
 ## Creating Pin Blcokage for lower and upper pin layers ##
@@ -151,6 +153,7 @@ setAnalysisMode -analysisType onChipVariation -cppr both
 
 # routeOpt
 #optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
+source fix_route_drc.tcl
 
 #extractRC
 deselectAll