Commit 180d444c by ZhiangWang033

modified grouping readme

parent 83935698
......@@ -22,6 +22,13 @@ The following cartoon was recently provided by a Google engineer to explain the
## **How Groups Are Used**
Each group is recorded in the “.fix file” that is part of the input to the hMETIS hypergraph partitioner when the gate-level netlist is clustered into soft macros.
## **How Grouping Scripts Are used**
We provide [(an example)](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Grouping/test/test.py) about the usage of our grouping script.
Basically our grouping scripts take follows as inputs: (i) [(setup_file)](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/main/CodeElements/Grouping/test/setup.tcl)
including enablement information (lefs/libs), synthesized gate-level netlist (*.v), def file with placed IOs (*.def); (ii) n_rows and n_cols determined by the [(Gridding)](https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/CodeElements/Gridding) step; (iii) K_in and K_out parameters; (iv) global_net_threshold for ignoring global nets. If a net has more than global_net_threshold instances, we ignore such net when we search "transitive" fanins and fanouts. After
running grouping scripts, you will get two files *.fix and *.fix.old. The ".fix.old" file contains the IOs or macros in the corresponding group while *.fix file only contains standard cells in each group.
# Thanks
We thank Google engineers for Q&A in a shared document, as well as live discussions on May 19, 2022, that explained the grouping method used in Circuit Training. All errors of understanding and implementation are the authors'. We will rectify such errors as soon as possible after being made aware of them.
......
#######################################################################
### Author: Zhiang, May, 2022
### Uses OpenROAD API to convert the netlist to a hypergraph (in hemtis format)
### This file cannot be used directly. It will be called by
### generate_cluster.py
### All the parameters set here are meaningless.
### !!! Please don't touch this file !!!
########################################################################
read_verilog $netlist
link_design $top_design
read_sdc $sdc
read_def $def_file -floorplan_initialize
#Generate the hypergraph
partition_design -max_num_inst 2000000 -min_num_inst 40000 \
-max_num_macro 12 -min_num_macro 4 \
-net_threshold 20 -virtual_weight 50 \
-num_hop 0 -timing_weight 1000 \
-report_file ${top_design}.hgr
exit
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