Updated README

Signed-off-by: sakundu <sakundu@ucsd.edu>

README.md

 # **MacroPlacement**
-**MacroPlacement** is an open, transparent effort to provide a public, baseline implementation of [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) (Morpheus) deep RL-based placement method. We will provide (1) testcases in open enablements, along with multiple EDA tool flows; (2) implementations of missing or binarized elements of Circuit Training; (3) reproducible example macro placement solutions produced by our implementation; and (4) post-routing results obtained by full completion of the place-and-route flow using both proprietary and open-source tools.
+**MacroPlacement** is an open, transparent effort to provide a public, baseline implementation of [Google Brain's Circuit Training](https://github.com/google-research/circuit_training) (Morpheus) deep RL-based placement method. We will provide (1) testcases in open enablements, along with multiple EDA tool flows; (2) implementations of missing or binarized elements of Circuit Training; (3) reproducible example macro placement solutions produced by our implementation; and (4) post-routing results obtained by full completion of the synthesis-place-and-route flow using both proprietary and open-source tools.
   
 ## **Table of Contents**
   <!-- - [Reproducible Example Solutions](#reproducible-example-solutions) -->
@@ -14,19 +14,19 @@
 The list of available testcases
 - Ariane (RTL)
   - [RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
-  - [RTL files for Ariane designs with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connection of 136 macro version.
+  - [RTL files for Ariane design with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connections of the 136 macro version.
 - MemPool (RTL)
-  - [RTL files for Mempool tile design](./Testcases/mempool_tile/)
-  - RTL files for Mempool group design
+  - [RTL files for Mempool tile design](./Testcases/mempool/)
+  - [RTL files for Mempool group design](./Testcases/mempool/)
 - NVDLA (RTL)
   - [RTL files for NVDLA Partition *c*](./Testcases/nvdla/)
   
-In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps instantiate memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's SRAM count [here](./Testcases/ariane133/). 
+In the [Nature Paper](https://www.nature.com/articles/s41586-021-03544-w), the authors report results for an Ariane design with 133 memory (256x16, single ported SRAM) macros. We observe that synthesizing from the available Ariane RTL in the [lowRISC](https://github.com/lowRISC/ariane) GitHub repository using 256x16 memories results in an Ariane design that has 136 memory macros. We outline the steps to instantiate the memories for Ariane 136 [here](./Testcases/ariane136/) and we show how we convert the Ariane 136 design to an Ariane 133 design that matches Google's memory macros count [here](./Testcases/ariane133/). 
 
 
-All the testcases are available under the [Testcases](./Testcases/) directory. Details of the sub-directories of each testcases:  
-  - *rtl*: directory contains all the required rtl files to synthesize the testcase.
-  - *sv2v*: If the main repository contains multiple Verilog files or the SystemVerilog files, then we convert it to a single Verilog file. This is availabe in the *sv2v* sub-drectory.
+All the testcases are available in the [Testcases](./Testcases/) directory. Details of the sub-directories are  
+  - *rtl*: directory contains all the required rtl files to synthesize the design.
+  - *sv2v*: If the main repository contains multiple Verilog files or SystemVerilog files, then we convert it to a single synthesizable Verilog RTL. This is availabe in the *sv2v* sub-drectory.
 
 ## **Enablements**
 The list of available enablements
@@ -34,16 +34,16 @@ The list of available enablements
 - [ASAP7](./Enablements/ASAP7/)
 - [SKY130HD FakeStack](./Enablements/SKY130HD/)
   
-Open-source enablements NanGate45, ASAP7 and SKY130DH are utilized in our SP&R flow. All the enablements are available under [Enablements](./Enablements) directory. Details of the sub-directories of each enablements:
- - *lib* directory contains all the required liberty files.
+Open-source enablements NanGate45, ASAP7 and SKY130HD are utilized in our SP&R flow. All the enablements are available under the [Enablements](./Enablements) directory. Details of the sub-directories are:
+ - *lib* directory contains all the required liberty files for standard cells and hard macros.
  - *lef* directory contains all the required lef files.
  - *qrc* directory contains all the required qrc tech files.
   
-Also, we provide steps to generate the fakerams.
+We also provide the steps to generate the fakeram model for each of the enablements based on the required memory configurations.
 
 
 ## **Flows**
-We provide multiple flows for each of the testcases and enablements. They are logical synthesis-based SP&R flow using Cadence Genus and Innovus ([Flow-1](./Flows/figures/flow-1.PNG)), physical synthesis-based SP&R flow using Cadence Genus iSpatial and Innovus ([Flow-2](./Flows/figures/flow-2.PNG)), logical synthesis-based SP&R flow using Yosys and OpenROAD ([Flow-3](./Flows/figures/flow-3.PNG)), and input data for Physical synthesis based CircuitTraining using Genus iSpatial ([Flow-4](./Flows/figures/flow-4.PNG)).
+We provide multiple flows for each of the testcases and enablements. They are: (1) a logical synthesis-based SP&R flow using Cadence Genus and Innovus ([Flow-1](./Flows/figures/flow-1.PNG)), (2) a physical synthesis-based SP&R flow using Cadence Genus iSpatial and Innovus ([Flow-2](./Flows/figures/flow-2.PNG)), (3) a logical synthesis-based SP&R flow using Yosys and OpenROAD ([Flow-3](./Flows/figures/flow-3.PNG)), and (4) creation of input data for Physical synthesis-based CircuitTraining using Genus iSpatial ([Flow-4](./Flows/figures/flow-4.PNG)).
 
 The details of each flow are shown below:  
 - **Flow-1:**