tech_cells_generic.patch

diff --git b/hardware/deps/tech_cells_generic/Bender.yml a/hardware/deps/tech_cells_generic/Bender.yml
index 4efe945..386cf62 100644
--- b/hardware/deps/tech_cells_generic/Bender.yml
+++ a/hardware/deps/tech_cells_generic/Bender.yml
@@ -10,7 +10,7 @@ sources:
   - src/deprecated/cluster_clk_cells.sv
   - src/deprecated/pulp_clk_cells.sv
 
-  - target: all(rtl, not(synthesis))
+  - target: any(all(rtl, not(synthesis)), verilator)
     files:
       # level 0
       - src/rtl/tc_sram.sv
@@ -22,7 +22,7 @@ sources:
       - src/fpga/tc_clk_xilinx.sv
       - src/fpga/tc_sram_xilinx.sv
 
-  - target: all(not(all(fpga, xilinx)), not(synthesis))
+  - target: any(all(not(all(fpga, xilinx)), not(synthesis)), verilator)
     files:
       # Level 0
       - src/rtl/tc_clk.sv
diff --git a/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv b/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
index 53ad07f..4ddd4e1 100644
--- a/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
+++ b/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
@@ -94,6 +94,7 @@ module pulp_clock_xor2 (
 endmodule
 
 `ifndef SYNTHESIS
+`ifndef VERILATOR
 module pulp_clock_delay(
   input  logic in_i,
   output logic out_o
@@ -103,5 +104,6 @@ module pulp_clock_delay(
 
 endmodule
 `endif
+`endif
 
 
diff --git b/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv a/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv
index 53530e0..82fe1f7 100644
--- b/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv
+++ a/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv
@@ -124,9 +124,11 @@ module tc_sram #(
   // write memory array
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
+      `ifndef VERILATOR
       for (int unsigned i = 0; i < NumWords; i++) begin
         sram[i] <= init_val[i];
       end
+      `endif
       for (int i = 0; i < NumPorts; i++) begin
         r_addr_q[i] <= {AddrWidth{1'b0}};
         // initialize the read output register for each port
@@ -204,4 +206,69 @@ module tc_sram #(
 `endif
 `endif
 // pragma translate_on
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Memory loader for simulation
+ *
+ * Include this file in a memory primitive to load a memory array from
+ * simulation.
+ *
+ * Requirements:
+ * - A memory array named `sram`.
+ * - A parameter `DataWidth` giving the memory width (word size) in bit.
+ * - A parameter `NumWords` giving the memory depth in words.
+ */
+
+`ifndef SYNTHESIS
+  // Task for loading 'sram' with SystemVerilog system task $readmemh()
+  export "DPI-C" task simutil_memload;
+
+  task simutil_memload;
+    input string file;
+    $readmemh(file, sram);
+  endtask
+
+  // Function for setting a specific element in |sram|
+  // Returns 1 (true) for success, 0 (false) for errors.
+  export "DPI-C" function simutil_set_mem;
+
+  function int simutil_set_mem(input int index, input bit [255:0] val);
+
+    // Function will only work for memories <= 256 bits
+    if (DataWidth > 256) begin
+      return 0;
+    end
+
+    if (index >= NumWords) begin
+      return 0;
+    end
+
+    sram[index] = val[DataWidth-1:0];
+    return 1;
+  endfunction
+
+  // Function for getting a specific element in |sram|
+  export "DPI-C" function simutil_get_mem;
+
+  function int simutil_get_mem(input int index, output bit [255:0] val);
+
+    // Function will only work for memories <= 256 bits
+    if (DataWidth > 256) begin
+      return 0;
+    end
+
+    if (index >= NumWords) begin
+      return 0;
+    end
+
+    val = 0;
+    val[DataWidth-1:0] = sram[index];
+    return 1;
+  endfunction
+`endif
+
 endmodule