# GroupingThe _grouping_ step in Circuit Training requires as inputs:- the post-synthesis gate-level netlist (standard cells and hard macros)- placed IOs (ports, or terminals), typically at the borders of the chip canvas- the _grid_ of **n_rows** rows and **n_cols** columns of _gridcells_, which defines the gridded layout canvas## ThanksWe thank Google engineers for Q&A in a shared document, as well as live discussions on May 19, 2022, that explained the grouping method used in Circuit Training. All errors of understanding and implementation are the authors'.We will rectify such errors as soon as possible after being made aware of them.
