Commits · 46a1c816037e33a53a2ad147cd211d6f74acacec · lvzhengyang / abc · GitLab

20 Jul, 2016 1 commit
- Extension in the detection code. · 2ba46d52
  Alan Mishchenko committed 8 years ago
  
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18 Jun, 2016 1 commit
- New multi-output PLA reader and preprocessor (read_plamo) (updated dist-1 merge). · a3095693
  Alan Mishchenko committed 8 years ago
  
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17 Jun, 2016 1 commit
- New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge). · 3c3a770a
  Alan Mishchenko committed 8 years ago
  
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16 Jun, 2016 2 commits
- Change to BENCH reader to read DFF with four inputs. · e06c04a3
  Alan Mishchenko committed 8 years ago
  
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- New multi-output PLA reader and preprocessor (read_plamo). · ada21a65
  Alan Mishchenko committed 8 years ago
  
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13 Jun, 2016 1 commit
- Detecting properties of internal nodes. · a18da5c8
  Alan Mishchenko committed 8 years ago
  
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12 May, 2016 1 commit
- Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset). · ea7d10d4
  Alan Mishchenko committed 8 years ago
  
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02 May, 2016 1 commit
- Updating GIG parser. · 11f1a249
  Alan Mishchenko committed 8 years ago
  
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12 Apr, 2016 1 commit
- Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG (cubes -x; st). · 2d6a6f66
  Alan Mishchenko committed 8 years ago
  
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01 Feb, 2016 1 commit
- An add-on to write Verilog for circuits mapped into simple gates. · 02725c9e
  Alan Mishchenko committed 9 years ago
  
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25 Aug, 2015 4 commits
- Changing 'refactor' to work with truth tables. · 41d18ca0
  Alan Mishchenko committed 9 years ago
  
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- Changes to be able to compile ABC without CUDD. · 9ef96ae8
  Alan Mishchenko committed 9 years ago
  
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- Changes to be able to compile ABC without CUDD. · 99e3e3bc
  Alan Mishchenko committed 9 years ago
  
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- Changes to be able to compile ABC without CUDD. · 77d64787
  Alan Mishchenko committed 9 years ago
  
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30 Jul, 2015 1 commit
- Improvements to Cba data-structure. · bab71101
  Alan Mishchenko committed 9 years ago
  
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29 Jul, 2015 1 commit
- Improvements to Cba data-structure. · 7f7b7671
  Alan Mishchenko committed 9 years ago
  
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06 Apr, 2015 1 commit
- Several additional fixed in the timing manager. · b6b9d284
  Alan Mishchenko committed 9 years ago
  
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05 Apr, 2015 1 commit
- Improvements in reading timing information from BLIF. · 85b33df1
  Alan Mishchenko committed 9 years ago
  
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04 Apr, 2015 2 commits
- Properly copying and saving the timing info in &get and &put. · 3a15f343
  Alan Mishchenko committed 9 years ago
  
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- Properly copying and saving the timing info in &get and &put. · 7c3eab6e
  Alan Mishchenko committed 9 years ago
  
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18 Mar, 2015 1 commit
- Adding switch '-b' in 'read_pla'. · fb5d4a66
  Alan Mishchenko committed 9 years ago
  
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19 Feb, 2015 1 commit
- Propagating changes after updating flag of 'sop'. · e3f87e18
  Alan Mishchenko committed 10 years ago
  
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11 Feb, 2015 1 commit
- Adding resource limit switch -C to 'sop'. · 8cabdcb5
  Alan Mishchenko committed 10 years ago
  
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08 Feb, 2015 1 commit
- Fixed a typo in variable names. · 68467cff
  Alan Mishchenko committed 10 years ago
  
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05 Feb, 2015 1 commit
- Improvements and tuning of CBA with buffering/sizing. · 8410daf3
  Alan Mishchenko committed 10 years ago
  
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04 Feb, 2015 1 commit
- Esperiments with MO PLA optimization. · eb270018
  Alan Mishchenko committed 10 years ago
  
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31 Jan, 2015 5 commits
- Preprocessing for multi-output PLA tables. · e30dae5a
  Alan Mishchenko committed 10 years ago
  
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- Preprocessing for multi-output PLA tables. · 13cd3a6a
  Alan Mishchenko committed 10 years ago
  
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- Preprocessing for multi-output PLA tables. · e293489f
  Alan Mishchenko committed 10 years ago
  
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- Preprocessing for multi-output PLA tables. · 6c3f1911
  Alan Mishchenko committed 10 years ago
  
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- Preprocessing for multi-output PLA tables. · ff1fb175
  Alan Mishchenko committed 10 years ago
  
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14 Dec, 2014 1 commit
- Integrating barrier buffers. · 6b6e5861
  Alan Mishchenko committed 10 years ago
  
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12 Nov, 2014 1 commit
- Generation of barrier-buffers for hierarchical design. · 968be157
  Alan Mishchenko committed 10 years ago
  
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10 Nov, 2014 1 commit
- Adding cyclicity check for netlist with boxes. · 5ebf135b
  Alan Mishchenko committed 10 years ago
  
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04 Oct, 2014 1 commit
- Deriving AIG after cell mapping. · fa5f05e3
  Alan Mishchenko committed 10 years ago
  
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28 Sep, 2014 2 commits
- Adding out-of-bounds checks to AIGER readers. · 0c070a35
  Alan Mishchenko committed 10 years ago
  
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- Adding features to CNF generation. · 98e377bd
  Alan Mishchenko committed 10 years ago
  
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12 Sep, 2014 1 commit
- New word-level representation package. · dcb7d0d3
  Alan Mishchenko committed 10 years ago
  
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10 Sep, 2014 1 commit
- Bug fix in transferring timing info. · 49f2ec22
  Alan Mishchenko committed 10 years ago
  
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28 Aug, 2014 1 commit
- Compiler warning. · 17343bf1
  Alan Mishchenko committed 10 years ago
  
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