Improvements to the SCL package.

src/map/mpm/mpmGates.c

@@ -218,7 +218,7 @@ Abc_Ntk_t * Mpm_ManDeriveMappedAbcNtk( Mpm_Man_t * p, Mio_Library_t * pMio )
         pObj = Abc_NtkCreateNode( pNtk );
         pObj->pData = Vec_PtrEntry( vNpnGatesMio, Abc_Lit2Var(pCutBest->iFunc) );
         assert( pObj->pData != NULL );
-        fCompl = Abc_LitIsCompl(pCutBest->iFunc) ^ ((Config >> 16) & 1);
+        fCompl = pCutBest->fCompl ^ Abc_LitIsCompl(pCutBest->iFunc) ^ ((Config >> 16) & 1);
         Config &= 0xFFFF;
         for ( k = 0; k < (int)pCutBest->nLeaves; k++ )
         {

src/map/scl/sclDnsize.c

@@ -254,12 +254,13 @@ void Abc_SclDnsizePerform( SC_Lib * pLib, Abc_Ntk_t * pNtk, SC_DnSizePars * pPar
         printf( "Delay =%8.2f ps. ", pPars->DUser    );
         printf( "Iters =%5d.  ",     pPars->nIters   );
         printf( "UseDept =%2d. ",    pPars->fUseDept );
+        printf( "UseWL =%2d. ",      pPars->fUseWireLoads );
         printf( "Timeout =%4d sec",  pPars->TimeOut  );
         printf( "\n" );
     }
 
     // prepare the manager; collect init stats
-    p = Abc_SclManStart( pLib, pNtk, 1, pPars->fUseDept, SC_LibTimeFromPs(pLib, pPars->DUser) );
+    p = Abc_SclManStart( pLib, pNtk, pPars->fUseWireLoads, pPars->fUseDept, SC_LibTimeFromPs(pLib, pPars->DUser) );
     p->timeTotal  = Abc_Clock();
     assert( p->vGatesBest == NULL );
     p->vGatesBest = Vec_IntDup( p->vGates );

src/map/scl/sclInt.h

@@ -85,6 +85,7 @@ struct SC_UpSizePars_
     int        TimeOut;
     int        fUseDept;
     int        fDumpStats;
+    int        fUseWireLoads;
     int        fVerbose;
     int        fVeryVerbose;
 };
@@ -98,6 +99,7 @@ struct SC_DnSizePars_
     int        TimeOut;
     int        fUseDept;
     int        fDumpStats;
+    int        fUseWireLoads;
     int        fVerbose;
     int        fVeryVerbose;
 };
@@ -480,7 +482,7 @@ extern void          Abc_SclPrintCells( SC_Lib * p );
 extern Vec_Int_t *   Abc_SclManFindGates( SC_Lib * pLib, Abc_Ntk_t * p );
 extern void          Abc_SclManSetGates( SC_Lib * pLib, Abc_Ntk_t * p, Vec_Int_t * vGates );
 extern void          Abc_SclPrintGateSizes( SC_Lib * pLib, Abc_Ntk_t * p );
-extern void          Abc_SclMinsizePerform( SC_Lib * pLib, Abc_Ntk_t * p, int fVerbose );
+extern void          Abc_SclMinsizePerform( SC_Lib * pLib, Abc_Ntk_t * p, int fUseMax, int fVerbose );
 
 
 ABC_NAMESPACE_HEADER_END

src/map/scl/sclUpsize.c

@@ -475,16 +475,16 @@ void Abc_SclUpsizePerform( SC_Lib * pLib, Abc_Ntk_t * pNtk, SC_UpSizePars * pPar
     {
         printf( "Upsizing parameters: " );
         printf( "Iters =%5d.  ",          pPars->nIters   );
-        printf( "Time window =%3d %%. ",  pPars->Window   );
+        printf( "Time win =%3d %%. ",     pPars->Window   );
         printf( "Update ratio =%3d %%. ", pPars->Ratio    );
-        printf( "Max steps =%3d. ",       pPars->Notches  );
         printf( "UseDept =%2d. ",         pPars->fUseDept );
+        printf( "UseWL =%2d. ",           pPars->fUseWireLoads );
         printf( "Timeout =%4d sec",       pPars->TimeOut  );
         printf( "\n" );
     }
 
     // prepare the manager; collect init stats
-    p = Abc_SclManStart( pLib, pNtk, 1, pPars->fUseDept, 0 );
+    p = Abc_SclManStart( pLib, pNtk, pPars->fUseWireLoads, pPars->fUseDept, 0 );
     p->timeTotal  = Abc_Clock();
     assert( p->vGatesBest == NULL );
     p->vGatesBest = Vec_IntDup( p->vGates );
@@ -572,7 +572,7 @@ void Abc_SclUpsizePerform( SC_Lib * pLib, Abc_Ntk_t * pNtk, SC_UpSizePars * pPar
     if ( pPars->fVerbose )
         Abc_SclUpsizePrint( p, i, pPars->Window, nAllPos/(i?i:1), nAllNodes/(i?i:1), nAllUpsizes/(i?i:1), nAllTfos/(i?i:1), 1 );
     else
-        printf( "                                                                                                                                              \r" );
+        printf( "                                                                                                                                                  \r" );
     // report runtime
     p->timeTotal = Abc_Clock() - p->timeTotal;
     if ( pPars->fVerbose )

src/map/scl/sclUtil.c

@@ -303,17 +303,33 @@ void Abc_SclPrintGateSizes( SC_Lib * pLib, Abc_Ntk_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-void Abc_SclMinsizePerform( SC_Lib * pLib, Abc_Ntk_t * p, int fVerbose )
+SC_Cell * Abc_SclFindMaxAreaCell( SC_Cell * pRepr )
+{
+    SC_Cell * pCell, * pBest = pRepr;
+    float AreaBest = pRepr->area;
+    int i;
+    SC_RingForEachCell( pRepr, pCell, i )
+        if ( AreaBest < pCell->area )
+        {
+            AreaBest = pCell->area;
+            pBest = pCell;
+        }
+    return pBest;
+}
+void Abc_SclMinsizePerform( SC_Lib * pLib, Abc_Ntk_t * p, int fUseMax, int fVerbose )
 {
     Vec_Int_t * vMinCells, * vGates;
-    SC_Cell * pCell, * pRepr = NULL;
+    SC_Cell * pCell, * pRepr = NULL, * pBest = NULL;
     Abc_Obj_t * pObj;
     int i, k, gateId;
     // map each gate in the library into its min-size prototype
     vMinCells = Vec_IntStartFull( Vec_PtrSize(pLib->vCells) );
     SC_LibForEachCellClass( pLib, pRepr, i )
+    {
+        pBest = fUseMax ? Abc_SclFindMaxAreaCell(pRepr) : pRepr;
         SC_RingForEachCell( pRepr, pCell, k )
-            Vec_IntWriteEntry( vMinCells, pCell->Id, pRepr->Id );
+            Vec_IntWriteEntry( vMinCells, pCell->Id, pBest->Id );
+    }
     // update each cell
     vGates = Abc_SclManFindGates( pLib, p );
     Abc_NtkForEachNode1( p, pObj, i )
@@ -329,7 +345,6 @@ void Abc_SclMinsizePerform( SC_Lib * pLib, Abc_Ntk_t * p, int fVerbose )
     Vec_IntFree( vGates );
 }
 
-
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////