Fixes to Verilog parser.

src/base/abc/abc.h

@@ -192,8 +192,8 @@ struct Abc_Ntk_t_
     int               iStep;         // the generation number for the given network
     // hierarchy
     Abc_Lib_t *       pDesign;
-    short             fHieVisited;   // flag to mark the visited network
-    short             fHiePath;      // flag to mark the network on the path
+    int               fHieVisited;   // flag to mark the visited network
+    int               fHiePath;      // flag to mark the network on the path
     int               Id;            // model ID
     double            dTemp;         // temporary value
     // miscellaneous data members

src/base/io/io.c

@@ -197,6 +197,12 @@ int IoCommandRead( Abc_Frame_t * pAbc, int argc, char ** argv )
     for ( pTemp = pFileName; *pTemp; pTemp++ )
         if ( *pTemp == '>' )
             *pTemp = '\\';
+    // check if the library is available
+    if ( glo_fMapped && Abc_FrameReadLibGen() == NULL )
+    {
+        Abc_Print( 1, "Cannot read mapped design when the library is not given.\n" );
+        return 0;
+    }
     // read the file using the corresponding file reader
     pNtk = Io_Read( pFileName, Io_ReadFileType(pFileName), fCheck );
     if ( pNtk == NULL )

src/base/ver/verCore.c

@@ -2538,7 +2538,7 @@ int Ver_ParseDriveFormal( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_Bundle_t * pBu
         Vec_PtrForEachEntry( Abc_Obj_t *, pBundle->vNetsActual, pNetAct, m )
             if ( Abc_ObjFaninNum(pNetAct) > 0 )
             {
-                sprintf( pMan->sError, "Internal error while trying to connect undefined boxes. It is likely that the algorithm currently used has its limitations." );
+                sprintf( pMan->sError, "Missing specification of the I/Os of undefined box \"%s\".", Abc_NtkName(pNtk) );
                 Ver_ParsePrintErrorMessage( pMan );
                 return 0;
             }