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lvzhengyang
abc
Commits
f1b64be8
Commit
f1b64be8
authored
Dec 16, 2021
by
Alan Mishchenko
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Compiler warning.
parent
fb248e1c
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8 deletions
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src/base/wln/wlnRtl.c
+7
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src/base/wln/wlnRtl.c
View file @
f1b64be8
...
@@ -21,6 +21,13 @@
...
@@ -21,6 +21,13 @@
#include "wln.h"
#include "wln.h"
#include "base/main/main.h"
#include "base/main/main.h"
#ifdef WIN32
#include <process.h>
#define unlink _unlink
#else
#include <unistd.h>
#endif
ABC_NAMESPACE_IMPL_START
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
...
@@ -110,11 +117,7 @@ Wln_Ntk_t * Wln_ReadSystemVerilog( char * pFileName, char * pTopModule, int fVer
...
@@ -110,11 +117,7 @@ Wln_Ntk_t * Wln_ReadSystemVerilog( char * pFileName, char * pTopModule, int fVer
printf
(
"Dumped the design into file
\"
%s
\"
.
\n
"
,
pFileTemp
);
printf
(
"Dumped the design into file
\"
%s
\"
.
\n
"
,
pFileTemp
);
return
NULL
;
return
NULL
;
}
}
#ifdef WIN32
_unlink
(
pFileTemp
);
#else
unlink
(
pFileTemp
);
unlink
(
pFileTemp
);
#endif
return
pNtk
;
return
pNtk
;
}
}
Gia_Man_t
*
Wln_BlastSystemVerilog
(
char
*
pFileName
,
char
*
pTopModule
,
int
fSkipStrash
,
int
fInvert
,
int
fVerbose
)
Gia_Man_t
*
Wln_BlastSystemVerilog
(
char
*
pFileName
,
char
*
pTopModule
,
int
fSkipStrash
,
int
fInvert
,
int
fVerbose
)
...
@@ -139,11 +142,7 @@ Gia_Man_t * Wln_BlastSystemVerilog( char * pFileName, char * pTopModule, int fSk
...
@@ -139,11 +142,7 @@ Gia_Man_t * Wln_BlastSystemVerilog( char * pFileName, char * pTopModule, int fSk
ABC_FREE
(
pGia
->
pName
);
ABC_FREE
(
pGia
->
pName
);
pGia
->
pName
=
pTopModule
?
Abc_UtilStrsav
(
pTopModule
)
:
pGia
->
pName
=
pTopModule
?
Abc_UtilStrsav
(
pTopModule
)
:
Extra_FileNameGeneric
(
Extra_FileNameWithoutPath
(
pFileName
)
);
Extra_FileNameGeneric
(
Extra_FileNameWithoutPath
(
pFileName
)
);
#ifdef WIN32
_unlink
(
pFileTemp
);
#else
unlink
(
pFileTemp
);
unlink
(
pFileTemp
);
#endif
// complement the outputs
// complement the outputs
if
(
fInvert
)
if
(
fInvert
)
{
{
...
...
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