Integrating GIA with LUT mapping.

src/aig/gia/giaIf.c

@@ -30,6 +30,9 @@ ABC_NAMESPACE_IMPL_START
 ///                        DECLARATIONS                              ///
 ////////////////////////////////////////////////////////////////////////
 
+extern int Kit_TruthToGia( Gia_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory, Vec_Int_t * vLeaves, int fHash );
+extern int Abc_RecToGia2( Gia_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut, If_Obj_t * pIfObj, Vec_Int_t * vLeaves, int fHash );
+
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
 ////////////////////////////////////////////////////////////////////////
@@ -315,7 +318,7 @@ If_Man_t * Gia_ManToIf( Gia_Man_t * p, If_Par_t * pPars )
   SeeAlso     []
 
 ***********************************************************************/
-int Gia_ManNodeIfSopToGiaInt( Gia_Man_t * pNew, Vec_Wrd_t * vAnds, int nVars, Vec_Int_t * vLeaves )
+int Gia_ManNodeIfSopToGiaInt( Gia_Man_t * pNew, Vec_Wrd_t * vAnds, int nVars, Vec_Int_t * vLeaves, int fHash )
 {
     Vec_Int_t * vResults;
     int iRes0, iRes1, iRes;
@@ -334,19 +337,21 @@ int Gia_ManNodeIfSopToGiaInt( Gia_Man_t * pNew, Vec_Wrd_t * vAnds, int nVars, Ve
         This  = If_WrdToAnd( Entry );
         iRes0 = Abc_LitNotCond( Vec_IntEntry(vResults, This.iFan0), This.fCompl0 ); 
         iRes1 = Abc_LitNotCond( Vec_IntEntry(vResults, This.iFan1), This.fCompl1 ); 
-        iRes  = Gia_ManHashAnd( pNew, iRes0, iRes1 );
-//        iRes  = Gia_ManAppendAnd( pNew, iRes0, iRes1 );
+        if ( fHash )
+            iRes  = Gia_ManHashAnd( pNew, iRes0, iRes1 );
+        else
+            iRes  = Gia_ManAppendAnd( pNew, iRes0, iRes1 );
         Vec_IntPush( vResults, iRes );
     }
     Vec_IntFree( vResults );
     return Abc_LitNotCond( iRes, This.fCompl );
 }
-int Gia_ManNodeIfSopToGia( Gia_Man_t * pNew, If_Man_t * p, If_Cut_t * pCut, Vec_Int_t * vLeaves )
+int Gia_ManNodeIfSopToGia( Gia_Man_t * pNew, If_Man_t * p, If_Cut_t * pCut, Vec_Int_t * vLeaves, int fHash )
 {
     int iResult;
     Vec_Wrd_t * vArray;
     vArray  = If_CutDelaySopArray( p, pCut );
-    iResult = Gia_ManNodeIfSopToGiaInt( pNew, vArray, If_CutLeaveNum(pCut), vLeaves );
+    iResult = Gia_ManNodeIfSopToGiaInt( pNew, vArray, If_CutLeaveNum(pCut), vLeaves, fHash );
 //    Vec_WrdFree( vArray );
     return iResult;
 }
@@ -362,7 +367,7 @@ int Gia_ManNodeIfSopToGia( Gia_Man_t * pNew, If_Man_t * p, If_Cut_t * pCut, Vec_
   SeeAlso     []
 
 ***********************************************************************/
-int Gia_ManNodeIfToGia_rec( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfObj, Vec_Ptr_t * vVisited )
+int Gia_ManNodeIfToGia_rec( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfObj, Vec_Ptr_t * vVisited, int fHash )
 {
     If_Cut_t * pCut;
     If_Obj_t * pTemp;
@@ -382,15 +387,17 @@ int Gia_ManNodeIfToGia_rec( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfO
     // compute the functions of the children
     for ( pTemp = pIfObj; pTemp; pTemp = pTemp->pEquiv )
     {
-        iFunc0 = Gia_ManNodeIfToGia_rec( pNew, pIfMan, pTemp->pFanin0, vVisited );
+        iFunc0 = Gia_ManNodeIfToGia_rec( pNew, pIfMan, pTemp->pFanin0, vVisited, fHash );
         if ( iFunc0 == ~0 )
             continue;
-        iFunc1 = Gia_ManNodeIfToGia_rec( pNew, pIfMan, pTemp->pFanin1, vVisited );
+        iFunc1 = Gia_ManNodeIfToGia_rec( pNew, pIfMan, pTemp->pFanin1, vVisited, fHash );
         if ( iFunc1 == ~0 )
             continue;
         // both branches are solved
-        iFunc = Gia_ManHashAnd( pNew, Abc_LitNotCond(iFunc0, pTemp->fCompl0), Abc_LitNotCond(iFunc1, pTemp->fCompl1) ); 
-//        iFunc = Gia_ManAppendAnd( pNew, Abc_LitNotCond(iFunc0, pTemp->fCompl0), Abc_LitNotCond(iFunc1, pTemp->fCompl1) ); 
+        if ( fHash )
+            iFunc = Gia_ManHashAnd( pNew, Abc_LitNotCond(iFunc0, pTemp->fCompl0), Abc_LitNotCond(iFunc1, pTemp->fCompl1) ); 
+        else
+            iFunc = Gia_ManAppendAnd( pNew, Abc_LitNotCond(iFunc0, pTemp->fCompl0), Abc_LitNotCond(iFunc1, pTemp->fCompl1) ); 
         if ( pTemp->fPhase != pIfObj->fPhase )
             iFunc = Abc_LitNot(iFunc);
         If_CutSetDataInt( pCut, iFunc );
@@ -398,7 +405,7 @@ int Gia_ManNodeIfToGia_rec( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfO
     }
     return If_CutDataInt(pCut);
 }
-int Gia_ManNodeIfToGia( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfObj, Vec_Int_t * vLeaves )
+int Gia_ManNodeIfToGia( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfObj, Vec_Int_t * vLeaves, int fHash )
 {
     If_Cut_t * pCut;
     If_Obj_t * pLeaf;
@@ -411,7 +418,7 @@ int Gia_ManNodeIfToGia( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfObj,
         If_CutSetDataInt( If_ObjCutBest(pLeaf), Vec_IntEntry(vLeaves, i) );
     // recursively compute the function while collecting visited cuts
     Vec_PtrClear( pIfMan->vTemp );
-    iRes = Gia_ManNodeIfToGia_rec( pNew, pIfMan, pIfObj, pIfMan->vTemp ); 
+    iRes = Gia_ManNodeIfToGia_rec( pNew, pIfMan, pIfObj, pIfMan->vTemp, fHash ); 
     if ( iRes == ~0 )
     {
         Abc_Print( -1, "Gia_ManNodeIfToGia(): Computing local AIG has failed.\n" );
@@ -438,10 +445,12 @@ int Gia_ManNodeIfToGia( Gia_Man_t * pNew, If_Man_t * pIfMan, If_Obj_t * pIfObj,
 ***********************************************************************/
 Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
 {
+    int fHash = 0;
     Gia_Man_t * pNew;
     If_Obj_t * pIfObj, * pIfLeaf;
     If_Cut_t * pCutBest;
     Vec_Int_t * vLeaves;
+    Vec_Int_t * vCover;
     unsigned * pTruth;
     int Counter, iOffset, nItems = 0;
     int i, k, w, GiaId;
@@ -449,6 +458,7 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
     pNew = Gia_ManStart( If_ManObjNum(pIfMan) );
     Gia_ManHashAlloc( pNew );
     // iterate through nodes used in the mapping
+    vCover = Vec_IntAlloc( 1 << 16 );
     vLeaves = Vec_IntAlloc( 16 );
     If_ManCleanCutData( pIfMan );
     If_ManForEachObj( pIfMan, pIfObj, i )
@@ -463,10 +473,18 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
             If_CutForEachLeaf( pIfMan, pCutBest, pIfLeaf, k )
                 Vec_IntPush( vLeaves, pIfLeaf->iCopy );
             // get the functionality
-            if ( pIfMan->pPars->fDelayOpt )
-                pIfObj->iCopy = Gia_ManNodeIfSopToGia( pNew, pIfMan, pCutBest, vLeaves );
+            if ( pIfMan->pPars->pLutStruct )
+                pIfObj->iCopy = Kit_TruthToGia( pNew, If_CutTruth(pCutBest), If_CutLeaveNum(pCutBest), vCover, vLeaves, fHash );
+            else if ( pIfMan->pPars->fDelayOpt )
+                pIfObj->iCopy = Gia_ManNodeIfSopToGia( pNew, pIfMan, pCutBest, vLeaves, fHash );
+            else if ( pIfMan->pPars->fUserRecLib )
+                pIfObj->iCopy = Abc_RecToGia2( pNew, pIfMan, pCutBest, pIfObj, vLeaves, fHash );
             else
-                pIfObj->iCopy = Gia_ManNodeIfToGia( pNew, pIfMan, pIfObj, vLeaves );
+                pIfObj->iCopy = Gia_ManNodeIfToGia( pNew, pIfMan, pIfObj, vLeaves, fHash );
+            // complement the node if the TT was used and the cut was complemented
+            if ( pIfMan->pPars->pLutStruct )
+                pIfObj->iCopy = Abc_LitNotCond( pIfObj->iCopy, pCutBest->fCompl );
+            // count entries in the mapping array
             nItems += 2 + If_CutLeaveNum( pCutBest );
         }
         else if ( If_ObjIsCi(pIfObj) )
@@ -480,6 +498,7 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
         }
         else assert( 0 );
     }
+    Vec_IntFree( vCover );
     Vec_IntFree( vLeaves );
     Gia_ManHashStop( pNew );
 
@@ -501,8 +520,10 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
         if ( pIfObj->nRefs == 0 && !If_ObjIsTerm(pIfObj) )
             continue;
         if ( If_ObjIsAnd(pIfObj) )
-        {
+        { 
             GiaId = Abc_Lit2Var( pIfObj->iCopy );
+            if ( !Gia_ObjIsAnd(Gia_ManObj(pNew, GiaId)) ) // skip trivial node
+                continue;
             assert( Gia_ObjIsAnd(Gia_ManObj(pNew, GiaId)) );
             if ( !Gia_ManObj(pNew, GiaId)->fMark0 ) // skip dangling node
                 continue;
@@ -526,10 +547,10 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
             pNew->pMapping[iOffset++] = If_CutLeaveNum(pCutBest);
             If_CutForEachLeaf( pIfMan, pCutBest, pIfLeaf, k )
             {
-                GiaId = Abc_Lit2Var(pIfLeaf->iCopy);
+                int FaninId = Abc_Lit2Var(pIfLeaf->iCopy);
                 if ( pTruth && Abc_LitIsCompl(pIfLeaf->iCopy) )
                     Kit_TruthChangePhase( pTruth, If_CutLeaveNum(pCutBest), k );
-                if ( !Gia_ManObj(pNew, GiaId)->fMark0 ) // skip dangling node
+                if ( !Gia_ManObj(pNew, FaninId)->fMark0 ) // skip dangling node
                 {
                     // update truth table
                     if ( pTruth )
@@ -547,7 +568,8 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
                     pNew->pMapping[iOffset-k-1]--;
                     continue;
                 }
-                pNew->pMapping[iOffset++] = GiaId;
+                assert( FaninId != GiaId );
+                pNew->pMapping[iOffset++] = FaninId;
             }
             pNew->pMapping[iOffset++] = GiaId;
         }

src/base/abci/abcRec2.c

@@ -86,6 +86,7 @@ struct Abc_ManRec_t_2
     Vec_Ptr_t *       vNodes;                   // the temporary nodes
     Vec_Ptr_t *       vTtTemps;                 // the truth tables for the internal nodes of the cut
     Vec_Ptr_t *       vLabels;                  // temporary storage for AIG node labels
+    Vec_Int_t *       vLabelsInt;               // temporary storage for AIG node labels
     Vec_Int_t *       vUselessPos;
     // statistics
     int               nTried;                   // the number of cuts tried
@@ -1144,6 +1145,7 @@ p->timeInsert += clock() - timeInsert;
     p->vNodes = Vec_PtrAlloc( 100 );
     p->vTtTemps = Vec_PtrAllocSimInfo( 1024, p->nWords );
     p->vLabels = Vec_PtrStart( 1000 );
+    p->vLabelsInt = Vec_IntStart( 1000 );
 
 
  p->timeTotal += clock() - clkTotal;  
@@ -2065,6 +2067,105 @@ Hop_Obj_t * Abc_RecToHop2( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut,
 
 /**Function*************************************************************
 
+  Synopsis    [Derive the final network from the library.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Abc_RecToGia2( Gia_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut, If_Obj_t * pIfObj, Vec_Int_t * vLeaves, int fHash )
+{
+    Rec_Obj_t2 * pCandMin;
+    int pHopObj, pFan0, pFan1;
+    Gia_Obj_t* pGiaObj, *pGiaTemp;
+    Gia_Man_t * pAig = s_pMan->pGia;
+    int nLeaves, i;// DelayMin = ABC_INFINITY , Delay = -ABC_INFINITY
+    unsigned uCanonPhase;
+    int nVars = s_pMan->nVars;
+    char pCanonPerm[16];
+    unsigned *pInOut = s_pMan->pTemp1;
+    unsigned *pTemp = s_pMan->pTemp2;
+    int time = clock();
+    int fCompl;
+    int * pCompl = &fCompl;
+    nLeaves = If_CutLeaveNum(pCut);
+//  if (nLeaves < 3)
+//      return Abc_NodeTruthToHop(pMan, pIfMan, pCut);
+    Kit_TruthCopy(pInOut, If_CutTruth(pCut), pCut->nLimit);
+    //special cases when cut-minimization return 2, that means there is only one leaf in the cut.
+    if ((Kit_TruthIsConst0(pInOut, nLeaves) && pCut->fCompl == 0) || (Kit_TruthIsConst1(pInOut, nLeaves) && pCut->fCompl == 1))
+        return 0;
+    if ((Kit_TruthIsConst0(pInOut, nLeaves) && pCut->fCompl == 1) || (Kit_TruthIsConst1(pInOut, nLeaves) && pCut->fCompl == 0))
+        return 1;
+    if (Kit_TruthSupport(pInOut, nLeaves) != Kit_BitMask(nLeaves))
+    {   
+        for (i = 0; i < nLeaves; i++)
+            if(Kit_TruthVarInSupport( pInOut, nLeaves, i ))
+                return Abc_LitNotCond( Vec_IntEntry(vLeaves, i), (pCut->fCompl ^ ((*pInOut & 0x01) > 0)) );
+    }
+    
+    for (i = 0; i < nLeaves; i++)
+        pCanonPerm[i] = i;
+    uCanonPhase = Kit_TruthSemiCanonicize_new(pInOut, pTemp, nLeaves, pCanonPerm);
+    If_CutTruthStretch(pInOut, nLeaves, nVars);
+    pCandMin = Abc_NtkRecLookUpBest(pIfMan, pCut, pInOut, pCanonPerm, pCompl,NULL);
+
+    // get the top-most GIA node
+    pGiaObj = Abc_NtkRecGetObj( Rec_ObjID(s_pMan, pCandMin) );
+    assert( Gia_ObjIsAnd(pGiaObj) || Gia_ObjIsPi(pAig, pGiaObj) );
+    // collect internal nodes into pAig->vTtNodes
+    if ( pAig->vTtNodes == NULL )
+        pAig->vTtNodes = Vec_IntAlloc( 256 );
+    Gia_ObjCollectInternal( pAig, pGiaObj );
+    // collect HOP nodes for leaves
+    Vec_IntClear( s_pMan->vLabelsInt );
+    for (i = 0; i < nLeaves; i++)
+    {
+        pHopObj = Vec_IntEntry(vLeaves, pCanonPerm[i]);
+        pHopObj = Abc_LitNotCond(pHopObj, ((uCanonPhase & (1 << i)) > 0));
+        Vec_IntPush(s_pMan->vLabelsInt, pHopObj);
+    }
+    // compute HOP nodes for internal nodes
+    Gia_ManForEachObjVec( pAig->vTtNodes, pAig, pGiaTemp, i )
+    {
+        pGiaTemp->fMark0 = 0; // unmark node marked by Gia_ObjCollectInternal()
+
+        if ( Gia_ObjIsAnd(Gia_ObjFanin0(pGiaTemp)) )
+            pFan0 = Vec_IntEntry(s_pMan->vLabelsInt, Gia_ObjNum(pAig, Gia_ObjFanin0(pGiaTemp)) + nLeaves);
+        else
+            pFan0 = Vec_IntEntry(s_pMan->vLabelsInt, Gia_ObjCioId(Gia_ObjFanin0(pGiaTemp)));
+        pFan0 = Abc_LitNotCond(pFan0, Gia_ObjFaninC0(pGiaTemp));
+
+        if ( Gia_ObjIsAnd(Gia_ObjFanin1(pGiaTemp)) )
+            pFan1 = Vec_IntEntry(s_pMan->vLabelsInt, Gia_ObjNum(pAig, Gia_ObjFanin1(pGiaTemp)) + nLeaves);
+        else
+            pFan1 = Vec_IntEntry(s_pMan->vLabelsInt, Gia_ObjCioId(Gia_ObjFanin1(pGiaTemp)));
+        pFan1 = Abc_LitNotCond(pFan1, Gia_ObjFaninC1(pGiaTemp));
+
+        if ( fHash )
+            pHopObj = Gia_ManHashAnd(pMan, pFan0, pFan1);
+        else
+            pHopObj = Gia_ManAppendAnd(pMan, pFan0, pFan1);
+        Vec_IntPush(s_pMan->vLabelsInt, pHopObj);
+    }
+    // get the final result
+    if ( Gia_ObjIsAnd(pGiaObj) )
+        pHopObj = Vec_IntEntry(s_pMan->vLabelsInt, Gia_ObjNum(pAig, pGiaObj) + nLeaves);
+    else if ( Gia_ObjIsPi(pAig, pGiaObj) )
+        pHopObj = Vec_IntEntry(s_pMan->vLabelsInt, Gia_ObjCioId(pGiaObj));
+    else assert( 0 );
+    
+    s_pMan->timeIfDerive += clock() - time;
+    s_pMan->timeIfTotal += clock() - time;
+    // complement the result if needed
+    return Abc_LitNotCond(pHopObj, (pCut->fCompl)^(((uCanonPhase & (1 << nLeaves)) > 0)) ^ fCompl);    
+}
+
+/**Function*************************************************************
+
   Synopsis    [Returns the given record.]
 
   Description []
@@ -2097,8 +2198,8 @@ void Abc_NtkRecStop2()
     ABC_FREE( s_pMan->pTemp2 );
     Vec_PtrFree( s_pMan->vNodes );
     Vec_PtrFree( s_pMan->vTtTemps );
-    if ( s_pMan->vLabels )
-        Vec_PtrFree( s_pMan->vLabels );
+    Vec_PtrFree( s_pMan->vLabels );
+    Vec_IntFree( s_pMan->vLabelsInt );
     //if(s_pMan->pMemObj)
     //    Mem_FixedStop(s_pMan->pMemObj, 0);
     Vec_IntFree( s_pMan->vUselessPos);

src/bool/kit/kit.h

@@ -68,7 +68,8 @@ struct Kit_Node_t_
     Kit_Edge_t        eEdge0;          // the left child of the node
     Kit_Edge_t        eEdge1;          // the right child of the node
     // other info
-    void *            pFunc;           // the function of the node (BDD or AIG)
+    union { int       iFunc;           // the function of the node (BDD or AIG)
+    void *            pFunc; };        // the function of the node (BDD or AIG)
     unsigned          Level    : 14;   // the level of this node in the global AIG
     // printing info 
     unsigned          fNodeOr  :  1;   // marks the original OR node
@@ -561,6 +562,7 @@ extern unsigned        Kit_GraphToTruth( Kit_Graph_t * pGraph );
 extern Kit_Graph_t *   Kit_TruthToGraph( unsigned * pTruth, int nVars, Vec_Int_t * vMemory );
 extern int             Kit_GraphLeafDepth_rec( Kit_Graph_t * pGraph, Kit_Node_t * pNode, Kit_Node_t * pLeaf );
 /*=== kitHop.c ==========================================================*/
+//extern int             Kit_TruthToGia( Gia_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory, Vec_Int_t * vLeaves, int fHash );
 //extern Hop_Obj_t *     Kit_GraphToHop( Hop_Man_t * pMan, Kit_Graph_t * pGraph );
 //extern Hop_Obj_t *     Kit_TruthToHop( Hop_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory );
 //extern Hop_Obj_t *     Kit_CoverToHop( Hop_Man_t * pMan, Vec_Int_t * vCover, int nVars, Vec_Int_t * vMemory );

src/bool/kit/kitHop.c

@@ -20,6 +20,7 @@
 
 #include "kit.h"
 #include "aig/hop/hop.h"
+#include "aig/gia/gia.h"
 
 ABC_NAMESPACE_IMPL_START
 
@@ -43,31 +44,66 @@ ABC_NAMESPACE_IMPL_START
   SeeAlso     []
 
 ***********************************************************************/
-Hop_Obj_t * Kit_GraphToHopInternal( Hop_Man_t * pMan, Kit_Graph_t * pGraph )
+int Kit_GraphToGiaInternal( Gia_Man_t * pMan, Kit_Graph_t * pGraph, int fHash )
 {
     Kit_Node_t * pNode = NULL;
-    Hop_Obj_t * pAnd0, * pAnd1;
-    int i;
+    int i, pAnd0, pAnd1;
     // check for constant function
     if ( Kit_GraphIsConst(pGraph) )
-        return Hop_NotCond( Hop_ManConst1(pMan), Kit_GraphIsComplement(pGraph) );
+        return Abc_LitNotCond( 1, Kit_GraphIsComplement(pGraph) );
     // check for a literal
     if ( Kit_GraphIsVar(pGraph) )
-        return Hop_NotCond( (Hop_Obj_t *)Kit_GraphVar(pGraph)->pFunc, Kit_GraphIsComplement(pGraph) );
+        return Abc_LitNotCond( Kit_GraphVar(pGraph)->iFunc, Kit_GraphIsComplement(pGraph) );
     // build the AIG nodes corresponding to the AND gates of the graph
     Kit_GraphForEachNode( pGraph, pNode, i )
     {
-        pAnd0 = Hop_NotCond( (Hop_Obj_t *)Kit_GraphNode(pGraph, pNode->eEdge0.Node)->pFunc, pNode->eEdge0.fCompl ); 
-        pAnd1 = Hop_NotCond( (Hop_Obj_t *)Kit_GraphNode(pGraph, pNode->eEdge1.Node)->pFunc, pNode->eEdge1.fCompl ); 
-        pNode->pFunc = Hop_And( pMan, pAnd0, pAnd1 );
+        pAnd0 = Abc_LitNotCond( Kit_GraphNode(pGraph, pNode->eEdge0.Node)->iFunc, pNode->eEdge0.fCompl ); 
+        pAnd1 = Abc_LitNotCond( Kit_GraphNode(pGraph, pNode->eEdge1.Node)->iFunc, pNode->eEdge1.fCompl ); 
+        if ( fHash )
+            pNode->iFunc = Gia_ManHashAnd( pMan, pAnd0, pAnd1 );
+        else
+            pNode->iFunc = Gia_ManAppendAnd( pMan, pAnd0, pAnd1 );
     }
     // complement the result if necessary
-    return Hop_NotCond( (Hop_Obj_t *)pNode->pFunc, Kit_GraphIsComplement(pGraph) );
+    return Abc_LitNotCond( pNode->iFunc, Kit_GraphIsComplement(pGraph) );
+}
+int Kit_GraphToGia( Gia_Man_t * pMan, Kit_Graph_t * pGraph, Vec_Int_t * vLeaves, int fHash )
+{
+    Kit_Node_t * pNode = NULL;
+    int i;
+    // collect the fanins
+    Kit_GraphForEachLeaf( pGraph, pNode, i )
+        pNode->iFunc = Vec_IntEntry( vLeaves, i );
+    // perform strashing
+    return Kit_GraphToGiaInternal( pMan, pGraph, fHash );
+}
+int Kit_TruthToGia( Gia_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory, Vec_Int_t * vLeaves, int fHash )
+{
+    int iLit;
+    Kit_Graph_t * pGraph;
+    // transform truth table into the decomposition tree
+    if ( vMemory == NULL )
+    {
+        vMemory = Vec_IntAlloc( 0 );
+        pGraph = Kit_TruthToGraph( pTruth, nVars, vMemory );
+        Vec_IntFree( vMemory );
+    }
+    else
+        pGraph = Kit_TruthToGraph( pTruth, nVars, vMemory );
+    if ( pGraph == NULL )
+    {
+        printf( "Kit_TruthToGia(): Converting truth table to AIG has failed for function:\n" );
+        Kit_DsdPrintFromTruth( pTruth, nVars ); printf( "\n" );
+    }
+    // derive the AIG for the decomposition tree
+    iLit = Kit_GraphToGia( pMan, pGraph, vLeaves, fHash );
+    Kit_GraphFree( pGraph );
+    return iLit;
 }
 
 /**Function*************************************************************
 
-  Synopsis    [Strashes one logic node using its SOP.]
+  Synopsis    [Transforms the decomposition graph into the AIG.]
 
   Description []
                
@@ -76,6 +112,27 @@ Hop_Obj_t * Kit_GraphToHopInternal( Hop_Man_t * pMan, Kit_Graph_t * pGraph )
   SeeAlso     []
 
 ***********************************************************************/
+Hop_Obj_t * Kit_GraphToHopInternal( Hop_Man_t * pMan, Kit_Graph_t * pGraph )
+{
+    Kit_Node_t * pNode = NULL;
+    Hop_Obj_t * pAnd0, * pAnd1;
+    int i;
+    // check for constant function
+    if ( Kit_GraphIsConst(pGraph) )
+        return Hop_NotCond( Hop_ManConst1(pMan), Kit_GraphIsComplement(pGraph) );
+    // check for a literal
+    if ( Kit_GraphIsVar(pGraph) )
+        return Hop_NotCond( (Hop_Obj_t *)Kit_GraphVar(pGraph)->pFunc, Kit_GraphIsComplement(pGraph) );
+    // build the AIG nodes corresponding to the AND gates of the graph
+    Kit_GraphForEachNode( pGraph, pNode, i )
+    {
+        pAnd0 = Hop_NotCond( (Hop_Obj_t *)Kit_GraphNode(pGraph, pNode->eEdge0.Node)->pFunc, pNode->eEdge0.fCompl ); 
+        pAnd1 = Hop_NotCond( (Hop_Obj_t *)Kit_GraphNode(pGraph, pNode->eEdge1.Node)->pFunc, pNode->eEdge1.fCompl ); 
+        pNode->pFunc = Hop_And( pMan, pAnd0, pAnd1 );
+    }
+    // complement the result if necessary
+    return Hop_NotCond( (Hop_Obj_t *)pNode->pFunc, Kit_GraphIsComplement(pGraph) );
+}
 Hop_Obj_t * Kit_GraphToHop( Hop_Man_t * pMan, Kit_Graph_t * pGraph )
 {
     Kit_Node_t * pNode = NULL;
@@ -86,18 +143,6 @@ Hop_Obj_t * Kit_GraphToHop( Hop_Man_t * pMan, Kit_Graph_t * pGraph )
     // perform strashing
     return Kit_GraphToHopInternal( pMan, pGraph );
 }
-
-/**Function*************************************************************
-
-  Synopsis    [Strashed onen logic nodes using its truth table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
 Hop_Obj_t * Kit_TruthToHop( Hop_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory )
 {
     Hop_Obj_t * pObj;