Commit e3e2918e by Alan Mishchenko

Version abc90405

parent 23fd1103
...@@ -3695,6 +3695,10 @@ SOURCE=.\src\aig\gia\giaCSat.c ...@@ -3695,6 +3695,10 @@ SOURCE=.\src\aig\gia\giaCSat.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\gia\giaCSatOld.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaDfs.c SOURCE=.\src\aig\gia\giaDfs.c
# End Source File # End Source File
# Begin Source File # Begin Source File
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [] Synopsis []
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [External declarations.] Synopsis [External declarations.]
...@@ -44,6 +44,7 @@ struct Cec_ParSat_t_ ...@@ -44,6 +44,7 @@ struct Cec_ParSat_t_
int nBTLimit; // conflict limit at a node int nBTLimit; // conflict limit at a node
int nSatVarMax; // the max number of SAT variables int nSatVarMax; // the max number of SAT variables
int nCallsRecycle; // calls to perform before recycling SAT solver int nCallsRecycle; // calls to perform before recycling SAT solver
int fNonChrono; // use non-chronological backtracling (for circuit SAT only)
int fPolarFlip; // flops polarity of variables int fPolarFlip; // flops polarity of variables
int fCheckMiter; // the circuit is the miter int fCheckMiter; // the circuit is the miter
int fFirstStop; // stop on the first sat output int fFirstStop; // stop on the first sat output
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Integrated combinatinal equivalence checker.] Synopsis [Integrated combinatinal equivalence checker.]
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Computation of structural choices.] Synopsis [Computation of structural choices.]
......
...@@ -4,9 +4,9 @@ ...@@ -4,9 +4,9 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Equivalence class representation.] Synopsis [Equivalence class refinement.]
Author [Alan Mishchenko] Author [Alan Mishchenko]
...@@ -838,6 +838,8 @@ int Cec_ManSimClassesPrepare( Cec_ManSim_t * p ) ...@@ -838,6 +838,8 @@ int Cec_ManSimClassesPrepare( Cec_ManSim_t * p )
// allocate representation // allocate representation
p->pAig->pReprs = ABC_CALLOC( Gia_Rpr_t, Gia_ManObjNum(p->pAig) ); p->pAig->pReprs = ABC_CALLOC( Gia_Rpr_t, Gia_ManObjNum(p->pAig) );
p->pAig->pNexts = ABC_CALLOC( int, Gia_ManObjNum(p->pAig) ); p->pAig->pNexts = ABC_CALLOC( int, Gia_ManObjNum(p->pAig) );
// create references
Gia_ManSetRefs( p->pAig );
// set starting representative of internal nodes to be constant 0 // set starting representative of internal nodes to be constant 0
if ( p->pPars->fLatchCorr ) if ( p->pPars->fLatchCorr )
Gia_ManForEachObj( p->pAig, pObj, i ) Gia_ManForEachObj( p->pAig, pObj, i )
...@@ -848,9 +850,9 @@ int Cec_ManSimClassesPrepare( Cec_ManSim_t * p ) ...@@ -848,9 +850,9 @@ int Cec_ManSimClassesPrepare( Cec_ManSim_t * p )
// if sequential simulation, set starting representative of ROs to be constant 0 // if sequential simulation, set starting representative of ROs to be constant 0
if ( p->pPars->fSeqSimulate ) if ( p->pPars->fSeqSimulate )
Gia_ManForEachRo( p->pAig, pObj, i ) Gia_ManForEachRo( p->pAig, pObj, i )
Gia_ObjSetRepr( p->pAig, Gia_ObjId(p->pAig, pObj), 0 ); if ( pObj->Value )
Gia_ObjSetRepr( p->pAig, Gia_ObjId(p->pAig, pObj), 0 );
// perform simulation // perform simulation
Gia_ManSetRefs( p->pAig );
p->nWords = 1; p->nWords = 1;
do { do {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Core procedures.] Synopsis [Core procedures.]
...@@ -42,9 +42,10 @@ ...@@ -42,9 +42,10 @@
void Cec_ManSatSetDefaultParams( Cec_ParSat_t * p ) void Cec_ManSatSetDefaultParams( Cec_ParSat_t * p )
{ {
memset( p, 0, sizeof(Cec_ParSat_t) ); memset( p, 0, sizeof(Cec_ParSat_t) );
p->nBTLimit = 10; // conflict limit at a node p->nBTLimit = 100; // conflict limit at a node
p->nSatVarMax = 2000; // the max number of SAT variables p->nSatVarMax = 2000; // the max number of SAT variables
p->nCallsRecycle = 200; // calls to perform before recycling SAT solver p->nCallsRecycle = 200; // calls to perform before recycling SAT solver
p->fNonChrono = 0; // use non-chronological backtracling (for circuit SAT only)
p->fPolarFlip = 1; // flops polarity of variables p->fPolarFlip = 1; // flops polarity of variables
p->fCheckMiter = 0; // the circuit is the miter p->fCheckMiter = 0; // the circuit is the miter
p->fFirstStop = 0; // stop on the first sat output p->fFirstStop = 0; // stop on the first sat output
...@@ -399,7 +400,7 @@ p->timeSat += clock() - clk; ...@@ -399,7 +400,7 @@ p->timeSat += clock() - clk;
// if ( p->nAllFailed && !p->nAllProved && !p->nAllDisproved ) // if ( p->nAllFailed && !p->nAllProved && !p->nAllDisproved )
if ( p->nAllFailed > p->nAllProved + p->nAllDisproved ) if ( p->nAllFailed > p->nAllProved + p->nAllDisproved )
{ {
if ( pParsSat->nBTLimit >= 10000 ) if ( pParsSat->nBTLimit >= 10001 )
break; break;
pParsSat->nBTLimit *= 10; pParsSat->nBTLimit *= 10;
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
...@@ -413,7 +414,7 @@ p->timeSat += clock() - clk; ...@@ -413,7 +414,7 @@ p->timeSat += clock() - clk;
} }
} }
} }
if ( pPars->fDualOut && pPars->fColorDiff && Gia_ManAndNum(p->pAig) < 100000 ) if ( pPars->fDualOut && pPars->fColorDiff && (Gia_ManAndNum(p->pAig) < 100000 || p->nAllProved + p->nAllDisproved < 10) )
{ {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Switching into reduced mode.\n" ); printf( "Switching into reduced mode.\n" );
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [External declarations.] Synopsis [External declarations.]
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Detection of structural isomorphism.] Synopsis [Detection of structural isomorphism.]
......
...@@ -4,9 +4,9 @@ ...@@ -4,9 +4,9 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Manager pcocures.] Synopsis [Manager procedures.]
Author [Alan Mishchenko] Author [Alan Mishchenko]
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Simulation pattern manager.] Synopsis [Simulation pattern manager.]
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Refinement of sequential equivalence classes.] Synopsis [Refinement of sequential equivalence classes.]
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Simulation manager.] Synopsis [Simulation manager.]
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [Performs one round of SAT solving.] Synopsis [Performs one round of SAT solving.]
......
/**CFile**************************************************************** /**CFile****************************************************************
FileName [ceFraeep.c] FileName [cecSweep.c]
SystemName [ABC: Logic synthesis and verification system.] SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.] PackageName [Combinational equivalence checking.]
Synopsis [SAT sweeping manager.] Synopsis [SAT sweeping manager.]
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
Date [Ver. 1.0. Started - June 20, 2005.] Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: ceFraeep.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $] Revision [$Id: cecSweep.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/ ***********************************************************************/
......
...@@ -459,8 +459,10 @@ extern Aig_Man_t * Gia_ManToAig( Gia_Man_t * p ); ...@@ -459,8 +459,10 @@ extern Aig_Man_t * Gia_ManToAig( Gia_Man_t * p );
extern Gia_Man_t * Gia_ReadAiger( char * pFileName, int fCheck ); extern Gia_Man_t * Gia_ReadAiger( char * pFileName, int fCheck );
extern void Gia_WriteAiger( Gia_Man_t * p, char * pFileName, int fWriteSymbols, int fCompact ); extern void Gia_WriteAiger( Gia_Man_t * p, char * pFileName, int fWriteSymbols, int fCompact );
extern void Gia_DumpAiger( Gia_Man_t * p, char * pFilePrefix, int iFileNum, int nFileNumDigits ); extern void Gia_DumpAiger( Gia_Man_t * p, char * pFilePrefix, int iFileNum, int nFileNumDigits );
/*=== giaCsatOld.c ============================================================*/
extern Vec_Int_t * Cbs_ManSolveMiter( Gia_Man_t * pGia, int nConfs, Vec_Str_t ** pvStatus, int fVerbose );
/*=== giaCsat.c ============================================================*/ /*=== giaCsat.c ============================================================*/
extern Vec_Int_t * Cbs_ManSolveMiter( Gia_Man_t * pGia, int nConfs, Vec_Str_t ** pvStatus ); extern Vec_Int_t * Cbs_ManSolveMiterNc( Gia_Man_t * pGia, int nConfs, Vec_Str_t ** pvStatus, int fVerbose );
/*=== giaCof.c =============================================================*/ /*=== giaCof.c =============================================================*/
extern void Gia_ManPrintFanio( Gia_Man_t * pGia, int nNodes ); extern void Gia_ManPrintFanio( Gia_Man_t * pGia, int nNodes );
extern Gia_Man_t * Gia_ManDupCof( Gia_Man_t * p, int iVar ); extern Gia_Man_t * Gia_ManDupCof( Gia_Man_t * p, int iVar );
......
...@@ -243,6 +243,7 @@ Gia_Man_t * Gia_ManRetimeForwardOne( Gia_Man_t * p, int * pnRegFixed, int * pnRe ...@@ -243,6 +243,7 @@ Gia_Man_t * Gia_ManRetimeForwardOne( Gia_Man_t * p, int * pnRegFixed, int * pnRe
// finally derive the new manager // finally derive the new manager
pNew = Gia_ManRetimeDupForward( p, vCut ); pNew = Gia_ManRetimeDupForward( p, vCut );
Vec_PtrFree( vCut ); Vec_PtrFree( vCut );
if ( vObjClasses )
Vec_IntFree( vObjClasses ); Vec_IntFree( vObjClasses );
pNew->vFlopClasses = vFlopClasses; pNew->vFlopClasses = vFlopClasses;
return pNew; return pNew;
......
...@@ -405,7 +405,7 @@ int Gia_ManSimSimulate( Gia_Man_t * pAig, Gia_ParSim_t * pPars ) ...@@ -405,7 +405,7 @@ int Gia_ManSimSimulate( Gia_Man_t * pAig, Gia_ParSim_t * pPars )
if ( pPars->fVerbose ) if ( pPars->fVerbose )
{ {
printf( "Frame %4d out of %4d and timeout %3d sec. ", i+1, pPars->nIters, pPars->TimeLimit ); printf( "Frame %4d out of %4d and timeout %3d sec. ", i+1, pPars->nIters, pPars->TimeLimit );
printf( "Time = %7.2f sec\r", (1.0*clock()-clkTotal)/CLOCKS_PER_SEC ); printf( "Time = %7.2f sec\r", (1.0*clock()-clk)/CLOCKS_PER_SEC );
} }
if ( pPars->fCheckMiter && Gia_ManCheckPos( p, &iOut, &iPat ) ) if ( pPars->fCheckMiter && Gia_ManCheckPos( p, &iOut, &iPat ) )
{ {
......
...@@ -2,6 +2,7 @@ SRC += src/aig/gia/gia.c \ ...@@ -2,6 +2,7 @@ SRC += src/aig/gia/gia.c \
src/aig/gia/giaAig.c \ src/aig/gia/giaAig.c \
src/aig/gia/giaAiger.c \ src/aig/gia/giaAiger.c \
src/aig/gia/giaCof.c \ src/aig/gia/giaCof.c \
src/aig/gia/giaCSatOld.c \
src/aig/gia/giaCSat.c \ src/aig/gia/giaCSat.c \
src/aig/gia/giaDfs.c \ src/aig/gia/giaDfs.c \
src/aig/gia/giaDup.c \ src/aig/gia/giaDup.c \
......
...@@ -17681,7 +17681,7 @@ usage: ...@@ -17681,7 +17681,7 @@ usage:
fprintf( pErr, "\t-C num : the max number of conflicts at a node [default = %d]\n", nBTLimit ); fprintf( pErr, "\t-C num : the max number of conflicts at a node [default = %d]\n", nBTLimit );
// fprintf( pErr, "\t-G num : the max number of conflicts globally [default = %d]\n", nBTLimitAll ); // fprintf( pErr, "\t-G num : the max number of conflicts globally [default = %d]\n", nBTLimitAll );
// fprintf( pErr, "\t-D num : the delta in the number of nodes [default = %d]\n", nNodeDelta ); // fprintf( pErr, "\t-D num : the delta in the number of nodes [default = %d]\n", nNodeDelta );
fprintf( pErr, "\t-L num : the limit on fanout count of resets/enables to cofactor [default = %d]\n", nCofFanLit? "yes": "no" ); fprintf( pErr, "\t-L num : the limit on fanout count of resets/enables to cofactor [default = %d]\n", nCofFanLit );
fprintf( pErr, "\t-r : toggle the use of rewriting [default = %s]\n", fRewrite? "yes": "no" ); fprintf( pErr, "\t-r : toggle the use of rewriting [default = %s]\n", fRewrite? "yes": "no" );
// fprintf( pErr, "\t-a : toggle SAT sweeping and SAT solving [default = %s]\n", fNewAlgo? "SAT solving": "SAT sweeping" ); // fprintf( pErr, "\t-a : toggle SAT sweeping and SAT solving [default = %s]\n", fNewAlgo? "SAT solving": "SAT sweeping" );
fprintf( pErr, "\t-v : toggle verbose output [default = %s]\n", fVerbose? "yes": "no" ); fprintf( pErr, "\t-v : toggle verbose output [default = %s]\n", fVerbose? "yes": "no" );
...@@ -23472,7 +23472,7 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -23472,7 +23472,7 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv )
int fCSat = 0; int fCSat = 0;
Cec_ManSatSetDefaultParams( pPars ); Cec_ManSatSetDefaultParams( pPars );
Extra_UtilGetoptReset(); Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "CSNmfcvh" ) ) != EOF ) while ( ( c = Extra_UtilGetopt( argc, argv, "CSNnmfcvh" ) ) != EOF )
{ {
switch ( c ) switch ( c )
{ {
...@@ -23509,6 +23509,9 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -23509,6 +23509,9 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv )
if ( pPars->nCallsRecycle < 0 ) if ( pPars->nCallsRecycle < 0 )
goto usage; goto usage;
break; break;
case 'n':
pPars->fNonChrono ^= 1;
break;
case 'm': case 'm':
pPars->fCheckMiter ^= 1; pPars->fCheckMiter ^= 1;
break; break;
...@@ -23534,7 +23537,10 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -23534,7 +23537,10 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv )
{ {
Vec_Int_t * vCounters; Vec_Int_t * vCounters;
Vec_Str_t * vStatus; Vec_Str_t * vStatus;
vCounters = Cbs_ManSolveMiter( pAbc->pAig, 10*pPars->nBTLimit, &vStatus ); if ( pPars->fNonChrono )
vCounters = Cbs_ManSolveMiterNc( pAbc->pAig, pPars->nBTLimit, &vStatus, pPars->fVerbose );
else
vCounters = Cbs_ManSolveMiter( pAbc->pAig, pPars->nBTLimit, &vStatus, pPars->fVerbose );
Vec_IntFree( vCounters ); Vec_IntFree( vCounters );
Vec_StrFree( vStatus ); Vec_StrFree( vStatus );
} }
...@@ -23546,11 +23552,12 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -23546,11 +23552,12 @@ int Abc_CommandAbc9Sat( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0; return 0;
usage: usage:
fprintf( stdout, "usage: &sat [-CSN <num>] [-mfcvh]\n" ); fprintf( stdout, "usage: &sat [-CSN <num>] [-nmfcvh]\n" );
fprintf( stdout, "\t performs SAT solving for the combinational outputs\n" ); fprintf( stdout, "\t performs SAT solving for the combinational outputs\n" );
fprintf( stdout, "\t-C num : the max number of conflicts at a node [default = %d]\n", pPars->nBTLimit ); fprintf( stdout, "\t-C num : the max number of conflicts at a node [default = %d]\n", pPars->nBTLimit );
fprintf( stdout, "\t-S num : the min number of variables to recycle the solver [default = %d]\n", pPars->nSatVarMax ); fprintf( stdout, "\t-S num : the min number of variables to recycle the solver [default = %d]\n", pPars->nSatVarMax );
fprintf( stdout, "\t-N num : the min number of calls to recycle the solver [default = %d]\n", pPars->nCallsRecycle ); fprintf( stdout, "\t-N num : the min number of calls to recycle the solver [default = %d]\n", pPars->nCallsRecycle );
fprintf( stdout, "\t-n : toggle using non-chronological backtracking [default = %s]\n", pPars->fNonChrono? "yes": "no" );
fprintf( stdout, "\t-m : toggle miter vs. any circuit [default = %s]\n", pPars->fCheckMiter? "yes": "no" ); fprintf( stdout, "\t-m : toggle miter vs. any circuit [default = %s]\n", pPars->fCheckMiter? "yes": "no" );
fprintf( stdout, "\t-f : toggle quitting when one PO is asserted [default = %s]\n", pPars->fFirstStop? "yes": "no" ); fprintf( stdout, "\t-f : toggle quitting when one PO is asserted [default = %s]\n", pPars->fFirstStop? "yes": "no" );
fprintf( stdout, "\t-c : toggle using circuit-based SAT solver [default = %s]\n", fCSat? "yes": "no" ); fprintf( stdout, "\t-c : toggle using circuit-based SAT solver [default = %s]\n", fCSat? "yes": "no" );
......
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