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Commit c6af9094 by Alan Mishchenko
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Changing 'if' to allow for delay optimization on sequential paths only.

parent 38214f01
Showing with 26 additions and 19 deletions
src/aig/gia/giaIf.c
......@@ -70,7 +70,8 @@ void Gia_ManSetIfParsDefault( If_Par_t * pPars )
pPars->fVerbose = 0;
// internal parameters
pPars->fTruth = 0;
pPars->nLatches = 0;
pPars->nLatchesCi = 0;
pPars->nLatchesCo = 0;
pPars->fLiftLeaves = 0;
// pPars->pLutLib = Abc_FrameReadLibLut();
pPars->pLutLib = NULL;
......
src/base/abci/abc.c
......@@ -13499,7 +13499,8 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->pLutStruct = NULL;
// internal parameters
pPars->fTruth = 0;
pPars->nLatches = pNtk? Abc_NtkLatchNum(pNtk) : 0;
pPars->nLatchesCi = pNtk? Abc_NtkLatchNum(pNtk) : 0;
pPars->nLatchesCo = pNtk? Abc_NtkLatchNum(pNtk) : 0;
pPars->fLiftLeaves = 0;
pPars->pLutLib = (If_Lib_t *)Abc_FrameReadLibLut();
pPars->pTimesArr = NULL;
......@@ -13695,7 +13696,7 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
}
*/
if ( pPars->fSeqMap && pPars->nLatches == 0 )
if ( pPars->fSeqMap && (pPars->nLatchesCi == 0 || pPars->nLatchesCo == 0) )
{
Abc_Print( -1, "The network has no latches. Use combinational mapping instead of sequential.\n" );
return 1;
......
src/base/abci/abcRec.c
......@@ -1725,7 +1725,8 @@ void Abc_NtkRecAdd( Abc_Ntk_t * pNtk, int fUseSOPB)
pPars->fUsePerm = 0;
pPars->fDelayOpt = 0;
}
pPars->nLatches = 0;
pPars->nLatchesCi = 0;
pPars->nLatchesCo = 0;
pPars->pLutLib = NULL; // Abc_FrameReadLibLut();
pPars->pTimesArr = NULL;
pPars->pTimesArr = NULL;
......
src/base/abci/abcRenode.c
......@@ -89,7 +89,8 @@ Abc_Ntk_t * Abc_NtkRenode( Abc_Ntk_t * pNtk, int nFaninMax, int nCubeMax, int nF
// internal parameters
pPars->fTruth = 1;
pPars->fUsePerm = 1;
pPars->nLatches = 0;
pPars->nLatchesCi = 0;
pPars->nLatchesCo = 0;
pPars->pLutLib = NULL; // Abc_FrameReadLibLut();
pPars->pTimesArr = NULL;
pPars->pTimesArr = NULL;
......
src/map/if/if.h
......@@ -129,7 +129,8 @@ struct If_Par_t_
int fUseCnfs; // use local CNFs as a cost function
int fUseMv; // use local MV-SOPs as a cost function
int fUseAdders; // timing model for adders
int nLatches; // the number of latches in seq mapping
int nLatchesCi; // the number of latches in seq mapping
int nLatchesCo; // the number of latches in seq mapping
int fLiftLeaves; // shift the leaves for seq mapping
int fUseCoAttrs; // use CO attributes
If_Lib_t * pLutLib; // the LUT library
......@@ -307,8 +308,8 @@ static inline int If_ManObjNum( If_Man_t * p ) { r
static inline If_Obj_t * If_ManConst1( If_Man_t * p ) { return p->pConst1; }
static inline If_Obj_t * If_ManCi( If_Man_t * p, int i ) { return (If_Obj_t *)Vec_PtrEntry( p->vCis, i ); }
static inline If_Obj_t * If_ManCo( If_Man_t * p, int i ) { return (If_Obj_t *)Vec_PtrEntry( p->vCos, i ); }
static inline If_Obj_t * If_ManLi( If_Man_t * p, int i ) { return (If_Obj_t *)Vec_PtrEntry( p->vCos, If_ManCoNum(p) - p->pPars->nLatches + i ); }
static inline If_Obj_t * If_ManLo( If_Man_t * p, int i ) { return (If_Obj_t *)Vec_PtrEntry( p->vCis, If_ManCiNum(p) - p->pPars->nLatches + i ); }
static inline If_Obj_t * If_ManLi( If_Man_t * p, int i ) { return (If_Obj_t *)Vec_PtrEntry( p->vCos, If_ManCoNum(p) - p->pPars->nLatchesCo + i ); }
static inline If_Obj_t * If_ManLo( If_Man_t * p, int i ) { return (If_Obj_t *)Vec_PtrEntry( p->vCis, If_ManCiNum(p) - p->pPars->nLatchesCi + i ); }
static inline If_Obj_t * If_ManObj( If_Man_t * p, int i ) { return (If_Obj_t *)Vec_PtrEntry( p->vObjs, i ); }
static inline int If_ObjIsConst1( If_Obj_t * pObj ) { return pObj->Type == IF_CONST1; }
......@@ -380,15 +381,15 @@ static inline void If_AndClear( If_And_t * pNode ) { *
Vec_PtrForEachEntry( If_Obj_t *, p->vCos, pObj, i )
// iterator over the primary inputs
#define If_ManForEachPi( p, pObj, i ) \
Vec_PtrForEachEntryStop( If_Obj_t *, p->vCis, pObj, i, If_ManCiNum(p) - p->pPars->nLatches )
Vec_PtrForEachEntryStop( If_Obj_t *, p->vCis, pObj, i, If_ManCiNum(p) - p->pPars->nLatchesCi )
// iterator over the primary outputs
#define If_ManForEachPo( p, pObj, i ) \
Vec_PtrForEachEntryStop( If_Obj_t *, p->vCos, pObj, i, If_ManCoNum(p) - p->pPars->nLatches )
Vec_PtrForEachEntryStop( If_Obj_t *, p->vCos, pObj, i, If_ManCoNum(p) - p->pPars->nLatchesCo )
// iterator over the latches
#define If_ManForEachLatchInput( p, pObj, i ) \
Vec_PtrForEachEntryStart( If_Obj_t *, p->vCos, pObj, i, If_ManCoNum(p) - p->pPars->nLatches )
Vec_PtrForEachEntryStart( If_Obj_t *, p->vCos, pObj, i, If_ManCoNum(p) - p->pPars->nLatchesCo )
#define If_ManForEachLatchOutput( p, pObj, i ) \
Vec_PtrForEachEntryStart( If_Obj_t *, p->vCis, pObj, i, If_ManCiNum(p) - p->pPars->nLatches )
Vec_PtrForEachEntryStart( If_Obj_t *, p->vCis, pObj, i, If_ManCiNum(p) - p->pPars->nLatchesCi )
// iterator over all objects in topological order
#define If_ManForEachObj( p, pObj, i ) \
Vec_PtrForEachEntry( If_Obj_t *, p->vObjs, pObj, i )
......
src/map/if/ifSeq.c
......@@ -50,7 +50,7 @@ void If_ManPrepareMappingSeq( If_Man_t * p )
int i;
// link the latch outputs (CIs) directly to the drivers of latch inputs (COs)
for ( i = 0; i < p->pPars->nLatches; i++ )
for ( i = 0; i < p->pPars->nLatchesCi; i++ )
{
pObjLi = If_ManLi( p, i );
pObjLo = If_ManLo( p, i );
......@@ -98,13 +98,13 @@ Vec_Ptr_t * If_ManCollectLatches( If_Man_t * p )
If_Obj_t * pObj;
int i;
// collect latches
vLatches = Vec_PtrAlloc( p->pPars->nLatches );
vLatches = Vec_PtrAlloc( p->pPars->nLatchesCi );
If_ManForEachLatchOutput( p, pObj, i )
If_ManCollectLatches_rec( pObj, vLatches );
// clean marks
Vec_PtrForEachEntry( If_Obj_t *, vLatches, pObj, i )
pObj->fMark = 0;
assert( Vec_PtrSize(vLatches) == p->pPars->nLatches );
assert( Vec_PtrSize(vLatches) == p->pPars->nLatchesCi );
return vLatches;
}
......
src/map/if/ifUtil.c
......@@ -104,7 +104,7 @@ float If_ManDelayMax( If_Man_t * p, int fSeq )
If_Obj_t * pObj;
float DelayBest;
int i;
if ( p->pPars->fLatchPaths && p->pPars->nLatches == 0 )
if ( p->pPars->fLatchPaths && (p->pPars->nLatchesCi == 0 || p->pPars->nLatchesCo == 0) )
{
Abc_Print( 0, "Delay optimization of latch path is not performed because there is no latches.\n" );
p->pPars->fLatchPaths = 0;
......@@ -112,7 +112,7 @@ float If_ManDelayMax( If_Man_t * p, int fSeq )
DelayBest = -IF_FLOAT_LARGE;
if ( fSeq )
{
assert( p->pPars->nLatches > 0 );
assert( p->pPars->nLatchesCi > 0 );
If_ManForEachPo( p, pObj, i )
if ( DelayBest < If_ObjArrTime(If_ObjFanin0(pObj)) )
DelayBest = If_ObjArrTime(If_ObjFanin0(pObj));
......
src/opt/lpk/lpkCore.c
......@@ -68,7 +68,8 @@ void Lpk_IfManStart( Lpk_Man_t * p )
// internal parameters
pPars->fTruth = 1;
pPars->fUsePerm = 0;
pPars->nLatches = 0;
pPars->nLatchesCi = 0;
pPars->nLatchesCo = 0;
pPars->pLutLib = NULL; // Abc_FrameReadLibLut();
pPars->pTimesArr = NULL;
pPars->pTimesArr = NULL;
......
src/opt/nwk/nwkMap.c
......@@ -68,7 +68,8 @@ void Nwk_ManSetIfParsDefault( If_Par_t * pPars )
pPars->fVerbose = 0;
// internal parameters
pPars->fTruth = 0;
pPars->nLatches = 0;
pPars->nLatchesCi = 0;
pPars->nLatchesCo = 0;
pPars->fLiftLeaves = 0;
// pPars->pLutLib = Abc_FrameReadLibLut();
pPars->pLutLib = NULL;
......
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