Improvements to Cba data-structure.

src/base/cba/cba.h

@@ -692,8 +692,12 @@ static inline Cba_Ntk_t * Cba_NtkDupOrder( Cba_Man_t * pMan, Cba_Ntk_t * p, Vec_
 }
 static inline void Cba_NtkDupAttrs( Cba_Ntk_t * pNew, Cba_Ntk_t * p )
 {
-//    Vec_IntRemapArray( &p->vObjCopy, &p->vOrder,    &pNew->vOrder,    Cba_NtkPioOrderNum(pNew) );
-//    Vec_IntRemapArray( &p->vObjCopy, &p->vSeq,      &pNew->vSeq,      Cba_NtkBoxSeqNum(pNew) );
+    int i, iObj;
+    assert( Vec_IntSize(&pNew->vOrder) == 0 );
+    Cba_NtkForEachPioOrder( p, iObj, i )
+        Vec_IntPush( &pNew->vOrder, Cba_ObjCopy(p, iObj) );
+//    Vec_IntRemapArray( &p->vObjCopy, &p->vOrder,    &pNew->vOrder,    Cba_NtkPioOrderNum(p) );
+//    Vec_IntRemapArray( &p->vObjCopy, &p->vSeq,      &pNew->vSeq,      Cba_NtkBoxSeqNum(p) );
     // transfer object attributes
     Vec_IntRemapArray( &p->vObjCopy, &p->vObjFunc,  &pNew->vObjFunc,  Cba_NtkObjNum(pNew) + 1 );
     Vec_IntRemapArray( &p->vObjCopy, &p->vObjName,  &pNew->vObjName,  Cba_NtkObjNum(pNew) + 1 );

src/base/cba/cbaCom.c

@@ -100,7 +100,6 @@ int Cba_CommandRead( Abc_Frame_t * pAbc, int argc, char ** argv )
 {
     FILE * pFile;
     Cba_Man_t * p = NULL;
-    Vec_Ptr_t * vDes = NULL;
     char * pFileName = NULL;
     int c, fUseAbc = 0, fUsePtr = 0, fVerbose  =    0;
     Extra_UtilGetoptReset();
@@ -603,9 +602,8 @@ usage:
 ******************************************************************************/
 int Cba_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
 {
-    extern void Prs_ManReadBlifTest();
-
-    Cba_Man_t * p = Cba_AbcGetMan(pAbc);
+    extern void Prs_ManReadVerilogTest();
+    //Cba_Man_t * p = Cba_AbcGetMan(pAbc);
     int c, fVerbose  = 0;
     Extra_UtilGetoptReset();
     while ( ( c = Extra_UtilGetopt( argc, argv, "vh" ) ) != EOF )
@@ -628,7 +626,7 @@ int Cba_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
         return 0;
     }
 */
-    Prs_ManReadBlifTest();
+    Prs_ManReadVerilogTest();
     return 0;
 usage:
     Abc_Print( -2, "usage: @test [-vh]\n" );

src/base/cba/cbaReadBlif.c

@@ -604,7 +604,7 @@ Cba_Man_t * Prs_ManBuildCbaBlif( char * pFileName, Vec_Ptr_t * vDes )
     // create networks
     Vec_PtrForEachEntry( Prs_Ntk_t *, vDes, pPrsNtk, i )
     {
-        printf( "Elaboration module \"%s\"...\n", Prs_NtkName(pPrsNtk), vDes );
+        printf( "Elaboration module \"%s\"...\n", Prs_NtkName(pPrsNtk) );
         fError = Prs_CreateBlifNtk( Cba_ManNtk(p, i+1), pPrsNtk );
         if ( fError )
             break;

src/base/cba/cbaReadVer.c

@@ -122,6 +122,7 @@ static const char * s_VerilogModules[100] =
 };
 static const char * s_KnownModules[100] = 
 {
+    NULL,
     "VERIFIC_",
     "add_",                  
     "mult_",                 
@@ -189,7 +190,7 @@ static inline int Prs_ManIsVerilogModule( Prs_Man_t * p, char * pName )
 static inline int Prs_ManIsKnownModule( Prs_Man_t * p, char * pName )
 {
     int i;
-    for ( i = 0; s_KnownModules[i]; i++ )
+    for ( i = 1; s_KnownModules[i]; i++ )
         if ( !strncmp(pName, s_KnownModules[i], strlen(s_KnownModules[i])) )
             return i;
     return 0;
@@ -839,7 +840,7 @@ Vec_Ptr_t * Prs_ManReadVerilog( char * pFileName )
         return NULL;
     Prs_NtkAddVerilogDirectives( p );
     Prs_ManReadDesign( p );   
-    //Prs_ManPrintModules( p );
+    Prs_ManPrintModules( p );
     if ( Prs_ManErrorPrint(p) )
         ABC_SWAP( Vec_Ptr_t *, vPrs, p->vNtks );
     Prs_ManFree( p );
@@ -850,15 +851,17 @@ void Prs_ManReadVerilogTest( char * pFileName )
 {
     abctime clk = Abc_Clock();
     extern void Prs_ManWriteVerilog( char * pFileName, Vec_Ptr_t * p );
-    Vec_Ptr_t * vPrs = Prs_ManReadVerilog( "c/hie/dump/1/netlist_1.v" );
+//    Vec_Ptr_t * vPrs = Prs_ManReadVerilog( "c/hie/dump/1/netlist_1.v" );
 //    Vec_Ptr_t * vPrs = Prs_ManReadVerilog( "aga/me/me_wide.v" );
 //    Vec_Ptr_t * vPrs = Prs_ManReadVerilog( "aga/ray/ray_wide.v" );
+    Vec_Ptr_t * vPrs = Prs_ManReadVerilog( "aga/design/r4000/r4000_all_out.v" );
     if ( !vPrs ) return;
     printf( "Finished reading %d networks. ", Vec_PtrSize(vPrs) );
     printf( "NameIDs = %d. ", Abc_NamObjNumMax(Prs_ManNameMan(vPrs)) );
     printf( "Memory = %.2f MB. ", 1.0*Prs_ManMemory(vPrs)/(1<<20) );
     Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
-    Prs_ManWriteVerilog( "c/hie/dump/1/netlist_1_out_new.v", vPrs );
+    Prs_ManWriteVerilog( "aga/design/r4000/r4000_all_out_out.v", vPrs );
+//    Prs_ManWriteVerilog( "c/hie/dump/1/netlist_1_out_new.v", vPrs );
 //    Prs_ManWriteVerilog( "aga/me/me_wide_out.v", vPrs );
 //    Prs_ManWriteVerilog( "aga/ray/ray_wide_out.v", vPrs );
 //    Abc_NamPrint( p->pStrs );

src/base/cba/cbaWriteVer.c

@@ -146,7 +146,7 @@ static void Prs_ManWriteVerilogIoOrder( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t *
 {
     int i, NameId;
     Vec_IntForEachEntry( vOrder, NameId, i )
-        fprintf( pFile, "%s%s", Prs_NtkStr(p, NameId), i == Vec_IntSize(vOrder) - 1 ? "" : ", " );
+        fprintf( pFile, "%s%s", Prs_NtkStr(p, Abc_Lit2Var2(NameId)), i == Vec_IntSize(vOrder) - 1 ? "" : ", " );
 }
 static void Prs_ManWriteVerilogNtk( FILE * pFile, Prs_Ntk_t * p )
 {