Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
A
abc
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
abc
Commits
ae46690b
Commit
ae46690b
authored
Jul 21, 2015
by
Alan Mishchenko
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Renaming Cba into Bac.
parent
6f13e631
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 additions
and
1 deletions
+1
-1
src/base/cba/cbaWriteVer.c
+1
-1
No files found.
src/base/cba/cbaWriteVer.c
View file @
ae46690b
...
...
@@ -64,7 +64,7 @@ static void Prs_ManWriteVerilogSignal( FILE * pFile, Prs_Ntk_t * p, int Sig )
Prs_ManWriteVerilogConcat
(
pFile
,
p
,
Value
);
else
assert
(
0
);
}
static
void
Prs_ManWriteVerilogArray
(
FILE
*
pFile
,
Prs_Ntk_t
*
p
,
Vec_Int_t
*
vSigs
,
int
Start
,
int
Stop
,
int
fOdd
)
void
Prs_ManWriteVerilogArray
(
FILE
*
pFile
,
Prs_Ntk_t
*
p
,
Vec_Int_t
*
vSigs
,
int
Start
,
int
Stop
,
int
fOdd
)
{
int
i
,
Sig
;
assert
(
Vec_IntSize
(
vSigs
)
>
0
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment