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abc
Commit aab0c478 by Alan Mishchenko
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Version abc60909

parent c5c9e37a
Showing with 145 additions and 42 deletions
abc.dsp
...@@ -2050,6 +2050,10 @@ SOURCE=.\src\temp\ivy\ivyFanout.c ...@@ -2050,6 +2050,10 @@ SOURCE=.\src\temp\ivy\ivyFanout.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\temp\ivy\ivyFastMap.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyHaig.c SOURCE=.\src\temp\ivy\ivyHaig.c
# End Source File # End Source File
# Begin Source File # Begin Source File
...@@ -2114,10 +2118,6 @@ SOURCE=.\src\temp\player\playerCore.c ...@@ -2114,10 +2118,6 @@ SOURCE=.\src\temp\player\playerCore.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\temp\player\playerFast.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\player\playerMan.c SOURCE=.\src\temp\player\playerMan.c
# End Source File # End Source File
# Begin Source File # Begin Source File
......
src/base/abc/abcNtk.c
...@@ -705,6 +705,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk ) ...@@ -705,6 +705,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
Vec_PtrFree( pNtk->vCutSet ); Vec_PtrFree( pNtk->vCutSet );
Vec_PtrFree( pNtk->vBoxes ); Vec_PtrFree( pNtk->vBoxes );
Vec_FltFree( pNtk->vSkews ); Vec_FltFree( pNtk->vSkews );
if ( pNtk->vLevelsR ) Vec_IntFree( pNtk->vLevelsR );
if ( pNtk->pModel ) free( pNtk->pModel ); if ( pNtk->pModel ) free( pNtk->pModel );
TotalMemory = 0; TotalMemory = 0;
TotalMemory += pNtk->pMmObj? Extra_MmFixedReadMemUsage(pNtk->pMmObj) : 0; TotalMemory += pNtk->pMmObj? Extra_MmFixedReadMemUsage(pNtk->pMmObj) : 0;
......
src/base/abci/abc.c
...@@ -4736,11 +4736,11 @@ int Abc_CommandXyz( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -4736,11 +4736,11 @@ int Abc_CommandXyz( Abc_Frame_t * pAbc, int argc, char ** argv )
pErr = Abc_FrameReadErr(pAbc); pErr = Abc_FrameReadErr(pAbc);
// set defaults // set defaults
nLutMax = 8; nLutMax = 6;
nPlaMax = 128; nPlaMax = 128;
RankCost = 96000; RankCost = 96000;
fFastMode = 1; fFastMode = 1;
fRewriting = 1; fRewriting = 0;
fSynthesis = 0; fSynthesis = 0;
fVerbose = 1; fVerbose = 1;
Extra_UtilGetoptReset(); Extra_UtilGetoptReset();
...@@ -4811,7 +4811,7 @@ int Abc_CommandXyz( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -4811,7 +4811,7 @@ int Abc_CommandXyz( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1; return 1;
} }
if ( nLutMax < 2 || nLutMax > 8 || nPlaMax < 8 || nPlaMax > 128 ) if ( nLutMax < 2 || nLutMax > 12 || nPlaMax < 8 || nPlaMax > 128 )
{ {
fprintf( pErr, "Incorrect LUT/PLA parameters.\n" ); fprintf( pErr, "Incorrect LUT/PLA parameters.\n" );
return 1; return 1;
...@@ -4819,8 +4819,8 @@ int Abc_CommandXyz( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -4819,8 +4819,8 @@ int Abc_CommandXyz( Abc_Frame_t * pAbc, int argc, char ** argv )
// run the command // run the command
// pNtkRes = Abc_NtkXyz( pNtk, nPlaMax, 1, 0, fInvs, fVerbose ); // pNtkRes = Abc_NtkXyz( pNtk, nPlaMax, 1, 0, fInvs, fVerbose );
// pNtkRes = Abc_NtkPlayer( pNtk, nLutMax, nPlaMax, RankCost, fFastMode, fRewriting, fSynthesis, fVerbose ); pNtkRes = Abc_NtkPlayer( pNtk, nLutMax, nPlaMax, RankCost, fFastMode, fRewriting, fSynthesis, fVerbose );
pNtkRes = NULL; // pNtkRes = NULL;
if ( pNtkRes == NULL ) if ( pNtkRes == NULL )
{ {
fprintf( pErr, "Command has failed.\n" ); fprintf( pErr, "Command has failed.\n" );
...@@ -6495,7 +6495,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -6495,7 +6495,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
} }
// create the new LUT library // create the new LUT library
if ( nLutSize >= 3 && nLutSize <= 6 ) if ( nLutSize >= 3 && nLutSize <= 10 )
Fpga_SetSimpleLutLib( nLutSize ); Fpga_SetSimpleLutLib( nLutSize );
/* /*
else else
...@@ -6560,7 +6560,7 @@ usage: ...@@ -6560,7 +6560,7 @@ usage:
fprintf( pErr, "\t-p : optimizes power by minimizing switching activity [default = %s]\n", fSwitching? "yes": "no" ); fprintf( pErr, "\t-p : optimizes power by minimizing switching activity [default = %s]\n", fSwitching? "yes": "no" );
fprintf( pErr, "\t-l : optimizes latch paths for delay, other paths for area [default = %s]\n", fLatchPaths? "yes": "no" ); fprintf( pErr, "\t-l : optimizes latch paths for delay, other paths for area [default = %s]\n", fLatchPaths? "yes": "no" );
fprintf( pErr, "\t-D float : sets the required time for the mapping [default = %s]\n", Buffer ); fprintf( pErr, "\t-D float : sets the required time for the mapping [default = %s]\n", Buffer );
fprintf( pErr, "\t-K num : the number of LUT inputs [default = %s]%s\n", LutSize, (nLutSize == -1 ? " (type \"print_lut\")" : "") ); fprintf( pErr, "\t-K num : the number of LUT inputs (2 < num < 11) [default = %s]%s\n", LutSize, (nLutSize == -1 ? " (type \"print_lut\")" : "") );
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" ); fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : prints the command usage\n"); fprintf( pErr, "\t-h : prints the command usage\n");
return 1; return 1;
......
src/base/abci/abcFpgaFast.c 0 → 100644
/**CFile****************************************************************
FileName [abcFpgaFast.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Fast FPGA mapper.]
Author [Sungmin Cho]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: abcFpgaFast.c,v 1.00 2006/09/02 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Performs fast FPGA mapping of the network.]
Description [Takes the AIG to be mapped, the LUT size, and verbosity
flag. Produces the new network by fast FPGA mapping of the current
network. If the current network in ABC in not an AIG, the user should
run command "strash" to make sure that the current network into an AIG
before calling this procedure.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkFpgaFast( Abc_Ntk_t * pNtk, int nLutSize, int fVerbose )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj;
int i;
// make sure the network is an AIG
assert( Abc_NtkIsStrash(pNtk) );
// iterate over the nodes in the network
Abc_NtkForEachNode( pNtk, pObj, i )
{
}
// create the new network after mapping
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD );
// here we need to create nodes of the new network
// make sure that the final network passes the test
if ( pNtkNew != NULL && !Abc_NtkCheck( pNtkNew ) )
{
printf( "Abc_NtkFastMap: The network check has failed.\n" );
Abc_NtkDelete( pNtkNew );
return NULL;
}
return pNtkNew;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/base/abci/abcIvy.c
...@@ -383,7 +383,7 @@ Abc_Ntk_t * Abc_NtkIvy( Abc_Ntk_t * pNtk ) ...@@ -383,7 +383,7 @@ Abc_Ntk_t * Abc_NtkIvy( Abc_Ntk_t * pNtk )
// Ivy_ManRequiredLevels( pMan ); // Ivy_ManRequiredLevels( pMan );
// Pla_ManFastLutMap( pMan, 8 ); // Ivy_FastMapPerform( pMan, 8 );
Ivy_ManStop( pMan ); Ivy_ManStop( pMan );
return NULL; return NULL;
......
src/base/abci/abcPrint.c
...@@ -31,6 +31,9 @@ ...@@ -31,6 +31,9 @@
//extern int s_TotalNodes = 0; //extern int s_TotalNodes = 0;
//extern int s_TotalChanges = 0; //extern int s_TotalChanges = 0;
int s_MappingTime = 0;
int s_MappingMem = 0;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS /// /// FUNCTION DEFINITIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
...@@ -141,18 +144,20 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored ) ...@@ -141,18 +144,20 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
} }
*/ */
/*
// print the statistic into a file // print the statistic into a file
{ {
FILE * pTable; FILE * pTable;
pTable = fopen( "fpga_stats.txt", "a+" ); pTable = fopen( "fpga/fpga_stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName ); fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%d ", Abc_NtkGetLevelNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) ); fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%d ", Abc_AigGetLevelNum(pNtk) ); fprintf( pTable, "%.2f ", (float)(s_MappingMem)/(float)(1<<20) );
fprintf( pTable, "%.2f", (float)(s_MappingTime)/(float)(CLOCKS_PER_SEC) );
fprintf( pTable, "\n" ); fprintf( pTable, "\n" );
fclose( pTable ); fclose( pTable );
} }
*/
/* /*
// print the statistic into a file // print the statistic into a file
......
src/base/abci/abcTiming.c
...@@ -646,7 +646,7 @@ void Abc_NtkStartReverseLevels( Abc_Ntk_t * pNtk ) ...@@ -646,7 +646,7 @@ void Abc_NtkStartReverseLevels( Abc_Ntk_t * pNtk )
Vec_Ptr_t * vNodes; Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanout; Abc_Obj_t * pObj, * pFanout;
int i, k, nLevelsCur; int i, k, nLevelsCur;
assert( Abc_NtkIsStrash(pNtk) ); // assert( Abc_NtkIsStrash(pNtk) );
// remember the maximum number of direct levels // remember the maximum number of direct levels
// pNtk->LevelMax = Abc_AigGetLevelNum(pNtk); // pNtk->LevelMax = Abc_AigGetLevelNum(pNtk);
pNtk->LevelMax = Abc_NtkGetLevelNum(pNtk); pNtk->LevelMax = Abc_NtkGetLevelNum(pNtk);
......
src/map/fpga/fpga.c
...@@ -248,18 +248,26 @@ usage: ...@@ -248,18 +248,26 @@ usage:
***********************************************************************/ ***********************************************************************/
void Fpga_SetSimpleLutLib( int nLutSize ) void Fpga_SetSimpleLutLib( int nLutSize )
{ {
Fpga_LutLib_t s_LutLib10= { "lutlib",10, {0,1,1,1,1,1,1,1,1,1,1}, {0,1,1,1,1,1,1,1,1,1,1} };
Fpga_LutLib_t s_LutLib9 = { "lutlib", 9, {0,1,1,1,1,1,1,1,1,1}, {0,1,1,1,1,1,1,1,1,1} };
Fpga_LutLib_t s_LutLib8 = { "lutlib", 8, {0,1,1,1,1,1,1,1,1}, {0,1,1,1,1,1,1,1,1} };
Fpga_LutLib_t s_LutLib7 = { "lutlib", 7, {0,1,1,1,1,1,1,1}, {0,1,1,1,1,1,1,1} };
Fpga_LutLib_t s_LutLib6 = { "lutlib", 6, {0,1,1,1,1,1,1}, {0,1,1,1,1,1,1} }; Fpga_LutLib_t s_LutLib6 = { "lutlib", 6, {0,1,1,1,1,1,1}, {0,1,1,1,1,1,1} };
Fpga_LutLib_t s_LutLib5 = { "lutlib", 5, {0,1,1,1,1,1}, {0,1,1,1,1,1} }; Fpga_LutLib_t s_LutLib5 = { "lutlib", 5, {0,1,1,1,1,1}, {0,1,1,1,1,1} };
Fpga_LutLib_t s_LutLib4 = { "lutlib", 4, {0,1,1,1,1}, {0,1,1,1,1} }; Fpga_LutLib_t s_LutLib4 = { "lutlib", 4, {0,1,1,1,1}, {0,1,1,1,1} };
Fpga_LutLib_t s_LutLib3 = { "lutlib", 3, {0,1,1,1}, {0,1,1,1} }; Fpga_LutLib_t s_LutLib3 = { "lutlib", 3, {0,1,1,1}, {0,1,1,1} };
Fpga_LutLib_t * pLutLib; Fpga_LutLib_t * pLutLib;
assert( nLutSize >= 3 && nLutSize <= 6 ); assert( nLutSize >= 3 && nLutSize <= 10 );
switch ( nLutSize ) switch ( nLutSize )
{ {
case 3: pLutLib = &s_LutLib3; break; case 3: pLutLib = &s_LutLib3; break;
case 4: pLutLib = &s_LutLib4; break; case 4: pLutLib = &s_LutLib4; break;
case 5: pLutLib = &s_LutLib5; break; case 5: pLutLib = &s_LutLib5; break;
case 6: pLutLib = &s_LutLib6; break; case 6: pLutLib = &s_LutLib6; break;
case 7: pLutLib = &s_LutLib7; break;
case 8: pLutLib = &s_LutLib8; break;
case 9: pLutLib = &s_LutLib9; break;
case 10: pLutLib = &s_LutLib10; break;
default: pLutLib = NULL; break; default: pLutLib = NULL; break;
} }
if ( pLutLib == NULL ) if ( pLutLib == NULL )
......
src/map/fpga/fpgaCore.c
...@@ -24,6 +24,10 @@ ...@@ -24,6 +24,10 @@
static int Fpga_MappingPostProcess( Fpga_Man_t * p ); static int Fpga_MappingPostProcess( Fpga_Man_t * p );
extern int s_MappingTime;
extern int s_MappingMem;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS /// /// FUNCTION DEFINITIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
...@@ -70,6 +74,9 @@ int Fpga_Mapping( Fpga_Man_t * p ) ...@@ -70,6 +74,9 @@ int Fpga_Mapping( Fpga_Man_t * p )
p->timeRecover = clock() - clk; p->timeRecover = clock() - clk;
//PRT( "Total mapping time", clock() - clkTotal ); //PRT( "Total mapping time", clock() - clkTotal );
s_MappingTime = clock() - clkTotal;
s_MappingMem = Fpga_CutCountAll(p) * (sizeof(Fpga_Cut_t) - sizeof(int) * (FPGA_MAX_LEAVES - p->nVarsMax));
// print the AI-graph used for mapping // print the AI-graph used for mapping
//Fpga_ManShow( p, "test" ); //Fpga_ManShow( p, "test" );
if ( p->fVerbose ) if ( p->fVerbose )
......
src/map/fpga/fpgaCut.c
...@@ -35,9 +35,11 @@ struct Fpga_CutTableStrutct_t ...@@ -35,9 +35,11 @@ struct Fpga_CutTableStrutct_t
}; };
// the largest number of cuts considered // the largest number of cuts considered
#define FPGA_CUTS_MAX_COMPUTE 500 //#define FPGA_CUTS_MAX_COMPUTE 500
#define FPGA_CUTS_MAX_COMPUTE 2000
// the largest number of cuts used // the largest number of cuts used
#define FPGA_CUTS_MAX_USE 200 //#define FPGA_CUTS_MAX_USE 200
#define FPGA_CUTS_MAX_USE 1000
// primes used to compute the hash key // primes used to compute the hash key
static int s_HashPrimes[10] = { 109, 499, 557, 619, 631, 709, 797, 881, 907, 991 }; static int s_HashPrimes[10] = { 109, 499, 557, 619, 631, 709, 797, 881, 907, 991 };
...@@ -130,7 +132,7 @@ void Fpga_MappingCuts( Fpga_Man_t * p ) ...@@ -130,7 +132,7 @@ void Fpga_MappingCuts( Fpga_Man_t * p )
int nCuts, nNodes, i; int nCuts, nNodes, i;
// set the elementary cuts for the PI variables // set the elementary cuts for the PI variables
assert( p->nVarsMax > 1 && p->nVarsMax < 7 ); assert( p->nVarsMax > 1 && p->nVarsMax < 11 );
Fpga_MappingCreatePiCuts( p ); Fpga_MappingCreatePiCuts( p );
// compute the cuts for the internal nodes // compute the cuts for the internal nodes
...@@ -347,8 +349,8 @@ void Fpga_CutFilter( Fpga_Man_t * p, Fpga_Node_t * pNode ) ...@@ -347,8 +349,8 @@ void Fpga_CutFilter( Fpga_Man_t * p, Fpga_Node_t * pNode )
Fpga_Cut_t * Fpga_CutMergeLists( Fpga_Man_t * p, Fpga_CutTable_t * pTable, Fpga_Cut_t * Fpga_CutMergeLists( Fpga_Man_t * p, Fpga_CutTable_t * pTable,
Fpga_Cut_t * pList1, Fpga_Cut_t * pList2, int fComp1, int fComp2, int fPivot1, int fPivot2 ) Fpga_Cut_t * pList1, Fpga_Cut_t * pList2, int fComp1, int fComp2, int fPivot1, int fPivot2 )
{ {
Fpga_Node_t * ppNodes[6]; Fpga_Node_t * ppNodes[FPGA_MAX_LEAVES];
Fpga_Cut_t * pListNew, ** ppListNew, * pLists[7] = { NULL }; Fpga_Cut_t * pListNew, ** ppListNew, * pLists[FPGA_MAX_LEAVES+1] = { NULL };
Fpga_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2; Fpga_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2;
int nNodes, Counter, i; int nNodes, Counter, i;
Fpga_Cut_t ** ppArray1, ** ppArray2, ** ppArray3; Fpga_Cut_t ** ppArray1, ** ppArray2, ** ppArray3;
...@@ -532,8 +534,8 @@ QUITS : ...@@ -532,8 +534,8 @@ QUITS :
Fpga_Cut_t * Fpga_CutMergeLists2( Fpga_Man_t * p, Fpga_CutTable_t * pTable, Fpga_Cut_t * Fpga_CutMergeLists2( Fpga_Man_t * p, Fpga_CutTable_t * pTable,
Fpga_Cut_t * pList1, Fpga_Cut_t * pList2, int fComp1, int fComp2, int fPivot1, int fPivot2 ) Fpga_Cut_t * pList1, Fpga_Cut_t * pList2, int fComp1, int fComp2, int fPivot1, int fPivot2 )
{ {
Fpga_Node_t * ppNodes[6]; Fpga_Node_t * ppNodes[FPGA_MAX_LEAVES];
Fpga_Cut_t * pListNew, ** ppListNew, * pLists[7] = { NULL }; Fpga_Cut_t * pListNew, ** ppListNew, * pLists[FPGA_MAX_LEAVES+1] = { NULL };
Fpga_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2; Fpga_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2;
int nNodes, Counter, i; int nNodes, Counter, i;
......
src/map/fpga/fpgaInt.h
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
#endif #endif
// the maximum number of cut leaves (currently does not work for 7) // the maximum number of cut leaves (currently does not work for 7)
#define FPGA_MAX_LEAVES 6 #define FPGA_MAX_LEAVES 10
// the bit masks // the bit masks
#define FPGA_MASK(n) ((~((unsigned)0)) >> (32-(n))) #define FPGA_MASK(n) ((~((unsigned)0)) >> (32-(n)))
......
src/temp/ivy/ivy.h
...@@ -425,6 +425,11 @@ extern void Ivy_ObjPatchFanout( Ivy_Man_t * p, Ivy_Obj_t * pObj, Ivy_ ...@@ -425,6 +425,11 @@ extern void Ivy_ObjPatchFanout( Ivy_Man_t * p, Ivy_Obj_t * pObj, Ivy_
extern void Ivy_ObjCollectFanouts( Ivy_Man_t * p, Ivy_Obj_t * pObj, Vec_Ptr_t * vArray ); extern void Ivy_ObjCollectFanouts( Ivy_Man_t * p, Ivy_Obj_t * pObj, Vec_Ptr_t * vArray );
extern Ivy_Obj_t * Ivy_ObjReadFirstFanout( Ivy_Man_t * p, Ivy_Obj_t * pObj ); extern Ivy_Obj_t * Ivy_ObjReadFirstFanout( Ivy_Man_t * p, Ivy_Obj_t * pObj );
extern int Ivy_ObjFanoutNum( Ivy_Man_t * p, Ivy_Obj_t * pObj ); extern int Ivy_ObjFanoutNum( Ivy_Man_t * p, Ivy_Obj_t * pObj );
/*=== ivyFastMap.c =============================================================*/
extern void Ivy_FastMapPerform( Ivy_Man_t * pAig, int nLimit );
extern void Ivy_FastMapStop( Ivy_Man_t * pAig );
extern void Ivy_FastMapReadSupp( Ivy_Man_t * pAig, Ivy_Obj_t * pObj, Vec_Int_t * vLeaves );
extern void Ivy_FastMapReverseLevel( Ivy_Man_t * pAig );
/*=== ivyHaig.c ==========================================================*/ /*=== ivyHaig.c ==========================================================*/
extern void Ivy_ManHaigStart( Ivy_Man_t * p, int fVerbose ); extern void Ivy_ManHaigStart( Ivy_Man_t * p, int fVerbose );
extern void Ivy_ManHaigTrasfer( Ivy_Man_t * p, Ivy_Man_t * pNew ); extern void Ivy_ManHaigTrasfer( Ivy_Man_t * p, Ivy_Man_t * pNew );
......
src/temp/ivy/ivyIsop.c
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
// ISOP computation fails if intermediate memory usage exceed this limit // ISOP computation fails if intermediate memory usage exceed this limit
#define IVY_ISOP_MEM_LIMIT 4096 #define IVY_ISOP_MEM_LIMIT 16*4096
// intermediate ISOP representation // intermediate ISOP representation
typedef struct Ivy_Sop_t_ Ivy_Sop_t; typedef struct Ivy_Sop_t_ Ivy_Sop_t;
......
src/temp/ivy/module.make
...@@ -5,6 +5,7 @@ SRC += src/temp/ivy/ivyBalance.c \ ...@@ -5,6 +5,7 @@ SRC += src/temp/ivy/ivyBalance.c \
src/temp/ivy/ivyDfs.c \ src/temp/ivy/ivyDfs.c \
src/temp/ivy/ivyDsd.c \ src/temp/ivy/ivyDsd.c \
src/temp/ivy/ivyFanout.c \ src/temp/ivy/ivyFanout.c \
src/temp/ivy/ivyFastMap.c \
src/temp/ivy/ivyIsop.c \ src/temp/ivy/ivyIsop.c \
src/temp/ivy/ivyMan.c \ src/temp/ivy/ivyMan.c \
src/temp/ivy/ivyMem.c \ src/temp/ivy/ivyMem.c \
......
src/temp/player/module.make
SRC += src/temp/player/playerToAbc.c \ SRC += src/temp/player/playerToAbc.c \
src/temp/player/playerFast.c \
src/temp/player/playerCore.c \ src/temp/player/playerCore.c \
src/temp/player/playerMan.c \ src/temp/player/playerMan.c \
src/temp/player/playerUtil.c src/temp/player/playerUtil.c
src/temp/player/player.h
...@@ -89,11 +89,6 @@ static inline Pla_Obj_t * Ivy_ObjPlaStr( Ivy_Man_t * p, Ivy_Obj_t * pObj ) { ...@@ -89,11 +89,6 @@ static inline Pla_Obj_t * Ivy_ObjPlaStr( Ivy_Man_t * p, Ivy_Obj_t * pObj ) {
extern void * Abc_NtkPlayer( void * pNtk, int nLutMax, int nPlaMax, int RankCost, int fFastMode, int fRewriting, int fSynthesis, int fVerbose ); extern void * Abc_NtkPlayer( void * pNtk, int nLutMax, int nPlaMax, int RankCost, int fFastMode, int fRewriting, int fSynthesis, int fVerbose );
/*=== playerCore.c =============================================================*/ /*=== playerCore.c =============================================================*/
extern Pla_Man_t * Pla_ManDecompose( Ivy_Man_t * p, int nLutMax, int nPlaMax, int fVerbose ); extern Pla_Man_t * Pla_ManDecompose( Ivy_Man_t * p, int nLutMax, int nPlaMax, int fVerbose );
/*=== playerFast.c =============================================================*/
extern void Pla_ManFastLutMap( Ivy_Man_t * pAig, int nLimit );
extern void Pla_ManFastLutMapStop( Ivy_Man_t * pAig );
extern void Pla_ManFastLutMapReadSupp( Ivy_Man_t * pAig, Ivy_Obj_t * pObj, Vec_Int_t * vLeaves );
extern void Pla_ManFastLutMapReverseLevel( Ivy_Man_t * pAig );
/*=== playerMan.c ==============================================================*/ /*=== playerMan.c ==============================================================*/
extern Pla_Man_t * Pla_ManAlloc( Ivy_Man_t * p, int nLutMax, int nPlaMax ); extern Pla_Man_t * Pla_ManAlloc( Ivy_Man_t * p, int nLutMax, int nPlaMax );
extern void Pla_ManFree( Pla_Man_t * p ); extern void Pla_ManFree( Pla_Man_t * p );
......
src/temp/player/playerToAbc.c
...@@ -88,13 +88,14 @@ void * Abc_NtkPlayer( void * pNtk, int nLutMax, int nPlaMax, int RankCost, int f ...@@ -88,13 +88,14 @@ void * Abc_NtkPlayer( void * pNtk, int nLutMax, int nPlaMax, int RankCost, int f
if ( fFastMode ) if ( fFastMode )
{ {
// perform mapping into LUTs // perform mapping into LUTs
Pla_ManFastLutMap( pMan, nLutMax ); Ivy_FastMapPerform( pMan, nLutMax );
// convert from the extended AIG manager into an SOP network // convert from the extended AIG manager into an SOP network
pNtkNew = Ivy_ManToAbc( pNtk, pMan, NULL, fFastMode ); pNtkNew = Ivy_ManToAbc( pNtk, pMan, NULL, fFastMode );
Pla_ManFastLutMapStop( pMan ); Ivy_FastMapStop( pMan );
} }
else else
{ {
assert( nLutMax >= 2 && nLutMax <= 8 );
// perform decomposition/mapping into PLAs/LUTs // perform decomposition/mapping into PLAs/LUTs
p = Pla_ManDecompose( pMan, nLutMax, nPlaMax, fVerbose ); p = Pla_ManDecompose( pMan, nLutMax, nPlaMax, fVerbose );
// convert from the extended AIG manager into an SOP network // convert from the extended AIG manager into an SOP network
...@@ -109,7 +110,7 @@ void * Abc_NtkPlayer( void * pNtk, int nLutMax, int nPlaMax, int RankCost, int f ...@@ -109,7 +110,7 @@ void * Abc_NtkPlayer( void * pNtk, int nLutMax, int nPlaMax, int RankCost, int f
Abc_NtkDelete( pNtkNew ); Abc_NtkDelete( pNtkNew );
return NULL; return NULL;
} }
Abc_NtkPlayerCost( pNtkNew, RankCost, fVerbose ); // Abc_NtkPlayerCost( pNtkNew, RankCost, fVerbose );
return pNtkNew; return pNtkNew;
} }
...@@ -168,7 +169,7 @@ Abc_Ntk_t * Ivy_ManToAbc( Abc_Ntk_t * pNtk, Ivy_Man_t * pMan, Pla_Man_t * p, int ...@@ -168,7 +169,7 @@ Abc_Ntk_t * Ivy_ManToAbc( Abc_Ntk_t * pNtk, Ivy_Man_t * pMan, Pla_Man_t * p, int
// start the new ABC network // start the new ABC network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_SOP ); pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_SOP );
// transfer the pointers to the basic nodes // transfer the pointers to the basic nodes
Abc_ObjSetIvy2Abc( pMan, Ivy_ManConst1(pMan)->Id, Abc_AigConst1(pNtkNew) ); Abc_ObjSetIvy2Abc( pMan, Ivy_ManConst1(pMan)->Id, Abc_NodeCreateConst1(pNtkNew) );
Abc_NtkForEachCi( pNtkNew, pObjAbc, i ) Abc_NtkForEachCi( pNtkNew, pObjAbc, i )
Abc_ObjSetIvy2Abc( pMan, Ivy_ManPi(pMan, i)->Id, pObjAbc ); Abc_ObjSetIvy2Abc( pMan, Ivy_ManPi(pMan, i)->Id, pObjAbc );
// recursively construct the network // recursively construct the network
...@@ -370,7 +371,7 @@ Abc_Obj_t * Ivy_ManToAbcFast_rec( Abc_Ntk_t * pNtkNew, Ivy_Man_t * pMan, Ivy_Obj ...@@ -370,7 +371,7 @@ Abc_Obj_t * Ivy_ManToAbcFast_rec( Abc_Ntk_t * pNtkNew, Ivy_Man_t * pMan, Ivy_Obj
return pObjAbc; return pObjAbc;
assert( Ivy_ObjIsAnd(pObjIvy) || Ivy_ObjIsExor(pObjIvy) ); assert( Ivy_ObjIsAnd(pObjIvy) || Ivy_ObjIsExor(pObjIvy) );
// get the support of K-LUT // get the support of K-LUT
Pla_ManFastLutMapReadSupp( pMan, pObjIvy, vSupp ); Ivy_FastMapReadSupp( pMan, pObjIvy, vSupp );
// create new ABC node and its fanins // create new ABC node and its fanins
pObjAbc = Abc_NtkCreateNode( pNtkNew ); pObjAbc = Abc_NtkCreateNode( pNtkNew );
Vec_IntForEachEntry( vSupp, Entry, i ) Vec_IntForEachEntry( vSupp, Entry, i )
......
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