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abc
Commit a6086f08 by Alan Mishchenko
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Version abc51203

parent 53c4fffa
Showing with 729 additions and 31 deletions
abc.opt
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abc.rc
# global parameters
set check # checks intermediate networks
#set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
......@@ -68,10 +68,8 @@ alias share "b; ren; fx; b"
alias sharem "b; ren -m; fx; b"
alias sharedsd "b; ren; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resynl "b; rw -l; rwz -l; b; rwz -l; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2l "b; rw -l; rf -l; b; rw -l; rwz -l; b; rfz -l; rwz -l; b"
alias thin "rwz; rfz; b; ps"
alias choice "fraig_store; resynl; fraig_store; resyn2l; fraig_store; fraig_restore"
alias t "r step_opt.blif; b; seq; show_aig; sfpga -v"
alias compress "b; rw -l; rwz -l; b; rwz -l; b"
alias compress2 "b; rw -l; rf -l; b; rw -l; rwz -l; b; rfz -l; rwz -l; b"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
abclib.opt
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abctestlib.dsp 0 → 100644
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abctestlib.dsw 0 → 100644
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abctestlib.opt 0 → 100644
File added
abctestlib.plg 0 → 100644
<html>
<body>
<pre>
<h1>Build Log</h1>
<h3>
--------------------Configuration: abctestlib - Win32 Release--------------------
</h3>
<h3>Command Lines</h3>
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP86.tmp" with contents
[
/nologo /ML /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /Fp"Release/abctestlib.pch" /YX /Fo"Release/" /Fd"Release/" /FD /c
"C:\_projects\abctestlib\demo.c"
]
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP86.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP87.tmp" with contents
[
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib C:\_projects\abc\abclib\abclib_release.lib /nologo /subsystem:console /incremental:no /pdb:"Release/abctestlib.pdb" /machine:I386 /out:"_TEST/abctestlib.exe"
.\Release\demo.obj
]
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP87.tmp"
<h3>Output Window</h3>
Compiling...
demo.c
Linking...
<h3>Results</h3>
abctestlib.exe - 0 error(s), 0 warning(s)
</pre>
</body>
</html>
demo.c 0 → 100644
/**CFile****************************************************************
FileName [demo.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [ABC as a static library.]
Synopsis [A demo program illustrating the use of ABC as a static library.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: demo.c,v 1.00 2005/11/14 00:00:00 alanmi Exp $]
***********************************************************************/
#include <stdio.h>
#include <time.h>
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
// procedures to start and stop the ABC framework
// (should be called before and after the ABC procedures are called)
extern void Abc_Start();
extern void Abc_Stop();
// procedures to get the ABC framework and execute commands in it
extern void * Abc_FrameGetGlobalFrame();
extern int Cmd_CommandExecute( void * pAbc, char * sCommand );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [The main() procedure.]
Description [This procedure compiles into a stand-alone program for
DAG-aware rewriting of the AIGs. A BLIF or PLA file to be considered
for rewriting should be given as a command-line argument. Implementation
of the rewriting is inspired by the paper: Per Bjesse, Arne Boralv,
"DAG-aware circuit compression for formal verification", Proc. ICCAD 2004.]
SideEffects []
SeeAlso []
***********************************************************************/
int main( int argc, char * argv[] )
{
// parameters
int fUseResyn2 = 0;
int fPrintStats = 1;
int fVerify = 1;
// variables
void * pAbc;
char * pFileName;
char Command[1000];
int clkRead, clkResyn, clkVer, clk;
//////////////////////////////////////////////////////////////////////////
// get the input file name
if ( argc != 2 )
{
printf( "Wrong number of command-line arguments.\n" );
return 1;
}
pFileName = argv[1];
//////////////////////////////////////////////////////////////////////////
// start the ABC framework
Abc_Start();
pAbc = Abc_FrameGetGlobalFrame();
clk = clock();
//////////////////////////////////////////////////////////////////////////
// read the file
sprintf( Command, "read %s", pFileName );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
//////////////////////////////////////////////////////////////////////////
// balance
sprintf( Command, "balance" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
clkRead = clock() - clk;
//////////////////////////////////////////////////////////////////////////
// print stats
if ( fPrintStats )
{
sprintf( Command, "print_stats" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
}
clk = clock();
//////////////////////////////////////////////////////////////////////////
// synthesize
if ( fUseResyn2 )
{
sprintf( Command, "balance; rewrite -l; refactor -l; balance; rewrite -l; rewrite -lz; balance; refactor -lz; rewrite -lz; balance" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
}
else
{
sprintf( Command, "balance; rewrite -l; rewrite -lz; balance; rewrite -lz; balance" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
}
clkResyn = clock() - clk;
//////////////////////////////////////////////////////////////////////////
// print stats
if ( fPrintStats )
{
sprintf( Command, "print_stats" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
}
//////////////////////////////////////////////////////////////////////////
// write the result in blif
sprintf( Command, "write_blif result.blif" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
//////////////////////////////////////////////////////////////////////////
// perform verification
clk = clock();
if ( fVerify )
{
sprintf( Command, "cec %s result.blif", pFileName );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return 1;
}
}
clkVer = clock() - clk;
printf( "Reading = %6.2f sec ", (float)(clkRead)/(float)(CLOCKS_PER_SEC) );
printf( "Rewriting = %6.2f sec ", (float)(clkResyn)/(float)(CLOCKS_PER_SEC) );
printf( "Verification = %6.2f sec\n", (float)(clkVer)/(float)(CLOCKS_PER_SEC) );
//////////////////////////////////////////////////////////////////////////
// stop the ABC framework
Abc_Stop();
return 0;
}
examples/ac.v 0 → 100644
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examples/pj1.blif 0 → 100644
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examples/s38584.bench 0 → 100644
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examples/s444.blif 0 → 100644
.model iscas\s444.bench
.inputs G0 G1 G2
.outputs G118 G167 G107 G119 G168 G108
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.end
src/base/abci/abc.c
......@@ -2062,7 +2062,7 @@ int Abc_CommandRewrite( Abc_Frame_t * pAbc, int argc, char ** argv )
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fUpdateLevel = 0;
fUpdateLevel = 1;
fPrecompute = 0;
fUseZeros = 0;
fVerbose = 0;
......@@ -5257,7 +5257,7 @@ int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
pNtkRes = Seq_NtkFpgaMapRetime( pNtkNew, nMaxIters, fVerbose );
if ( pNtkRes == NULL )
{
fprintf( pErr, "Sequential FPGA mapping has failed.\n" );
// fprintf( pErr, "Sequential FPGA mapping has failed.\n" );
Abc_NtkDelete( pNtkNew );
return 0;
}
......@@ -5381,7 +5381,7 @@ int Abc_CommandSeqMap( Abc_Frame_t * pAbc, int argc, char ** argv )
pNtkRes = Seq_MapRetime( pNtkNew, nMaxIters, fVerbose );
if ( pNtkRes == NULL )
{
fprintf( pErr, "Sequential FPGA mapping has failed.\n" );
// fprintf( pErr, "Sequential FPGA mapping has failed.\n" );
Abc_NtkDelete( pNtkNew );
return 0;
}
......
src/base/abci/abcNtbdd.c
......@@ -343,7 +343,7 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode )
{
DdNode * bFunc, * bFunc0, * bFunc1;
assert( !Abc_ObjIsComplement(pNode) );
if ( Cudd_ReadKeys(dd) > 500000 )
if ( Cudd_ReadKeys(dd) > 5000000 )
return NULL;
// if the result is available return
if ( pNode->pCopy )
......
src/base/seq/seqAigIter.c
......@@ -48,7 +48,7 @@ int Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
{
Abc_Seq_t * p = pNtk->pManFunc;
Abc_Obj_t * pNode;
int i, FiMax, FiBest, RetValue, clk, clkIter;
int i, FiMax, RetValue, clk, clkIter;
char NodeLag;
assert( Abc_NtkIsSeq( pNtk ) );
......@@ -68,11 +68,11 @@ int Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
// search for the optimal clock period between 0 and nLevelMax
clk = clock();
FiBest = Seq_RetimeSearch_rec( pNtk, 0, FiMax, fVerbose );
p->FiBestInt = Seq_RetimeSearch_rec( pNtk, 0, FiMax, fVerbose );
clkIter = clock() - clk;
// recompute the best l-values
RetValue = Seq_RetimeForPeriod( pNtk, FiBest, fVerbose );
RetValue = Seq_RetimeForPeriod( pNtk, p->FiBestInt, fVerbose );
assert( RetValue );
// fix the problem with non-converged delays
......@@ -84,13 +84,14 @@ clkIter = clock() - clk;
Vec_StrFill( p->vLags, p->nSize, 0 );
Abc_AigForEachAnd( pNtk, pNode, i )
{
NodeLag = Seq_NodeComputeLag( Seq_NodeGetLValue(pNode), FiBest );
NodeLag = Seq_NodeComputeLag( Seq_NodeGetLValue(pNode), p->FiBestInt );
Seq_NodeSetLag( pNode, NodeLag );
}
// print the result
if ( fVerbose )
printf( "The best clock period is %3d.\n", FiBest );
printf( "The best clock period is %3d.\n", p->FiBestInt );
/*
printf( "lvalues and lags : " );
Abc_AigForEachAnd( pNtk, pNode, i )
......
src/base/seq/seqFpgaCore.c
......@@ -66,7 +66,8 @@ Abc_Ntk_t * Seq_NtkFpgaMapRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fVerbose
return NULL;
if ( RetValue = Abc_NtkGetChoiceNum(pNtk) )
{
printf( "The network has %d choices. Deriving the resulting network is skipped.\n", RetValue );
printf( "The network has %d choices. The resulting network is not derived (this is temporary).\n", RetValue );
printf( "The mininum clock period computed is %d.\n", p->FiBestInt );
return NULL;
}
......
src/base/seq/seqInt.h
......@@ -59,6 +59,8 @@ struct Abc_Seq_t_
float fEpsilon; // the accuracy for delay computation
int fStandCells; // the flag denoting standard cell mapping
int nMaxIters; // the max number of iterations
int FiBestInt; // the best clock period
float FiBestFloat; // the best clock period
// K-feasible cuts
int nVarsMax; // the max cut size
Cut_Man_t * pCutMan; // cut manager
......
src/base/seq/seqMapCore.c
......@@ -78,10 +78,11 @@ Abc_Ntk_t * Seq_MapRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fVerbose )
return NULL;
if ( RetValue = Abc_NtkGetChoiceNum(pNtk) )
{
printf( "The network has %d choices. Deriving the resulting network is skipped.\n", RetValue );
printf( "The network has %d choices. The resulting network is not derived (this is temporary).\n", RetValue );
printf( "The mininum clock period computed is %5.2f.\n", p->FiBestFloat );
return NULL;
}
return NULL;
printf( "The resulting network is derived as BDD logic network (this is temporary).\n" );
// duplicate the nodes contained in multiple cuts
pNtkNew = Seq_NtkMapDup( pNtk );
......
src/base/seq/seqMapIter.c
......@@ -53,7 +53,7 @@ int Seq_MapRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
Abc_Seq_t * p = pNtk->pManFunc;
Cut_Params_t Params, * pParams = &Params;
Abc_Obj_t * pObj;
float TotalArea, FiBest;
float TotalArea;
int i, clk;
// set defaults for cut computation
......@@ -80,8 +80,8 @@ p->timeCuts = clock() - clk;
// compute the delays
clk = clock();
FiBest = Seq_MapRetimeDelayLagsInternal( pNtk, fVerbose );
if ( FiBest == 0.0 )
p->FiBestFloat = Seq_MapRetimeDelayLagsInternal( pNtk, fVerbose );
if ( p->FiBestFloat == 0.0 )
return 0;
p->timeDelay = clock() - clk;
/*
......@@ -89,7 +89,7 @@ p->timeDelay = clock() - clk;
FILE * pTable;
pTable = fopen( "stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%.2f ", FiBest );
fprintf( pTable, "%.2f ", p->FiBestFloat );
fprintf( pTable, "%.2f ", (float)(p->timeCuts)/(float)(CLOCKS_PER_SEC) );
fprintf( pTable, "%.2f ", (float)(p->timeDelay)/(float)(CLOCKS_PER_SEC) );
fprintf( pTable, "\n" );
......@@ -105,7 +105,7 @@ p->timeDelay = clock() - clk;
p->vMapCuts = Vec_VecAlloc( 1000 );
TotalArea = 0.0;
Abc_NtkForEachPo( pNtk, pObj, i )
TotalArea += Seq_MapCollectNode_rec( Abc_ObjChild0(pObj), FiBest, p->vMapAnds, p->vMapCuts );
TotalArea += Seq_MapCollectNode_rec( Abc_ObjChild0(pObj), p->FiBestFloat, p->vMapAnds, p->vMapCuts );
// clean the marks
Abc_NtkForEachObj( pNtk, pObj, i )
......@@ -202,7 +202,7 @@ float Seq_MapRetimeDelayLagsInternal( Abc_Ntk_t * pNtk, int fVerbose )
//printf( "\n\n" );
// print the result
// if ( fVerbose )
if ( fVerbose )
printf( "The best clock period after mapping/retiming is %6.2f.\n", FiBest );
return FiBest;
}
......
src/base/seq/seqRetCore.c
......@@ -62,8 +62,6 @@ Abc_Ntk_t * Seq_NtkRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fInitial, int fV
// find the best mapping and retiming
if ( !Seq_NtkRetimeDelayLags( pNtk, pNtkSeq, fVerbose ) )
return NULL;
return NULL;
// implement the retiming
RetValue = Seq_NtkImplementRetiming( pNtkSeq, p->vLags, fVerbose );
......
src/base/seq/seqRetIter.c
......@@ -53,7 +53,7 @@ int Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
{
Abc_Seq_t * p = pNtk->pManFunc;
Abc_Obj_t * pNode;
float FiMax, FiBest, Delta;
float FiMax, Delta;
int i, RetValue;
char NodeLag;
......@@ -99,10 +99,10 @@ int Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
}
// search for the optimal clock period between 0 and nLevelMax
FiBest = Seq_NtkMappingSearch_rec( pNtk, 0.0, FiMax, Delta, fVerbose );
p->FiBestFloat = Seq_NtkMappingSearch_rec( pNtk, 0.0, FiMax, Delta, fVerbose );
// recompute the best l-values
RetValue = Seq_NtkMappingForPeriod( pNtk, FiBest, fVerbose );
RetValue = Seq_NtkMappingForPeriod( pNtk, p->FiBestFloat, fVerbose );
assert( RetValue );
// fix the problem with non-converged delays
......@@ -127,7 +127,7 @@ int Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
Seq_NodeSetLag( pNode, 0 );
continue;
}
NodeLag = Seq_NodeComputeLagFloat( Seq_NodeGetLValueP(pNode), FiBest );
NodeLag = Seq_NodeComputeLagFloat( Seq_NodeGetLValueP(pNode), p->FiBestFloat );
Seq_NodeRetimeSetLag_rec( pNode, NodeLag );
}
// unmark the nodes
......@@ -136,7 +136,7 @@ int Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
// print the result
if ( fVerbose )
printf( "The best clock period is %6.2f.\n", FiBest );
printf( "The best clock period is %6.2f.\n", p->FiBestFloat );
/*
{
FILE * pTable;
......
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