Version abc80909

abc.dsp

@@ -2010,6 +2010,10 @@ SOURCE=.\src\map\ply\plyAig.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\map\ply\plyFake.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\map\ply\plyInt.h
 # End Source File
 # Begin Source File
@@ -3442,6 +3446,10 @@ SOURCE=.\src\aig\ssw\sswSat.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\aig\ssw\sswSim.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\aig\ssw\sswSimSat.c
 # End Source File
 # Begin Source File

src/aig/aig/aigPartReg.c

@@ -19,7 +19,7 @@
 ***********************************************************************/
 
 #include "aig.h"
-#include "fra.h"
+//#include "fra.h"
 
 ////////////////////////////////////////////////////////////////////////
 ///                        DECLARATIONS                              ///

src/aig/aig/aigPartSat.c

@@ -494,7 +494,7 @@ int Aig_ManPartitionedSat( Aig_Man_t * p, int nAlgo, int nPartSize,
     Aig_Man_t * pAig, * pTemp;
     Vec_Int_t * vNode2Part, * vNode2Var;
     int nConfRemaining = nConfTotal, nNodes = 0;
-    int i, clk, status, RetValue;
+    int i, clk, status, RetValue = -1;
 
     // perform partitioning according to the selected algorithm
     clk = clock();

src/aig/dar/darCore.c

@@ -264,7 +264,7 @@ Aig_MmFixed_t * Dar_ManComputeCuts( Aig_Man_t * pAig, int nCutsMax, int fVerbose
         printf( "Nodes = %6d. Total cuts = %6d. 4-input cuts = %6d.\n",
             Aig_ManObjNum(pAig), nCuts, nCutsK );
         printf( "Cut size = %2d. Truth size = %2d. Total mem = %5.2f Mb  ",
-            sizeof(Dar_Cut_t), (int)4, 1.0*Aig_MmFixedReadMemUsage(p->pMemCuts)/(1<<20) );
+            (int)sizeof(Dar_Cut_t), (int)4, 1.0*Aig_MmFixedReadMemUsage(p->pMemCuts)/(1<<20) );
         PRT( "Runtime", clock() - clk );
 /*
         Aig_ManForEachNode( pAig, pObj, i )

src/aig/fra/fraClass.c

@@ -378,6 +378,7 @@ void Fra_ClassesPrepare( Fra_Cla_t * p, int fLatchCorr, int nMaxLevs )
     free( ppNexts );
     // now it is time to refine the classes
     Fra_ClassesRefine( p );
+//    Fra_ClassesPrint( p, 0 );
 }
 
 /**Function*************************************************************

src/aig/fra/fraInd.c

@@ -568,7 +568,7 @@ p->timeTrav += clock() - clk2;
             Fra_OneHotAssume( p, p->vOneHots );
 //        if ( p->pManAig->vOnehots )
 //            Fra_OneHotAddKnownConstraint( p, p->pManAig->vOnehots );
-
+ 
         // report the intermediate results
         if ( pPars->fVerbose )
         {
@@ -580,7 +580,6 @@ p->timeTrav += clock() - clk2;
             if ( p->pPars->fUse1Hot )
                 printf( "1h = %6d. ", Fra_OneHotCount(p, p->vOneHots) );
             printf( "NR = %6d. ", Aig_ManNodeNum(p->pManFraig) );
-            PRT( "T", clock() - clk3 );
 //            printf( "\n" );
         } 
 
@@ -593,12 +592,13 @@ clk2 = clock();
         Fra_FraigSweep( p );
         if ( pPars->fVerbose )
         {
-//            PRT( "t", clock() - clk2 ); 
+            PRT( "T", clock() - clk3 );
         } 
 
 //        Sat_SolverPrintStats( stdout, p->pSat );
         // remove FRAIG and SAT solver
         Aig_ManStop( p->pManFraig );   p->pManFraig = NULL;
+//        printf( "Vars = %d. Clauses = %d. Learnts = %d.\n", p->pSat->size, p->pSat->clauses.size, p->pSat->learnts.size );
         sat_solver_delete( p->pSat );  p->pSat = NULL; 
         memset( p->pMemFraig, 0, sizeof(Aig_Obj_t *) * p->nSizeAlloc * p->nFramesAll );
 //        printf( "Recent SAT called = %d. Skipped = %d.\n", p->nSatCallsRecent, p->nSatCallsSkipped );

src/aig/fra/fraLcr.c

@@ -629,6 +629,9 @@ clk2 = clock();
 p->timeFraig += clock() - clk2;
             Vec_PtrPush( p->vFraigs, pAigTemp );
             Aig_ManStop( pAigPart );
+
+//intf( "finished part %d (out of %d)\n", i, Vec_PtrSize(p->vParts) );
+
         }
         Fra_ClassNodesUnmark( p );
         // report the intermediate results

src/aig/saig/saigPhase.c

@@ -886,6 +886,11 @@ Aig_Man_t * Saig_ManPhaseAbstractAuto( Aig_Man_t * p, int fVerbose )
     Saig_TsiStop( pTsi );
     if ( pNew == NULL )
         pNew = Aig_ManDupSimple( p );
+    if ( Aig_ManPiNum(pNew) == Aig_ManRegNum(pNew) )
+    {
+        Aig_ManStop( pNew);
+        pNew = Aig_ManDupSimple( p );
+    }
     return pNew;
 }
 

src/aig/ssw/module.make

@@ -4,5 +4,6 @@ SRC +=    src/aig/ssw/sswAig.c \
     src/aig/ssw/sswCore.c \
     src/aig/ssw/sswMan.c \
     src/aig/ssw/sswSat.c \
+    src/aig/ssw/sswSim.c \
     src/aig/ssw/sswSimSat.c \
     src/aig/ssw/sswSweep.c

src/aig/ssw/ssw.h

@@ -54,6 +54,18 @@ struct Ssw_Pars_t_
     int              nIters;        // the number of iterations performed
 };
 
+// sequential counter-example
+typedef struct Ssw_Cex_t_   Ssw_Cex_t;
+struct Ssw_Cex_t_
+{
+    int              iPo;               // the zero-based number of PO, for which verification failed
+    int              iFrame;            // the zero-based number of the time-frame, for which verificaiton failed
+    int              nRegs;             // the number of registers in the miter 
+    int              nPis;              // the number of primary inputs in the miter
+    int              nBits;             // the number of words of bit data used
+    unsigned         pData[0];          // the cex bit data (the number of bits: nRegs + (iFrame+1) * nPis)
+};
+
 ////////////////////////////////////////////////////////////////////////
 ///                      MACRO DEFINITIONS                           ///
 ////////////////////////////////////////////////////////////////////////

src/aig/ssw/sswAig.c

@@ -28,7 +28,6 @@
 ///                     FUNCTION DEFINITIONS                         ///
 ////////////////////////////////////////////////////////////////////////
 
-
 /**Function*************************************************************
 
   Synopsis    [Performs speculative reduction for one node.]

src/aig/ssw/sswClass.c

@@ -335,7 +335,7 @@ void Ssw_ClassesPrint( Ssw_Cla_t * p, int fVeryVerbose )
     Aig_Obj_t * pObj;
     int i;
     printf( "Equivalence classes: Const1 = %5d. Class = %5d. Lit = %5d.\n", 
-        p->nCands1, p->nClasses, p->nLits );
+        p->nCands1, p->nClasses, p->nCands1+p->nLits );
     if ( !fVeryVerbose )
         return;
     printf( "Constants { " );
@@ -368,12 +368,13 @@ void Ssw_ClassesRemoveNode( Ssw_Cla_t * p, Aig_Obj_t * pObj )
     assert( p->pId2Class[pObj->Id] == NULL );
     pRepr = Aig_ObjRepr( p->pAig, pObj );
     assert( pRepr != NULL );
-    Aig_ObjSetRepr( p->pAig, pObj, NULL );
     if ( Ssw_ObjIsConst1Cand( p->pAig, pObj ) )
     {
+        Aig_ObjSetRepr( p->pAig, pObj, NULL );
         p->nCands1--;
         return;
     }
+    Aig_ObjSetRepr( p->pAig, pObj, NULL );
     assert( p->pId2Class[pRepr->Id][0] == pRepr );
     assert( p->pClassSizes[pRepr->Id] >= 2 );
     if ( p->pClassSizes[pRepr->Id] == 2 )
@@ -408,11 +409,26 @@ void Ssw_ClassesRemoveNode( Ssw_Cla_t * p, Aig_Obj_t * pObj )
   SeeAlso     []
 
 ***********************************************************************/
-void Ssw_ClassesPrepare( Ssw_Cla_t * p, int fLatchCorr, int nMaxLevs )
+Ssw_Cla_t * Ssw_ClassesPrepare( Aig_Man_t * pAig, int fLatchCorr, int nMaxLevs )
 {
+    Ssw_Cla_t * p;
+    Ssw_Sml_t * pSml;
     Aig_Obj_t ** ppTable, ** ppNexts, ** ppClassNew;
     Aig_Obj_t * pObj, * pTemp, * pRepr;
     int i, k, nTableSize, nNodes, iEntry, nEntries, nEntries2;
+    int clk;
+
+    // start the classes
+    p = Ssw_ClassesStart( pAig );
+
+    // perform sequential simulation
+clk = clock();
+    pSml = Ssw_SmlSimulateSeq( pAig, 0, 32, 4 );
+PRT( "Simulation of 32 frames with 4 words", clock() - clk );
+
+    // set comparison procedures
+clk = clock();
+    Ssw_ClassesSetData( p, pSml, Ssw_SmlNodeHash, Ssw_SmlNodeIsConst, Ssw_SmlNodesAreEqual );
 
     // allocate the hash table hashing simulation info into nodes
     nTableSize = Aig_PrimeCudd( Aig_ManObjNumMax(p->pAig)/4 );
@@ -430,7 +446,7 @@ void Ssw_ClassesPrepare( Ssw_Cla_t * p, int fLatchCorr, int nMaxLevs )
         }
         else
         {
-            if ( !Aig_ObjIsNode(pObj) && !Saig_ObjIsPi(p->pAig, pObj) )
+            if ( !Aig_ObjIsNode(pObj) && !Aig_ObjIsPi(pObj) )
                 continue;
             // skip the node with more that the given number of levels
             if ( nMaxLevs && (int)pObj->Level > nMaxLevs )
@@ -499,9 +515,14 @@ void Ssw_ClassesPrepare( Ssw_Cla_t * p, int fLatchCorr, int nMaxLevs )
     assert( nEntries == nEntries2 );
     free( ppTable );
     free( ppNexts );
+
     // now it is time to refine the classes
-    Ssw_ClassesRefine( p );
+    Ssw_ClassesRefine( p, 1 );
     Ssw_ClassesCheck( p );
+    Ssw_SmlStop( pSml );
+//    Ssw_ClassesPrint( p, 0 );
+PRT( "Collecting candidate equival classes", clock() - clk );
+    return p;
 }
 
 /**Function*************************************************************
@@ -654,12 +675,12 @@ int Ssw_ClassesRefineOneClass( Ssw_Cla_t * p, Aig_Obj_t * pReprOld, int fRecursi
   SeeAlso     []
 
 ***********************************************************************/
-int Ssw_ClassesRefine( Ssw_Cla_t * p )
+int Ssw_ClassesRefine( Ssw_Cla_t * p, int fRecursive )
 {
     Aig_Obj_t ** ppClass;
     int i, nRefis = 0;
     Ssw_ManForEachClass( p, ppClass, i )
-        nRefis += Ssw_ClassesRefineOneClass( p, ppClass[0], 0 );
+        nRefis += Ssw_ClassesRefineOneClass( p, ppClass[0], fRecursive );
     return nRefis;
 }
 

src/aig/ssw/sswCnf.c

@@ -264,8 +264,8 @@ void Ssw_ObjAddToFrontier( Ssw_Man_t * p, Aig_Obj_t * pObj, Vec_Ptr_t * vFrontie
     assert( Ssw_ObjSatNum(p,pObj) == 0 );
     if ( Aig_ObjIsConst1(pObj) )
         return;
-//    Vec_PtrPush( p->vUsedNodes, pObj );
     Ssw_ObjSetSatNum( p, pObj, p->nSatVars++ );
+    sat_solver_setnvars( p->pSat, 100 * (1 + p->nSatVars / 100) );
     if ( Aig_ObjIsNode(pObj) )
         Vec_PtrPush( vFrontier, pObj );
 }

src/aig/ssw/sswCore.c

@@ -48,8 +48,8 @@ void Ssw_ManSetDefaultParams( Ssw_Pars_t * p )
     p->nConstrs       =     0;  // treat the last nConstrs POs as seq constraints
     p->nBTLimit       =  1000;  // conflict limit at a node
     p->fPolarFlip     =     0;  // uses polarity adjustment
-    p->fLatchCorr     =     1;  // performs register correspondence
-    p->fVerbose       =     1;  // verbose stats
+    p->fLatchCorr     =     0;  // performs register correspondence
+    p->fVerbose       =     0;  // verbose stats
     p->nIters         =     0;  // the number of iterations performed
 }
 
@@ -70,18 +70,40 @@ Aig_Man_t * Ssw_SignalCorrespondence( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
     Ssw_Man_t * p;
     int RetValue, nIter, clk, clkTotal = clock();
     // reset random numbers
-    Aig_ManRandom(1);
+    Aig_ManRandom( 1 );
     // start the choicing manager
     p = Ssw_ManCreate( pAig, pPars );
     // compute candidate equivalence classes
-    p->ppClasses = Ssw_ClassesPrepareSimple( pAig, pPars->fLatchCorr, pPars->nMaxLevs );
+    if ( p->pPars->nConstrs == 0 )
+    {
+        p->ppClasses = Ssw_ClassesPrepare( pAig, pPars->fLatchCorr, pPars->nMaxLevs );
+        p->pSml = Ssw_SmlStart( pAig, 0, p->nFrames + 2, 2 );
+        Ssw_ClassesSetData( p->ppClasses, p->pSml, Ssw_SmlNodeHash, Ssw_SmlNodeIsConst, Ssw_SmlNodesAreEqual );
+    }
+    else
+    {
+        assert( 0 );
+        p->ppClasses = Ssw_ClassesPrepareSimple( pAig, pPars->fLatchCorr, pPars->nMaxLevs );
+    }
+//    Ssw_ClassesSetData( p->ppClasses, NULL, NULL, Ssw_NodeIsConstCex, Ssw_NodesAreEqualCex );
+
+    // get the starting stats
+    p->nLitsBeg  = Ssw_ClassesLitNum( p->ppClasses );
+    p->nNodesBeg = Aig_ManNodeNum(pAig);
+    p->nRegsBeg  = Aig_ManRegNum(pAig);
     // refine classes using BMC
     if ( pPars->fVerbose )
+    {
+        printf( "Before BMC: " );
         Ssw_ClassesPrint( p->ppClasses, 0 );
+    }
     Ssw_ManSweepBmc( p );
     Ssw_ManCleanup( p );
     if ( pPars->fVerbose )
+    {
+        printf( "After  BMC: " );
         Ssw_ClassesPrint( p->ppClasses, 0 );
+    }
     // refine classes using induction
     for ( nIter = 0; ; nIter++ )
     {
@@ -98,10 +120,16 @@ clk = clock();
         if ( !RetValue )
             break;
     } 
+    p->pPars->nIters = nIter + 1;
 p->timeTotal = clock() - clkTotal;
-    Ssw_ManStop( p );
     pAigNew = Aig_ManDupRepr( pAig, 0 );
     Aig_ManSeqCleanup( pAigNew );
+    // get the final stats
+    p->nLitsEnd  = Ssw_ClassesLitNum( p->ppClasses );
+    p->nNodesEnd = Aig_ManNodeNum(pAigNew);
+    p->nRegsEnd  = Aig_ManRegNum(pAigNew);
+    // cleanup
+    Ssw_ManStop( p );
     return pAigNew;
 }
 

src/aig/ssw/sswInt.h

@@ -41,11 +41,10 @@ extern "C" {
 ///                         BASIC TYPES                              ///
 ////////////////////////////////////////////////////////////////////////
 
-// equivalence classes
-typedef struct Ssw_Cla_t_ Ssw_Cla_t;
+typedef struct Ssw_Man_t_ Ssw_Man_t; // signal correspondence manager
+typedef struct Ssw_Cla_t_ Ssw_Cla_t; // equivalence classe manager
+typedef struct Ssw_Sml_t_ Ssw_Sml_t; // sequential simulation manager
 
-// manager
-typedef struct Ssw_Man_t_ Ssw_Man_t;
 struct Ssw_Man_t_
 {
     // parameters
@@ -57,25 +56,38 @@ struct Ssw_Man_t_
     Aig_Obj_t **     pNodeToFraig;   // mapping of AIG nodes into FRAIG nodes
     // equivalence classes
     Ssw_Cla_t *      ppClasses;      // equivalence classes of nodes
-//    Aig_Obj_t **     pReprsProved;   // equivalences proved
     int              fRefined;       // is set to 1 when refinement happens
     // SAT solving
     sat_solver *     pSat;           // recyclable SAT solver
     int              nSatVars;       // the counter of SAT variables
     int *            pSatVars;       // mapping of each node into its SAT var
+    int              nSatVarsTotal;  // the total number of SAT vars created
     Vec_Ptr_t *      vFanins;        // fanins of the CNF node
     Vec_Ptr_t *      vSimRoots;      // the roots of cand const 1 nodes to simulate
     Vec_Ptr_t *      vSimClasses;    // the roots of cand equiv classes to simulate
+    // sequential simulator
+    Ssw_Sml_t *      pSml;
+    // counter example storage
+    int              nPatWords;      // the number of words in the counter example
+    unsigned *       pPatWords;      // the counter example
     // constraints
     int              nConstrTotal;   // the number of total constraints
     int              nConstrReduced; // the number of reduced constraints
-    int              nStragers;
+    int              nStrangers;     // the number of strange situations
     // SAT calls statistics
     int              nSatCalls;      // the number of SAT calls
     int              nSatProof;      // the number of proofs
+    int              nSatFails;      // the number of timeouts
     int              nSatFailsReal;  // the number of timeouts
     int              nSatCallsUnsat; // the number of unsat SAT calls
     int              nSatCallsSat;   // the number of sat SAT calls
+    // node/register/lit statistics
+    int              nLitsBeg;
+    int              nLitsEnd;
+    int              nNodesBeg;
+    int              nNodesEnd;
+    int              nRegsBeg;
+    int              nRegsEnd;
     // runtime stats
     int              timeBmc;        // bounded model checking
     int              timeReduce;     // speculative reduction
@@ -131,12 +143,14 @@ extern Aig_Obj_t **  Ssw_ClassesReadClass( Ssw_Cla_t * p, Aig_Obj_t * pRepr, int
 extern void          Ssw_ClassesCheck( Ssw_Cla_t * p );
 extern void          Ssw_ClassesPrint( Ssw_Cla_t * p, int fVeryVerbose );
 extern void          Ssw_ClassesRemoveNode( Ssw_Cla_t * p, Aig_Obj_t * pObj );
-extern void          Ssw_ClassesPrepare( Ssw_Cla_t * p, int fLatchCorr, int nMaxLevs );
+extern Ssw_Cla_t * Ssw_ClassesPrepare( Aig_Man_t * pAig, int fLatchCorr, int nMaxLevs );
 extern Ssw_Cla_t *   Ssw_ClassesPrepareSimple( Aig_Man_t * pAig, int fLatchCorr, int nMaxLevs );
-extern int           Ssw_ClassesRefine( Ssw_Cla_t * p );
+extern int           Ssw_ClassesRefine( Ssw_Cla_t * p, int fRecursive );
 extern int           Ssw_ClassesRefineOneClass( Ssw_Cla_t * p, Aig_Obj_t * pRepr, int fRecursive );
 extern int           Ssw_ClassesRefineConst1Group( Ssw_Cla_t * p, Vec_Ptr_t * vRoots, int fRecursive );
 extern int           Ssw_ClassesRefineConst1( Ssw_Cla_t * p, int fRecursive );
+extern int           Ssw_NodeIsConstCex( void * p, Aig_Obj_t * pObj );
+extern int           Ssw_NodesAreEqualCex( void * p, Aig_Obj_t * pObj0, Aig_Obj_t * pObj1 );
 /*=== sswCnf.c ===================================================*/
 extern void          Ssw_CnfNodeAddToSolver( Ssw_Man_t * p, Aig_Obj_t * pObj );
 /*=== sswMan.c ===================================================*/
@@ -147,9 +161,19 @@ extern void          Ssw_ManStartSolver( Ssw_Man_t * p );
 /*=== sswSat.c ===================================================*/
 extern int           Ssw_NodesAreEquiv( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew );
 extern int           Ssw_NodesAreConstrained( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew );
+/*=== sswSim.c ===================================================*/
+extern Ssw_Sml_t *   Ssw_SmlStart( Aig_Man_t * pAig, int nPref, int nFrames, int nWordsFrame );
+extern void          Ssw_SmlStop( Ssw_Sml_t * p );
+extern Ssw_Sml_t *   Ssw_SmlSimulateSeq( Aig_Man_t * pAig, int nPref, int nFrames, int nWords );
+extern unsigned      Ssw_SmlNodeHash( Ssw_Sml_t * p, Aig_Obj_t * pObj );
+extern int           Ssw_SmlNodeIsConst( Ssw_Sml_t * p, Aig_Obj_t * pObj );
+extern int           Ssw_SmlNodesAreEqual( Ssw_Sml_t * p, Aig_Obj_t * pObj0, Aig_Obj_t * pObj1 );
+extern void          Ssw_SmlAssignDist1Plus( Ssw_Sml_t * p, unsigned * pPat );
+extern void          Ssw_SmlSimulateOne( Ssw_Sml_t * p );
 /*=== sswSimSat.c ===================================================*/
 extern void          Ssw_ManResimulateCex( Ssw_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pRepr, int f );
 extern void          Ssw_ManResimulateCexTotal( Ssw_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pRepr, int f );
+extern void          Ssw_ManResimulateCexTotalSim( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr, int f );
 /*=== sswSweep.c ===================================================*/
 extern int           Ssw_ManSweepBmc( Ssw_Man_t * p );
 extern int           Ssw_ManSweep( Ssw_Man_t * p );

src/aig/ssw/sswMan.c

@@ -49,18 +49,18 @@ Ssw_Man_t * Ssw_ManCreate( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
     // create interpolation manager
     p = ALLOC( Ssw_Man_t, 1 );
     memset( p, 0, sizeof(Ssw_Man_t) );
-    p->pPars        = pPars;
-    p->pAig         = pAig;
-    p->nFrames      = pPars->nFramesK + 1;
-    p->pNodeToFraig = CALLOC( Aig_Obj_t *, Aig_ManObjNumMax(p->pAig) * p->nFrames );
+    p->pPars         = pPars;
+    p->pAig          = pAig;
+    p->nFrames       = pPars->nFramesK + 1;
+    p->pNodeToFraig  = CALLOC( Aig_Obj_t *, Aig_ManObjNumMax(p->pAig) * p->nFrames );
     // SAT solving
-    p->nSatVars     = 1;
-    p->pSatVars     = CALLOC( int, Aig_ManObjNumMax(p->pAig) * p->nFrames );
-    p->vFanins      = Vec_PtrAlloc( 100 );
-    p->vSimRoots    = Vec_PtrAlloc( 1000 );
-    p->vSimClasses  = Vec_PtrAlloc( 1000 );
-    // equivalences proved
-//    p->pReprsProved = CALLOC( Aig_Obj_t *, Aig_ManObjNumMax(p->pAig) );
+    p->pSatVars      = CALLOC( int, Aig_ManObjNumMax(p->pAig) * p->nFrames );
+    p->vFanins       = Vec_PtrAlloc( 100 );
+    p->vSimRoots     = Vec_PtrAlloc( 1000 );
+    p->vSimClasses   = Vec_PtrAlloc( 1000 );
+    // allocate storage for sim pattern
+    p->nPatWords     = Aig_BitWordNum( Saig_ManPiNum(pAig) * p->nFrames + Saig_ManRegNum(pAig) );
+    p->pPatWords     = ALLOC( unsigned, p->nPatWords ); 
     return p;
 }
 
@@ -80,7 +80,6 @@ int Ssw_ManCountEquivs( Ssw_Man_t * p )
     Aig_Obj_t * pObj;
     int i, nEquivs = 0;
     Aig_ManForEachObj( p->pAig, pObj, i )
-//        nEquivs += ( p->pReprsProved[i] != NULL );
         nEquivs += ( Aig_ObjRepr(p->pAig, pObj) != NULL );
     return nEquivs;
 }
@@ -98,14 +97,19 @@ int Ssw_ManCountEquivs( Ssw_Man_t * p )
 ***********************************************************************/
 void Ssw_ManPrintStats( Ssw_Man_t * p )
 {
-    printf( "Parameters: Frames = %d. Conf limit = %d. Constrs = %d.\n", 
-        p->pPars->nFramesK, p->pPars->nBTLimit, p->pPars->nConstrs );
-    printf( "AIG       : PI = %d. PO = %d. Latch = %d. Node = %d.  SAT vars = %d.\n", 
-        Saig_ManPiNum(p->pAig), Saig_ManPoNum(p->pAig), Saig_ManRegNum(p->pAig), Aig_ManNodeNum(p->pAig), p->nSatVars );
-    printf( "SAT calls : All = %6d. Unsat = %6d. Sat = %6d. Fail = %6d.  Equivs = %d. Str = %d.\n", 
-        p->nSatCalls, p->nSatCalls-p->nSatCallsSat-p->nSatFailsReal, 
-        p->nSatCallsSat, p->nSatFailsReal, Ssw_ManCountEquivs(p), p->nStragers );
-    printf( "Runtime statistics:\n" );
+    double nMemory = 1.0*Aig_ManObjNumMax(p->pAig)*p->nFrames*(2*sizeof(int)+2*sizeof(void*))/(1<<20);
+
+    printf( "Parameters: Frames = %d. Conf limit = %d. Constrs = %d. Max lev = %d. Mem = %0.2f Mb.\n", 
+        p->pPars->nFramesK, p->pPars->nBTLimit, p->pPars->nConstrs, p->pPars->nMaxLevs, nMemory );
+    printf( "AIG       : PI = %d. PO = %d. Latch = %d. Node = %d.  Ave SAT vars = %d.\n", 
+        Saig_ManPiNum(p->pAig), Saig_ManPoNum(p->pAig), Saig_ManRegNum(p->pAig), Aig_ManNodeNum(p->pAig), 
+        p->nSatVarsTotal/p->pPars->nIters );
+    printf( "SAT calls : Proof = %d. Cex = %d. Fail = %d. FailReal = %d.  Equivs = %d. Str = %d.\n", 
+        p->nSatProof, p->nSatCallsSat, p->nSatFails, p->nSatFailsReal, Ssw_ManCountEquivs(p), p->nStrangers );
+    printf( "NBeg = %d. NEnd = %d. (Gain = %6.2f %%).  RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n", 
+        p->nNodesBeg, p->nNodesEnd, 100.0*(p->nNodesBeg-p->nNodesEnd)/(p->nNodesBeg?p->nNodesBeg:1), 
+        p->nRegsBeg, p->nRegsEnd, 100.0*(p->nRegsBeg-p->nRegsEnd)/(p->nRegsBeg?p->nRegsBeg:1) );
+
     p->timeOther = p->timeTotal-p->timeBmc-p->timeReduce-p->timeSimSat-p->timeSat;
     PRTP( "BMC        ", p->timeBmc,      p->timeTotal );
     PRTP( "Spec reduce", p->timeReduce,   p->timeTotal );
@@ -140,9 +144,10 @@ void Ssw_ManCleanup( Ssw_Man_t * p )
     }
     if ( p->pSat )
     {
+//        printf( "Vars = %d. Clauses = %d. Learnts = %d.\n", p->pSat->size, p->pSat->clauses.size, p->pSat->learnts.size );
+        p->nSatVarsTotal += p->pSat->size;
         sat_solver_delete( p->pSat );
         p->pSat = NULL;
-//        p->nSatVars = 0;
         memset( p->pSatVars, 0, sizeof(int) * Aig_ManObjNumMax(p->pAig) * p->nFrames );
     }
     p->nConstrTotal = 0;
@@ -166,12 +171,14 @@ void Ssw_ManStop( Ssw_Man_t * p )
         Ssw_ManPrintStats( p );
     if ( p->ppClasses )
         Ssw_ClassesStop( p->ppClasses );
+    if ( p->pSml )      
+        Ssw_SmlStop( p->pSml );
     Vec_PtrFree( p->vFanins );
     Vec_PtrFree( p->vSimRoots );
     Vec_PtrFree( p->vSimClasses );
     FREE( p->pNodeToFraig );
-//    FREE( p->pReprsProved );
     FREE( p->pSatVars );
+    FREE( p->pPatWords );
     free( p );
 }
 
@@ -191,7 +198,7 @@ void Ssw_ManStartSolver( Ssw_Man_t * p )
     int Lit;
     assert( p->pSat == NULL );
     p->pSat = sat_solver_new();
-    sat_solver_setnvars( p->pSat, 10000 );
+    sat_solver_setnvars( p->pSat, 1000 );
     // var 0 is not used
     // var 1 is reserved for const1 node - add the clause
     p->nSatVars = 1;

src/aig/ssw/sswSat.c

@@ -68,8 +68,11 @@ int Ssw_NodesAreEquiv( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
     }
 //Sat_SolverWriteDimacs( p->pSat, "temp.cnf", pLits, pLits + 2, 1 );
 
-    RetValue = sat_solver_simplify(p->pSat);
-    assert( RetValue != 0 );
+    if ( p->pSat->qtail != p->pSat->qhead )
+    {
+        RetValue = sat_solver_simplify(p->pSat);
+        assert( RetValue != 0 );
+    }
 
 clk = clock();
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 
@@ -114,8 +117,11 @@ p->timeSatUndec += clock() - clk;
         if ( pNew->fPhase )  pLits[1] = lit_neg( pLits[1] );
     }
 
-    RetValue = sat_solver_simplify(p->pSat);
-    assert( RetValue != 0 );
+    if ( p->pSat->qtail != p->pSat->qhead )
+    {
+        RetValue = sat_solver_simplify(p->pSat);
+        assert( RetValue != 0 );
+    }
 
 clk = clock();
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 

src/aig/ssw/sswSimSat.c

@@ -241,7 +241,60 @@ void Ssw_ManResimulateCexTotal( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pR
                      & ( Aig_ObjFanin1(pObj)->fMarkB ^ Aig_ObjFaninC1(pObj) );
     // check equivalence classes
     RetValue1 = Ssw_ClassesRefineConst1( p->ppClasses, 0 );
-    RetValue2 = Ssw_ClassesRefine( p->ppClasses );
+    RetValue2 = Ssw_ClassesRefine( p->ppClasses, 0 );
+    // make sure refinement happened
+    if ( Aig_ObjIsConst1(pRepr) )
+        assert( RetValue1 );
+    else
+        assert( RetValue2 );
+p->timeSimSat += clock() - clk;
+}
+
+
+/**Function*************************************************************
+
+  Synopsis    [Copy pattern from the solver into the internal storage.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ssw_SmlSavePatternAig( Ssw_Man_t * p, int f )
+{
+    Aig_Obj_t * pObj;
+    int i;
+    memset( p->pPatWords, 0, sizeof(unsigned) * p->nPatWords );
+    Aig_ManForEachPi( p->pAig, pObj, i )
+        if ( Ssw_ManOriginalPiValue( p, pObj, f ) )
+            Aig_InfoSetBit( p->pPatWords, i );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Handle the counter-example.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ssw_ManResimulateCexTotalSim( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr, int f )
+{
+    int RetValue1, RetValue2, clk = clock();
+    // save the counter-example
+    Ssw_SmlSavePatternAig( p, f );
+    // set the PI simulation information
+    Ssw_SmlAssignDist1Plus( p->pSml, p->pPatWords );
+    // simulate internal nodes
+    Ssw_SmlSimulateOne( p->pSml );
+    // check equivalence classes
+    RetValue1 = Ssw_ClassesRefineConst1( p->ppClasses, 1 );
+    RetValue2 = Ssw_ClassesRefine( p->ppClasses, 1 );
     // make sure refinement happened
     if ( Aig_ObjIsConst1(pRepr) )
         assert( RetValue1 );

src/aig/ssw/sswSweep.c

@@ -74,16 +74,12 @@ void Ssw_ManSweepNode( Ssw_Man_t * p, Aig_Obj_t * pObj, int f )
                 p->pSat->model.ptr[iVar] = (int)(p->pPars->fPolarFlip? 0 : (pObj->fPhase? l_True : l_False));
                 p->pSat->model.size = p->pSat->size;
             }
-        p->nStragers++;
+        p->nStrangers++;
         return;
     }
     // if the fraiged nodes are the same, return
     if ( Aig_Regular(pObjFraig) == Aig_Regular(pObjReprFraig) )
-    {
-        // remember the proved equivalence
-//        p->pReprsProved[ pObj->Id ] = pObjRepr;
         return;
-    }
 //    assert( Aig_Regular(pObjFraig) != Aig_ManConst1(p->pFrames) );
     if ( Aig_Regular(pObjFraig) != Aig_ManConst1(p->pFrames) )
         RetValue = Ssw_NodesAreEquiv( p, Aig_Regular(pObjReprFraig), Aig_Regular(pObjFraig) );
@@ -92,7 +88,7 @@ void Ssw_ManSweepNode( Ssw_Man_t * p, Aig_Obj_t * pObj, int f )
 
     if ( RetValue == -1 ) // timed out
     {
-        assert( 0 );
+//        assert( 0 );
         Ssw_ClassesRemoveNode( p->ppClasses, pObj );
         p->fRefined = 1;
         return;
@@ -101,13 +97,12 @@ void Ssw_ManSweepNode( Ssw_Man_t * p, Aig_Obj_t * pObj, int f )
     {
         pObjFraig2 = Aig_NotCond( pObjReprFraig, pObj->fPhase ^ pObjRepr->fPhase );
         Ssw_ObjSetFraig( p, pObj, f, pObjFraig2 );
-        // remember the proved equivalence
-//        p->pReprsProved[ pObj->Id ] = pObjRepr;
         return;
     }
     // disproved the equivalence
 //    Ssw_ManResimulateCex( p, pObj, pObjRepr, f );
-    Ssw_ManResimulateCexTotal( p, pObj, pObjRepr, f );
+//    Ssw_ManResimulateCexTotal( p, pObj, pObjRepr, f );
+    Ssw_ManResimulateCexTotalSim( p, pObj, pObjRepr, f );
     assert( Aig_ObjRepr( p->pAig, pObj ) != pObjRepr );
     p->fRefined = 1;
 }
@@ -126,7 +121,7 @@ void Ssw_ManSweepNode( Ssw_Man_t * p, Aig_Obj_t * pObj, int f )
 int Ssw_ManSweepBmc( Ssw_Man_t * p )
 {
     Bar_Progress_t * pProgress = NULL;
-    Aig_Obj_t * pObj, * pObjNew;
+    Aig_Obj_t * pObj, * pObjNew, * pObjLi, * pObjLo;
     int i, f, clk;
 clk = clock();
 
@@ -154,6 +149,12 @@ clk = clock();
             Ssw_ObjSetFraig( p, pObj, f, pObjNew );
             Ssw_ManSweepNode( p, pObj, f );
         }
+        // quit if this is the last timeframe
+        if ( f == p->pPars->nFramesK - 1 )
+            break;
+        // transfer latch input to the latch outputs 
+        Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
+            Ssw_ObjSetFraig( p, pObjLo, f+1, Ssw_ObjChild0Fra(p, pObjLi,f) );
     }
     if ( p->pPars->fVerbose )
         Bar_ProgressStop( pProgress );
@@ -223,7 +224,7 @@ p->timeReduce += clock() - clk;
         if ( Saig_ObjIsLo(p->pAig, pObj) )
             Ssw_ManSweepNode( p, pObj, f );
         else if ( Aig_ObjIsNode(pObj) )
-        {
+        { 
             pObjNew = Aig_And( p->pFrames, Ssw_ObjChild0Fra(p, pObj, f), Ssw_ObjChild1Fra(p, pObj, f) );
             Ssw_ObjSetFraig( p, pObj, f, pObjNew );
             Ssw_ManSweepNode( p, pObj, f );

src/base/abci/abc.c

@@ -7681,7 +7681,7 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
 {
     FILE * pOut, * pErr;
     Abc_Ntk_t * pNtk;
-//    Abc_Ntk_t * pNtkRes;
+    Abc_Ntk_t * pNtkRes;
     int c;
     int fBmc;
     int nFrames;
@@ -7700,7 +7700,7 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
     extern Abc_Ntk_t * Abc_NtkDarToCnf( Abc_Ntk_t * pNtk, char * pFileName );
     extern Abc_Ntk_t * Abc_NtkFilter( Abc_Ntk_t * pNtk );
 //    extern Abc_Ntk_t * Abc_NtkDarRetime( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose );
-//    extern Abc_Ntk_t * Abc_NtkPcmTest( Abc_Ntk_t * pNtk, int fVerbose );
+    extern Abc_Ntk_t * Abc_NtkPcmTest( Abc_Ntk_t * pNtk, int fVerbose );
     extern Abc_Ntk_t * Abc_NtkDarHaigRecord( Abc_Ntk_t * pNtk, int nIters, int nSteps, int fRetimingOnly, int fAddBugs, int fUseCnf, int fVerbose );
 //    extern void Abc_NtkDarTestBlif( char * pFileName );
 //    extern Abc_Ntk_t * Abc_NtkDarPartition( Abc_Ntk_t * pNtk );
@@ -7869,9 +7869,10 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
 */
 
 
-/*
+
 //    pNtkRes = Abc_NtkDar( pNtk );
-//    pNtkRes = Abc_NtkDarRetime( pNtk, nLevels, 1 );
+//    pNtkRes = Abc_NtkDarRetime( pNtk, nLevels, 1 ); 
+//    pNtkRes = Abc_NtkPcmTestAig( pNtk, fVerbose );
     pNtkRes = Abc_NtkPcmTest( pNtk, fVerbose );
 //    pNtkRes = NULL;
     if ( pNtkRes == NULL )
@@ -7882,7 +7883,7 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
     // replace the current network
     Abc_FrameReplaceCurrentNetwork( pAbc, pNtkRes );
     return 0;
-*/
+
 
 
 //    Abc_NtkDarClau( pNtk, nFrames, nLevels, fBmc, fVerbose, fVeryVerbose );

src/base/abci/abcDar.c

@@ -119,6 +119,7 @@ Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters )
     Abc_NtkForEachCo( pNtk, pObj, i )
         Aig_ObjCreatePo( pMan, (Aig_Obj_t *)Abc_ObjChild0Copy(pObj) );
     // complement the 1-valued registers
+    Aig_ManSetRegNum( pMan, Abc_NtkLatchNum(pNtk) );
     if ( fRegisters )
         Aig_ManForEachLiSeq( pMan, pObjNew, i )
             if ( Abc_LatchIsInit1(Abc_ObjFanout0(Abc_NtkCo(pNtk,i))) )

src/map/mio/mio.c

@@ -206,6 +206,9 @@ int Mio_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
 usage:
     fprintf( pErr, "usage: read_library [-vh]\n");
     fprintf( pErr, "\t         read the library from a genlib file\n" );  
+    fprintf( pErr, "\t         (if the library contains more than one gate\n" );  
+    fprintf( pErr, "\t         with the same Boolean function, only the first gate\n" );  
+    fprintf( pErr, "\t         in the order of their appearance in the file is used)\n" );  
     fprintf( pErr, "\t-h     : enable verbose output\n");
     return 1;       /* error exit */
 }