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Commit 6c4252c5 by Alan Mishchenko
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Integrated buffering and sizing.

parent 55872bc3
Showing with 32 additions and 26 deletions
src/map/scl/scl.c
......@@ -709,8 +709,8 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtkRes, * pNtk = Abc_FrameReadNtk(pAbc);
int c;
memset( pPars, 0, sizeof(SC_BusPars) );
pPars->GainRatio = 150;
pPars->Slew = 300;
pPars->GainRatio = 200;
pPars->Slew = 80;
pPars->nDegree = 4;
pPars->fSizeOnly = 0;
pPars->fAddBufs = 0;
......@@ -719,7 +719,7 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->fVerbose = 0;
pPars->fVeryVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "GSNsbpcvwh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "GSDsbpcvwh" ) ) != EOF )
{
switch ( c )
{
......@@ -745,7 +745,7 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
if ( pPars->Slew < 0 )
goto usage;
break;
case 'N':
case 'D':
if ( globalUtilOptind >= argc )
{
Abc_Print( -1, "Command line switch \"-N\" should be followed by a positive integer.\n" );
......@@ -808,11 +808,11 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
fprintf( pAbc->Err, "usage: bufsize [-GSM num] [-sbpcvwh]\n" );
fprintf( pAbc->Err, "usage: bufsize [-GSD num] [-sbpcvwh]\n" );
fprintf( pAbc->Err, "\t performs buffering and sizing and mapped network\n" );
fprintf( pAbc->Err, "\t-G <num> : target gain percentage [default = %d]\n", pPars->GainRatio );
fprintf( pAbc->Err, "\t-S <num> : target slew in pisoseconds [default = %d]\n", pPars->Slew );
fprintf( pAbc->Err, "\t-M <num> : the maximum fanout degree [default = %d]\n", pPars->nDegree );
fprintf( pAbc->Err, "\t-D <num> : the maximum fanout degree [default = %d]\n", pPars->nDegree );
fprintf( pAbc->Err, "\t-s : toggle performing only sizing [default = %s]\n", pPars->fSizeOnly? "yes": "no" );
fprintf( pAbc->Err, "\t-b : toggle using buffers instead of inverters [default = %s]\n", pPars->fAddBufs? "yes": "no" );
fprintf( pAbc->Err, "\t-p : toggle buffering primary inputs [default = %s]\n", pPars->fBufPis? "yes": "no" );
......
src/map/scl/sclBuffer.c
......@@ -201,7 +201,7 @@ Abc_Ntk_t * Abc_SclBufferPhase( Abc_Ntk_t * pNtk, int fVerbose )
Vec_Int_t * vInvs;
Abc_Obj_t * pObj, * pFanin, * pFaninNew;
int nNodesOld = Abc_NtkObjNumMax(pNtk);
int i, k, Counter = 0, Total = 0;
int i, k, Counter = 0, Counter2 = 0, Total = 0;
assert( pNtk->vPhases != NULL );
vInvs = Vec_IntStart( Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNodeCo( pNtk, pObj, i )
......@@ -213,7 +213,7 @@ Abc_Ntk_t * Abc_SclBufferPhase( Abc_Ntk_t * pNtk, int fVerbose )
Total++;
if ( !Abc_ObjFaninPhase(pObj, k) )
continue;
if ( Vec_IntEntry(vInvs, Abc_ObjId(pFanin)) == 0 )
if ( Vec_IntEntry(vInvs, Abc_ObjId(pFanin)) == 0 || Abc_ObjIsCi(pFanin) ) // allow PIs to have high fanout - to be fixed later
{
pFaninNew = Abc_NtkCreateNodeInv( pNtk, pFanin );
Vec_IntWriteEntry( vInvs, Abc_ObjId(pFanin), Abc_ObjId(pFaninNew) );
......@@ -221,10 +221,12 @@ Abc_Ntk_t * Abc_SclBufferPhase( Abc_Ntk_t * pNtk, int fVerbose )
}
pFaninNew = Abc_NtkObj( pNtk, Vec_IntEntry(vInvs, Abc_ObjId(pFanin)) );
Abc_ObjPatchFanin( pObj, pFanin, pFaninNew );
Counter2++;
}
}
if ( fVerbose )
printf( "Added %d (%.2f %%) inverters.\n", Counter, 100.0 * Counter / Total );
printf( "Added %d inverters (%.2f %% fanins) (%.2f %% compl fanins).\n",
Counter, 100.0 * Counter / Total, 100.0 * Counter2 / Total );
Vec_IntFree( vInvs );
Vec_IntFillExtra( pNtk->vPhases, Abc_NtkObjNumMax(pNtk), 0 );
// duplicate network in topo order
......@@ -319,9 +321,10 @@ void Abc_NodeInvUpdateFanPolarity( Abc_Obj_t * pObj )
{
Abc_Obj_t * pFanout;
int i;
assert( Abc_SclObjIsBufInv(pObj) );
assert( Abc_ObjFaninNum(pObj) == 0 || Abc_SclObjIsBufInv(pObj) );
Abc_ObjForEachFanout( pObj, pFanout, i )
{
assert( Abc_ObjFaninNum(pFanout) > 0 );
if ( Abc_SclObjIsBufInv(pFanout) )
Abc_NodeInvUpdateFanPolarity( pFanout );
else
......
src/map/scl/sclLib.c
......@@ -822,7 +822,7 @@ void Abc_SclLinkCells( SC_Lib * p )
SC_Cell * Abc_SclFindInvertor( SC_Lib * p, int fFindBuff )
{
SC_Cell * pCell = NULL;
word Truth = fFindBuff ? ABC_CONST(0x5555555555555555) : ABC_CONST(0xAAAAAAAAAAAAAAAA);
word Truth = fFindBuff ? ABC_CONST(0xAAAAAAAAAAAAAAAA) : ABC_CONST(0x5555555555555555);
int k;
SC_LibForEachCellClass( p, pCell, k )
if ( pCell->n_inputs == 1 && Vec_WrdEntry(SC_CellPin(pCell, 1)->vFunc, 0) == Truth )
......
src/map/scl/sclLib.h
......@@ -564,17 +564,17 @@ static inline SC_Timing * Scl_CellPinTime( SC_Cell * pCell, int iPin )
assert( Vec_PtrSize(pRTime->vTimings) == 1 );
return (SC_Timing *)Vec_PtrEntry( pRTime->vTimings, 0 );
}
static inline float Scl_LibPinArrivalEstimate( SC_Cell * pCell, int iPin, float Slew, float load )
static inline float Scl_LibPinArrivalEstimate( SC_Cell * pCell, int iPin, float Slew, float Load )
{
SC_Pair Load = { load, load };
SC_Pair LoadIn = { Load, Load };
SC_Pair ArrIn = { 0.0, 0.0 };
SC_Pair ArrOut = { 0.0, 0.0 };
SC_Pair SlewIn = { 0.0, 0.0 };
SC_Pair SlewOut = { 0.0, 0.0 };
SC_Timing * pTime = Scl_CellPinTime( pCell, iPin );
// Vec_Flt_t * vIndex0 = pTime->pCellRise->vIndex0; // slew
SlewIn.fall = SlewIn.rise = Slew; //Vec_FltEntry( vIndex0, Vec_FltSize(vIndex0)/2 );
Scl_LibPinArrival( pTime, &ArrIn, &SlewIn, &Load, &ArrOut, &SlewOut );
// SlewIn.fall = SlewIn.rise = Vec_FltEntry( vIndex0, Vec_FltSize(vIndex0)/2 );
SlewIn.fall = SlewIn.rise = Slew;
Scl_LibPinArrival( Scl_CellPinTime(pCell, iPin), &ArrIn, &SlewIn, &LoadIn, &ArrOut, &SlewOut );
return 0.5 * ArrOut.fall + 0.5 * ArrOut.rise;
}
......
src/map/scl/sclLoad.c
......@@ -79,14 +79,15 @@ Vec_Flt_t * Abc_SclFindWireCaps( SC_WireLoad * pWL )
SeeAlso []
***********************************************************************/
float Abc_SclFindWireLoad( Vec_Flt_t * vWireCaps, Abc_Obj_t * pObj )
float Abc_SclFindWireLoad( Vec_Flt_t * vWireCaps, int nFans )
{
int nFans = Abc_MinInt( Vec_FltSize(vWireCaps)-1, Abc_ObjFanoutNum(pObj) );
return vWireCaps ? Vec_FltEntry(vWireCaps, nFans) : 0;
if ( vWireCaps == NULL )
return 0;
return Vec_FltEntry( vWireCaps, Abc_MinInt(nFans, Vec_FltSize(vWireCaps)-1) );
}
void Abc_SclAddWireLoad( SC_Man * p, Abc_Obj_t * pObj, int fSubtr )
{
float Load = Abc_SclFindWireLoad( p->vWireCaps, pObj );
float Load = Abc_SclFindWireLoad( p->vWireCaps, Abc_ObjFanoutNum(pObj) );
Abc_SclObjLoad(p, pObj)->rise += fSubtr ? -Load : Load;
Abc_SclObjLoad(p, pObj)->fall += fSubtr ? -Load : Load;
}
......
src/map/scl/sclSize.h
......@@ -509,7 +509,7 @@ extern Abc_Ntk_t * Abc_SclBufPerform( Abc_Ntk_t * pNtk, int FanMin, int FanMax
extern void Abc_SclDnsizePerform( SC_Lib * pLib, Abc_Ntk_t * pNtk, SC_SizePars * pPars );
/*=== sclLoad.c ===============================================================*/
extern Vec_Flt_t * Abc_SclFindWireCaps( SC_WireLoad * pWL );
extern float Abc_SclFindWireLoad( Vec_Flt_t * vWireCaps, Abc_Obj_t * pObj );
extern float Abc_SclFindWireLoad( Vec_Flt_t * vWireCaps, int nFans );
extern void Abc_SclAddWireLoad( SC_Man * p, Abc_Obj_t * pObj, int fSubtr );
extern void Abc_SclComputeLoad( SC_Man * p );
extern void Abc_SclUpdateLoad( SC_Man * p, Abc_Obj_t * pObj, SC_Cell * pOld, SC_Cell * pNew );
......
src/map/scl/sclUpsize.c
......@@ -360,7 +360,7 @@ int Abc_SclFindBypasses( SC_Man * p, Vec_Int_t * vPathNodes, int Ratio, int Notc
{
if ( Abc_SclIsInv(pBuf) )
{
if ( !Abc_ObjIsNode(pFanin) || !Abc_SclIsInv(pFanin) )
if ( !Abc_SclIsInv(pFanin) )
continue;
pFanin = Abc_ObjFanin0(pFanin);
if ( !Abc_ObjIsNode(pFanin) )
......@@ -425,7 +425,7 @@ int Abc_SclFindBypasses( SC_Man * p, Vec_Int_t * vPathNodes, int Ratio, int Notc
Vec_IntFree( vEvals );
if ( Vec_QueSize(p->vNodeByGain) == 0 )
return 0;
if ( fVeryVerbose )
if ( fVeryVerbose )
printf( "\n" );
// accept changes for that are half above the average and do not overlap
......@@ -438,12 +438,14 @@ int Abc_SclFindBypasses( SC_Man * p, Vec_Int_t * vPathNodes, int Ratio, int Notc
pFanout = Abc_NtkObj( p->pNtk, Vec_IntEntry(p->vBestFans, iNode) );
pBuf = Abc_NtkObj( p->pNtk, iNode );
pFanin = Abc_ObjFanin0(pBuf);
if ( pFanout->fMarkB || pBuf->fMarkB )
continue;
if ( p->pNtk->vPhases == NULL )
{
// update fanin
if ( Abc_SclIsInv(pBuf) )
{
if ( !Abc_ObjIsNode(pFanin) || !Abc_SclIsInv(pFanin) )
if ( !Abc_SclIsInv(pFanin) )
{
assert( 0 );
continue;
......@@ -456,7 +458,7 @@ int Abc_SclFindBypasses( SC_Man * p, Vec_Int_t * vPathNodes, int Ratio, int Notc
}
}
}
if ( pFanout->fMarkB || pBuf->fMarkB || pFanin->fMarkB )
if ( pFanin->fMarkB )
continue;
pFanout->fMarkB = 1;
pBuf->fMarkB = 1;
......@@ -930,7 +932,7 @@ void Abc_SclUpsizePerform( SC_Lib * pLib, Abc_Ntk_t * pNtk, SC_SizePars * pPars
clk = Abc_Clock();
if ( pPars->fUseDept )
{
if ( Vec_IntSize(p->vChanged) )
if ( Vec_IntSize(p->vChanged) && pPars->BypassFreq == 0 )
nConeSize = Abc_SclTimeIncUpdate( p );
else
Abc_SclTimeNtkRecompute( p, NULL, NULL, pPars->fUseDept, 0 );
......
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