Bug fix in incremental timing.

src/map/scl/sclSize.c

@@ -132,14 +132,14 @@ void Abc_SclTimeNtkPrint( SC_Man * p, int fShowAll, int fPrintPath )
     float maxDelay = Abc_SclObjTimePs(p, pPivot, fRise);
     p->ReportDelay = maxDelay;
 
-    printf( "WireLoad model = \"%s\"   ", p->pWLoadUsed ? p->pWLoadUsed->pName : "none" );
-    printf( "Gates = %6d   ",             Abc_NtkNodeNum(p->pNtk) );
-    printf( "Cave = %5.1f   ",            p->EstLoadAve );
-    printf( "Min = %5.1f %%   ",          100.0 * Abc_SclCountMinSize(p->pLib, p->pNtk, 0) / Abc_NtkNodeNum(p->pNtk) );
-    printf( "Area = %12.2f   ",           Abc_SclGetTotalArea(p->pNtk) );
-    printf( "Delay = %8.2f ps  ",         maxDelay );
-    printf( "Min = %5.1f %%  ",           100.0 * Abc_SclCountNearCriticalNodes(p) / Abc_NtkNodeNum(p->pNtk) );
-    printf( "                        \n" );
+    printf( "WireLoad model = \"%s\"  ", p->pWLoadUsed ? p->pWLoadUsed->pName : "none" );
+    printf( "Gates = %6d   ",            Abc_NtkNodeNum(p->pNtk) );
+    printf( "Cave = %5.1f ff   ",        p->EstLoadAve );
+    printf( "Area = %12.2f ",            Abc_SclGetTotalArea(p->pNtk) );
+    printf( "(%5.1f %%)   ",             100.0 * Abc_SclCountMinSize(p->pLib, p->pNtk, 0) / Abc_NtkNodeNum(p->pNtk) );
+    printf( "Delay = %8.2f ps  ",        maxDelay );
+    printf( "(%5.1f %%)   ",             100.0 * Abc_SclCountNearCriticalNodes(p) / Abc_NtkNodeNum(p->pNtk) );
+    printf( "                            \n" );
     if ( fShowAll )
     {
 //        printf( "Timing information for all nodes: \n" );
@@ -453,9 +453,9 @@ int Abc_SclTimeIncUpdate( SC_Man * p )
 //    Abc_SclTimeIncCheckLevel( p->pNtk );
     Abc_NtkForEachObjVec( p->vChanged, p->pNtk, pObj, i )
     {
+        Abc_SclTimeIncAddFanins( p, pObj );
         if ( pObj->fMarkC )
             continue;
-        Abc_SclTimeIncAddFanins( p, pObj );
         Abc_SclTimeIncAddNode( p, pObj );
     }
     Vec_IntClear( p->vChanged );

src/map/scl/sclUpsize.c

@@ -425,6 +425,8 @@ int Abc_SclFindBypasses( SC_Man * p, Vec_Int_t * vPathNodes, int Ratio, int Notc
     Vec_IntFree( vEvals );
     if ( Vec_QueSize(p->vNodeByGain) == 0 )
         return 0;
+    if ( fVeryVerbose )
+        printf( "\n" );
 
     // accept changes for that are half above the average and do not overlap
     Counter = 0;
@@ -500,9 +502,13 @@ int Abc_SclFindBypasses( SC_Man * p, Vec_Int_t * vPathNodes, int Ratio, int Notc
             Abc_NodeInvUpdateObjFanoutPolarity( pFanin, pFanout );
         // report
         if ( fVeryVerbose )
-            printf( "Node %6d  Redir fanout %6d to fanin %6d.  Gain = %7.1f ps.   Replacing gate %12s by gate %12s.\n", 
-                Abc_ObjId(pBuf), Abc_ObjId(pFanout), Abc_ObjId(pFanin), 
-                Vec_FltEntry(p->vNode2Gain, iNode), pCellOld->pName, pCellNew->pName );
+        {
+            printf( "Node %6d  Redir fanout %6d to fanin %6d.  Gain = %7.1f ps. ", 
+                Abc_ObjId(pBuf), Abc_ObjId(pFanout), Abc_ObjId(pFanin), Vec_FltEntry(p->vNode2Gain, iNode) );
+            printf( "Gate %12s (%2d/%2d)  -> %12s (%2d/%2d) \n", 
+                pCellOld->pName, pCellOld->Order, pCellOld->nGates, 
+                pCellNew->pName, pCellNew->Order, pCellNew->nGates );
+        }
 /*
         // check if the node became useless
         if ( Abc_ObjFanoutNum(pBuf) == 0 )