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abc
Commit 369f008e by Alan Mishchenko
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Version abc71130

parent 765a2124
Showing with 1148 additions and 31 deletions
abc.dsp
...@@ -2622,6 +2622,10 @@ SOURCE=.\src\aig\fra\fraClass.c ...@@ -2622,6 +2622,10 @@ SOURCE=.\src\aig\fra\fraClass.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\fra\fraClau.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\fra\fraCnf.c SOURCE=.\src\aig\fra\fraCnf.c
# End Source File # End Source File
# Begin Source File # Begin Source File
...@@ -2830,6 +2834,14 @@ SOURCE=.\src\aig\aig\aigFanout.c ...@@ -2830,6 +2834,14 @@ SOURCE=.\src\aig\aig\aigFanout.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\aig\aigFrames.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\aig\aigHaig.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\aig\aigMan.c SOURCE=.\src\aig\aig\aigMan.c
# End Source File # End Source File
# Begin Source File # Begin Source File
...@@ -2866,6 +2878,10 @@ SOURCE=.\src\aig\aig\aigRet.c ...@@ -2866,6 +2878,10 @@ SOURCE=.\src\aig\aig\aigRet.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\aig\aigRetF.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\aig\aigScl.c SOURCE=.\src\aig\aig\aigScl.c
# End Source File # End Source File
# Begin Source File # Begin Source File
......
abc.rc
...@@ -52,6 +52,7 @@ alias rh read_hie ...@@ -52,6 +52,7 @@ alias rh read_hie
alias rl read_blif alias rl read_blif
alias rb read_bench alias rb read_bench
alias ret retime alias ret retime
alias dret dretime
alias rp read_pla alias rp read_pla
alias rt read_truth alias rt read_truth
alias rv read_verilog alias rv read_verilog
...@@ -121,4 +122,7 @@ alias trec "rec_start; r c.blif; st; rec_add; rec_use" ...@@ -121,4 +122,7 @@ alias trec "rec_start; r c.blif; st; rec_add; rec_use"
alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use" alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use"
alias bmc2 "frames -i -F 10; orpos; iprove" alias bmc2 "frames -i -F 10; orpos; iprove"
alias t0 "r test/mc1.blif; st; test"
alias t1 "r s27mc2.blif; st; test"
alias t2 "r i/intel_001.aig; ps; test"
src/aig/aig/aig.h
...@@ -71,6 +71,7 @@ struct Aig_Obj_t_ // 8 words ...@@ -71,6 +71,7 @@ struct Aig_Obj_t_ // 8 words
Aig_Obj_t * pNext; // strashing table Aig_Obj_t * pNext; // strashing table
Aig_Obj_t * pFanin0; // fanin Aig_Obj_t * pFanin0; // fanin
Aig_Obj_t * pFanin1; // fanin Aig_Obj_t * pFanin1; // fanin
Aig_Obj_t * pHaig; // pointer to the HAIG node
unsigned int Type : 3; // object type unsigned int Type : 3; // object type
unsigned int fPhase : 1; // value under 000...0 pattern unsigned int fPhase : 1; // value under 000...0 pattern
unsigned int fMarkA : 1; // multipurpose mask unsigned int fMarkA : 1; // multipurpose mask
...@@ -140,6 +141,7 @@ struct Aig_Man_t_ ...@@ -140,6 +141,7 @@ struct Aig_Man_t_
Vec_Ptr_t * vMapped; Vec_Ptr_t * vMapped;
Vec_Int_t * vFlopNums; Vec_Int_t * vFlopNums;
void * pSeqModel; void * pSeqModel;
Aig_Man_t * pManHaig;
// timing statistics // timing statistics
int time1; int time1;
int time2; int time2;
...@@ -251,11 +253,14 @@ static inline Aig_Obj_t * Aig_ObjChild0( Aig_Obj_t * pObj ) { return pObj- ...@@ -251,11 +253,14 @@ static inline Aig_Obj_t * Aig_ObjChild0( Aig_Obj_t * pObj ) { return pObj-
static inline Aig_Obj_t * Aig_ObjChild1( Aig_Obj_t * pObj ) { return pObj->pFanin1; } static inline Aig_Obj_t * Aig_ObjChild1( Aig_Obj_t * pObj ) { return pObj->pFanin1; }
static inline Aig_Obj_t * Aig_ObjChild0Copy( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin0(pObj)? Aig_NotCond((Aig_Obj_t *)Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj)) : NULL; } static inline Aig_Obj_t * Aig_ObjChild0Copy( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin0(pObj)? Aig_NotCond((Aig_Obj_t *)Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj)) : NULL; }
static inline Aig_Obj_t * Aig_ObjChild1Copy( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin1(pObj)? Aig_NotCond((Aig_Obj_t *)Aig_ObjFanin1(pObj)->pData, Aig_ObjFaninC1(pObj)) : NULL; } static inline Aig_Obj_t * Aig_ObjChild1Copy( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin1(pObj)? Aig_NotCond((Aig_Obj_t *)Aig_ObjFanin1(pObj)->pData, Aig_ObjFaninC1(pObj)) : NULL; }
static inline void Aig_ObjChild0Flip( Aig_Obj_t * pObj ) { pObj->pFanin0 = Aig_Not(pObj->pFanin0); }
static inline void Aig_ObjChild1Flip( Aig_Obj_t * pObj ) { pObj->pFanin1 = Aig_Not(pObj->pFanin1); }
static inline int Aig_ObjLevel( Aig_Obj_t * pObj ) { return pObj->Level; } static inline int Aig_ObjLevel( Aig_Obj_t * pObj ) { return pObj->Level; }
static inline int Aig_ObjLevelNew( Aig_Obj_t * pObj ) { return Aig_ObjFanin1(pObj)? 1 + Aig_ObjIsExor(pObj) + AIG_MAX(Aig_ObjFanin0(pObj)->Level, Aig_ObjFanin1(pObj)->Level) : Aig_ObjFanin0(pObj)->Level; } static inline int Aig_ObjLevelNew( Aig_Obj_t * pObj ) { return Aig_ObjFanin1(pObj)? 1 + Aig_ObjIsExor(pObj) + AIG_MAX(Aig_ObjFanin0(pObj)->Level, Aig_ObjFanin1(pObj)->Level) : Aig_ObjFanin0(pObj)->Level; }
static inline void Aig_ObjClean( Aig_Obj_t * pObj ) { memset( pObj, 0, sizeof(Aig_Obj_t) ); } static inline void Aig_ObjClean( Aig_Obj_t * pObj ) { memset( pObj, 0, sizeof(Aig_Obj_t) ); }
static inline Aig_Obj_t * Aig_ObjFanout0( Aig_Man_t * p, Aig_Obj_t * pObj ) { assert(p->pFanData && pObj->Id < p->nFansAlloc); return Aig_ManObj(p, p->pFanData[5*pObj->Id] >> 1); } static inline Aig_Obj_t * Aig_ObjFanout0( Aig_Man_t * p, Aig_Obj_t * pObj ) { assert(p->pFanData && pObj->Id < p->nFansAlloc); return Aig_ManObj(p, p->pFanData[5*pObj->Id] >> 1); }
static inline Aig_Obj_t * Aig_ObjEquiv( Aig_Man_t * p, Aig_Obj_t * pObj ) { return p->pEquivs? p->pEquivs[pObj->Id] : NULL; } static inline Aig_Obj_t * Aig_ObjEquiv( Aig_Man_t * p, Aig_Obj_t * pObj ) { return p->pEquivs? p->pEquivs[pObj->Id] : NULL; }
static inline Aig_Obj_t * Aig_ObjHaig( Aig_Obj_t * pObj ) { assert( Aig_Regular(pObj)->pHaig ); return Aig_NotCond( Aig_Regular(pObj)->pHaig, Aig_IsComplement(pObj) ); }
static inline int Aig_ObjWhatFanin( Aig_Obj_t * pObj, Aig_Obj_t * pFanin ) static inline int Aig_ObjWhatFanin( Aig_Obj_t * pObj, Aig_Obj_t * pFanin )
{ {
if ( Aig_ObjFanin0(pObj) == pFanin ) return 0; if ( Aig_ObjFanin0(pObj) == pFanin ) return 0;
...@@ -398,6 +403,10 @@ extern void Aig_ObjAddFanout( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Ob ...@@ -398,6 +403,10 @@ extern void Aig_ObjAddFanout( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Ob
extern void Aig_ObjRemoveFanout( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFanout ); extern void Aig_ObjRemoveFanout( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFanout );
extern void Aig_ManFanoutStart( Aig_Man_t * p ); extern void Aig_ManFanoutStart( Aig_Man_t * p );
extern void Aig_ManFanoutStop( Aig_Man_t * p ); extern void Aig_ManFanoutStop( Aig_Man_t * p );
/*=== aigFrames.c ==========================================================*/
extern Aig_Man_t * Aig_ManFrames( Aig_Man_t * pAig, int nFs, int fInit, int fOuts, int fRegs, Aig_Obj_t *** ppObjMap );
/*=== aigHaig.c ==========================================================*/
extern void Aig_ManHaigRecord( Aig_Man_t * p );
/*=== aigMan.c ==========================================================*/ /*=== aigMan.c ==========================================================*/
extern Aig_Man_t * Aig_ManStart( int nNodesMax ); extern Aig_Man_t * Aig_ManStart( int nNodesMax );
extern Aig_Man_t * Aig_ManStartFrom( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManStartFrom( Aig_Man_t * p );
...@@ -463,6 +472,8 @@ extern Aig_Man_t * Aig_ManRehash( Aig_Man_t * p ); ...@@ -463,6 +472,8 @@ extern Aig_Man_t * Aig_ManRehash( Aig_Man_t * p );
extern void Aig_ManMarkValidChoices( Aig_Man_t * p ); extern void Aig_ManMarkValidChoices( Aig_Man_t * p );
/*=== aigRet.c ========================================================*/ /*=== aigRet.c ========================================================*/
extern Aig_Man_t * Rtm_ManRetime( Aig_Man_t * p, int fForward, int nStepsMax, int fVerbose ); extern Aig_Man_t * Rtm_ManRetime( Aig_Man_t * p, int fForward, int nStepsMax, int fVerbose );
/*=== aigRetF.c ========================================================*/
extern Aig_Man_t * Aig_ManRetimeFrontier( Aig_Man_t * p, int nStepsMax );
/*=== aigScl.c ==========================================================*/ /*=== aigScl.c ==========================================================*/
extern Aig_Man_t * Aig_ManRemap( Aig_Man_t * p, Vec_Ptr_t * vMap ); extern Aig_Man_t * Aig_ManRemap( Aig_Man_t * p, Vec_Ptr_t * vMap );
extern int Aig_ManSeqCleanup( Aig_Man_t * p ); extern int Aig_ManSeqCleanup( Aig_Man_t * p );
...@@ -479,6 +490,7 @@ extern void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj ); ...@@ -479,6 +490,7 @@ extern void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj );
extern void Aig_TableDelete( Aig_Man_t * p, Aig_Obj_t * pObj ); extern void Aig_TableDelete( Aig_Man_t * p, Aig_Obj_t * pObj );
extern int Aig_TableCountEntries( Aig_Man_t * p ); extern int Aig_TableCountEntries( Aig_Man_t * p );
extern void Aig_TableProfile( Aig_Man_t * p ); extern void Aig_TableProfile( Aig_Man_t * p );
extern void Aig_TableClear( Aig_Man_t * p );
/*=== aigTiming.c ========================================================*/ /*=== aigTiming.c ========================================================*/
extern void Aig_ObjClearReverseLevel( Aig_Man_t * p, Aig_Obj_t * pObj ); extern void Aig_ObjClearReverseLevel( Aig_Man_t * p, Aig_Obj_t * pObj );
extern int Aig_ObjRequiredLevel( Aig_Man_t * p, Aig_Obj_t * pObj ); extern int Aig_ObjRequiredLevel( Aig_Man_t * p, Aig_Obj_t * pObj );
......
src/aig/aig/aigFrames.c 0 → 100644
/**CFile****************************************************************
FileName [aigFrames.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [AIG package.]
Synopsis [Performs timeframe expansion of the AIG.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - April 28, 2007.]
Revision [$Id: aigFrames.c,v 1.00 2007/04/28 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static inline Aig_Obj_t * Aig_ObjFrames( Aig_Obj_t ** pObjMap, int nFs, Aig_Obj_t * pObj, int i ) { return pObjMap[nFs*pObj->Id + i]; }
static inline void Aig_ObjSetFrames( Aig_Obj_t ** pObjMap, int nFs, Aig_Obj_t * pObj, int i, Aig_Obj_t * pNode ) { pObjMap[nFs*pObj->Id + i] = pNode; }
static inline Aig_Obj_t * Aig_ObjChild0Frames( Aig_Obj_t ** pObjMap, int nFs, Aig_Obj_t * pObj, int i ) { return Aig_ObjFanin0(pObj)? Aig_NotCond(Aig_ObjFrames(pObjMap,nFs,Aig_ObjFanin0(pObj),i), Aig_ObjFaninC0(pObj)) : NULL; }
static inline Aig_Obj_t * Aig_ObjChild1Frames( Aig_Obj_t ** pObjMap, int nFs, Aig_Obj_t * pObj, int i ) { return Aig_ObjFanin1(pObj)? Aig_NotCond(Aig_ObjFrames(pObjMap,nFs,Aig_ObjFanin1(pObj),i), Aig_ObjFaninC1(pObj)) : NULL; }
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Performs timeframe expansion of the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManFrames( Aig_Man_t * pAig, int nFs, int fInit, int fOuts, int fRegs, Aig_Obj_t *** ppObjMap )
{
Aig_Man_t * pFrames;
Aig_Obj_t * pObj, * pObjLi, * pObjLo, * pObjNew;
Aig_Obj_t ** pObjMap;
int i, f;
// create mapping for the frames nodes
pObjMap = ALLOC( Aig_Obj_t *, nFs * Aig_ManObjNumMax(pAig) );
memset( pObjMap, 0, sizeof(Aig_Obj_t *) * nFs * Aig_ManObjNumMax(pAig) );
// start the fraig package
pFrames = Aig_ManStart( Aig_ManObjNumMax(pAig) * nFs );
pFrames->pName = Aig_UtilStrsav( pAig->pName );
// map constant nodes
for ( f = 0; f < nFs; f++ )
Aig_ObjSetFrames( pObjMap, nFs, Aig_ManConst1(pAig), f, Aig_ManConst1(pFrames) );
// create PI nodes for the frames
for ( f = 0; f < nFs; f++ )
Aig_ManForEachPiSeq( pAig, pObj, i )
Aig_ObjSetFrames( pObjMap, nFs, pObj, f, Aig_ObjCreatePi(pFrames) );
// set initial state for the latches
if ( fInit )
{
Aig_ManForEachLoSeq( pAig, pObj, i )
Aig_ObjSetFrames( pObjMap, nFs, pObj, 0, Aig_ManConst0(pFrames) );
}
else
{
Aig_ManForEachLoSeq( pAig, pObj, i )
Aig_ObjSetFrames( pObjMap, nFs, pObj, 0, Aig_ObjCreatePi(pFrames) );
}
// add timeframes
for ( f = 0; f < nFs; f++ )
{
// printf( "Frame = %d.\n", f );
// add internal nodes of this frame
Aig_ManForEachNode( pAig, pObj, i )
{
// Aig_Obj_t * pFanin0 = Aig_ObjChild0Frames(pObjMap,nFs,pObj,f);
// Aig_Obj_t * pFanin1 = Aig_ObjChild1Frames(pObjMap,nFs,pObj,f);
// printf( "Node = %3d. Fanin0 = %3d. Fanin1 = %3d.\n", pObj->Id, Aig_Regular(pFanin0)->Id, Aig_Regular(pFanin1)->Id );
pObjNew = Aig_And( pFrames, Aig_ObjChild0Frames(pObjMap,nFs,pObj,f), Aig_ObjChild1Frames(pObjMap,nFs,pObj,f) );
Aig_ObjSetFrames( pObjMap, nFs, pObj, f, pObjNew );
}
// set the latch inputs and copy them into the latch outputs of the next frame
Aig_ManForEachLiLoSeq( pAig, pObjLi, pObjLo, i )
{
pObjNew = Aig_ObjChild0Frames(pObjMap,nFs,pObjLi,f);
if ( f < nFs - 1 )
Aig_ObjSetFrames( pObjMap, nFs, pObjLo, f+1, pObjNew );
}
}
if ( fOuts )
{
for ( f = 0; f < nFs; f++ )
Aig_ManForEachPoSeq( pAig, pObj, i )
{
pObjNew = Aig_ObjCreatePo( pFrames, Aig_ObjChild0Frames(pObjMap,nFs,pObj,f) );
Aig_ObjSetFrames( pObjMap, nFs, pObj, f, pObjNew );
}
}
if ( fRegs )
{
pFrames->nRegs = pAig->nRegs;
Aig_ManForEachLiSeq( pAig, pObj, i )
{
pObjNew = Aig_ObjCreatePo( pFrames, Aig_ObjChild0Frames(pObjMap,nFs,pObj,nFs-1) );
Aig_ObjSetFrames( pObjMap, nFs, pObj, nFs-1, pObjNew );
}
}
Aig_ManCleanup( pFrames );
// return the new manager
if ( ppObjMap )
*ppObjMap = pObjMap;
else
free( pObjMap );
return pFrames;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/aig/aig/aigMan.c
...@@ -115,7 +115,14 @@ Aig_Obj_t * Aig_ManDup_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj ) ...@@ -115,7 +115,14 @@ Aig_Obj_t * Aig_ManDup_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj )
if ( Aig_ObjIsBuf(pObj) ) if ( Aig_ObjIsBuf(pObj) )
return pObj->pData = Aig_ObjChild0Copy(pObj); return pObj->pData = Aig_ObjChild0Copy(pObj);
Aig_ManDup_rec( pNew, p, Aig_ObjFanin1(pObj) ); Aig_ManDup_rec( pNew, p, Aig_ObjFanin1(pObj) );
return pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); if ( pNew->pManHaig == NULL )
return pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
else
{
Aig_Obj_t * pObjNew = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Aig_Regular(pObjNew->pHaig)->pHaig = Aig_Regular(pObj->pHaig);
return pObj->pData = pObjNew;
}
} }
/**Function************************************************************* /**Function*************************************************************
...@@ -132,28 +139,52 @@ Aig_Obj_t * Aig_ManDup_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj ) ...@@ -132,28 +139,52 @@ Aig_Obj_t * Aig_ManDup_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj )
Aig_Man_t * Aig_ManDup( Aig_Man_t * p, int fOrdered ) Aig_Man_t * Aig_ManDup( Aig_Man_t * p, int fOrdered )
{ {
Aig_Man_t * pNew; Aig_Man_t * pNew;
Aig_Obj_t * pObj; Aig_Obj_t * pObj, * pObjNew;
int i; int i;
// create the new manager // create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) ); pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->nRegs = p->nRegs; pNew->nRegs = p->nRegs;
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->pManHaig = p->pManHaig;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// create the PIs // create the PIs
Aig_ManCleanData( p ); Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew); Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManConst1(pNew)->pHaig = Aig_ManConst1(p)->pHaig;
Aig_ManForEachPi( p, pObj, i ) Aig_ManForEachPi( p, pObj, i )
pObj->pData = Aig_ObjCreatePi(pNew); {
pObjNew = Aig_ObjCreatePi( pNew );
pObjNew->pHaig = pObj->pHaig;
pObj->pData = pObjNew;
}
// duplicate internal nodes // duplicate internal nodes
if ( fOrdered ) if ( fOrdered )
{ {
Aig_ManForEachObj( p, pObj, i ) Aig_ManForEachObj( p, pObj, i )
if ( Aig_ObjIsBuf(pObj) ) if ( Aig_ObjIsBuf(pObj) )
pObj->pData = Aig_ObjChild0Copy(pObj); {
if ( pNew->pManHaig == NULL )
pObj->pData = Aig_ObjChild0Copy(pObj);
else
{
Aig_Obj_t * pObjNew = Aig_ObjChild0Copy(pObj);
Aig_Regular(pObjNew->pHaig)->pHaig = Aig_Regular(pObj->pHaig);
pObj->pData = pObjNew;
}
}
else if ( Aig_ObjIsNode(pObj) ) else if ( Aig_ObjIsNode(pObj) )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); {
if ( pNew->pManHaig == NULL )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
else
{
Aig_Obj_t * pObjNew = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Aig_Regular(pObjNew->pHaig)->pHaig = Aig_Regular(pObj->pHaig);
pObj->pData = pObjNew;
}
}
} }
else else
{ {
...@@ -166,8 +197,16 @@ Aig_Man_t * Aig_ManDup( Aig_Man_t * p, int fOrdered ) ...@@ -166,8 +197,16 @@ Aig_Man_t * Aig_ManDup( Aig_Man_t * p, int fOrdered )
} }
// add the POs // add the POs
Aig_ManForEachPo( p, pObj, i ) Aig_ManForEachPo( p, pObj, i )
Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(pObj) ); {
pObjNew = Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(pObj) );
pObjNew->pHaig = pObj->pHaig;
pObj->pData = pObjNew;
}
assert( Aig_ManBufNum(p) != 0 || Aig_ManNodeNum(p) == Aig_ManNodeNum(pNew) ); assert( Aig_ManBufNum(p) != 0 || Aig_ManNodeNum(p) == Aig_ManNodeNum(pNew) );
// pass the HAIG to the new AIG
p->pManHaig = NULL;
Aig_ManForEachObj( p, pObj, i )
pObj->pHaig = NULL;
// check the resulting network // check the resulting network
if ( !Aig_ManCheck(pNew) ) if ( !Aig_ManCheck(pNew) )
printf( "Aig_ManDup(): The check has failed.\n" ); printf( "Aig_ManDup(): The check has failed.\n" );
...@@ -228,6 +267,8 @@ void Aig_ManStop( Aig_Man_t * p ) ...@@ -228,6 +267,8 @@ void Aig_ManStop( Aig_Man_t * p )
{ {
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i; int i;
if ( p->pManHaig )
Aig_ManStop( p->pManHaig );
if ( p->vMapped ) if ( p->vMapped )
Vec_PtrFree( p->vMapped ); Vec_PtrFree( p->vMapped );
// print time // print time
......
src/aig/aig/aigObj.c
...@@ -88,7 +88,7 @@ Aig_Obj_t * Aig_ObjCreate( Aig_Man_t * p, Aig_Obj_t * pGhost ) ...@@ -88,7 +88,7 @@ Aig_Obj_t * Aig_ObjCreate( Aig_Man_t * p, Aig_Obj_t * pGhost )
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
assert( !Aig_IsComplement(pGhost) ); assert( !Aig_IsComplement(pGhost) );
assert( Aig_ObjIsHash(pGhost) ); assert( Aig_ObjIsHash(pGhost) );
assert( pGhost == &p->Ghost ); // assert( pGhost == &p->Ghost );
// get memory for the new object // get memory for the new object
pObj = Aig_ManFetchMemory( p ); pObj = Aig_ManFetchMemory( p );
pObj->Type = pGhost->Type; pObj->Type = pGhost->Type;
...@@ -97,6 +97,12 @@ Aig_Obj_t * Aig_ObjCreate( Aig_Man_t * p, Aig_Obj_t * pGhost ) ...@@ -97,6 +97,12 @@ Aig_Obj_t * Aig_ObjCreate( Aig_Man_t * p, Aig_Obj_t * pGhost )
// update node counters of the manager // update node counters of the manager
p->nObjs[Aig_ObjType(pObj)]++; p->nObjs[Aig_ObjType(pObj)]++;
assert( pObj->pData == NULL ); assert( pObj->pData == NULL );
if ( p->pManHaig )
{
pGhost->pFanin0 = Aig_ObjHaig( pGhost->pFanin0 );
pGhost->pFanin1 = Aig_ObjHaig( pGhost->pFanin1 );
pObj->pHaig = Aig_ObjCreate( p->pManHaig, pGhost );
}
return pObj; return pObj;
} }
...@@ -365,6 +371,13 @@ void Aig_ObjReplace( Aig_Man_t * p, Aig_Obj_t * pObjOld, Aig_Obj_t * pObjNew, in ...@@ -365,6 +371,13 @@ void Aig_ObjReplace( Aig_Man_t * p, Aig_Obj_t * pObjOld, Aig_Obj_t * pObjNew, in
// make sure object is not pointing to itself // make sure object is not pointing to itself
assert( pObjOld != Aig_ObjFanin0(pObjNewR) ); assert( pObjOld != Aig_ObjFanin0(pObjNewR) );
assert( pObjOld != Aig_ObjFanin1(pObjNewR) ); assert( pObjOld != Aig_ObjFanin1(pObjNewR) );
// map the HAIG nodes
if ( p->pManHaig != NULL )
{
assert( pObjNewR->pHaig != NULL );
assert( pObjNewR->pHaig->pHaig == NULL );
pObjNewR->pHaig->pHaig = pObjOld->pHaig;
}
// recursively delete the old node - but leave the object there // recursively delete the old node - but leave the object there
pObjNewR->nRefs++; pObjNewR->nRefs++;
Aig_ObjDelete_rec( p, pObjOld, 0 ); Aig_ObjDelete_rec( p, pObjOld, 0 );
...@@ -385,6 +398,8 @@ void Aig_ObjReplace( Aig_Man_t * p, Aig_Obj_t * pObjOld, Aig_Obj_t * pObjNew, in ...@@ -385,6 +398,8 @@ void Aig_ObjReplace( Aig_Man_t * p, Aig_Obj_t * pObjOld, Aig_Obj_t * pObjNew, in
pObjOld->Type = pObjNew->Type; pObjOld->Type = pObjNew->Type;
Aig_ObjDisconnect( p, pObjNew ); Aig_ObjDisconnect( p, pObjNew );
Aig_ObjConnect( p, pObjOld, pFanin0, pFanin1 ); Aig_ObjConnect( p, pObjOld, pFanin0, pFanin1 );
// update the haig node
pObjOld->pHaig = pObjNew->pHaig;
// delete the new object // delete the new object
Aig_ObjDelete( p, pObjNew ); Aig_ObjDelete( p, pObjNew );
// update levels // update levels
......
src/aig/aig/aigOper.c
...@@ -139,6 +139,15 @@ Aig_Obj_t * Aig_And( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 ) ...@@ -139,6 +139,15 @@ Aig_Obj_t * Aig_And( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
{ {
Aig_Obj_t * pGhost, * pResult; Aig_Obj_t * pGhost, * pResult;
// Aig_Obj_t * pFan0, * pFan1; // Aig_Obj_t * pFan0, * pFan1;
if ( p->pTable == NULL )
{
// pGhost = Aig_ObjCreateGhost( p, p0, p1, AIG_OBJ_AND );
pGhost = Aig_ManGhost(p);
pGhost->Type = AIG_OBJ_AND;
pGhost->pFanin0 = p0;
pGhost->pFanin1 = p1;
return Aig_ObjCreate( p, pGhost );
}
// check trivial cases // check trivial cases
if ( p0 == p1 ) if ( p0 == p1 )
return p0; return p0;
......
src/aig/aig/aigRetF.c 0 → 100644
/**CFile****************************************************************
FileName [aigRetF.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [AIG package.]
Synopsis [Retiming frontier.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - April 28, 2007.]
Revision [$Id: aigRetF.c,v 1.00 2007/04/28 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Mark the nodes reachable from the PIs in the reverse order.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_ManRetimeMark_rec( Aig_Man_t * p, Aig_Obj_t * pObj )
{
if ( pObj->fMarkB )
return 1;
if ( Aig_ObjIsPi(pObj) || Aig_ObjIsConst1(pObj) )
return 0;
if ( Aig_ObjIsTravIdCurrent(p, pObj) )
return pObj->fMarkB;
Aig_ObjSetTravIdCurrent(p, pObj);
if ( Aig_ManRetimeMark_rec( p, Aig_ObjFanin0(pObj) ) )
return pObj->fMarkB = 1;
if ( Aig_ObjIsNode(pObj) && Aig_ManRetimeMark_rec( p, Aig_ObjFanin1(pObj) ) )
return pObj->fMarkB = 1;
assert( pObj->fMarkB == 0 );
return 0;
}
/**Function*************************************************************
Synopsis [Mark the nodes reachable from the true PIs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManRetimeMark( Aig_Man_t * p )
{
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int fChange, i;
// mark the PIs
Aig_ManForEachObj( p, pObj, i )
assert( pObj->fMarkB == 0 );
Aig_ManForEachPiSeq( p, pObj, i )
pObj->fMarkB = 1;
// map registers into each other
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
{
assert( pObjLo->pNext == NULL );
assert( pObjLi->pNext == NULL );
pObjLo->pNext = pObjLi;
pObjLi->pNext = pObjLo;
}
// iterativively mark the logic reachable from PIs
fChange = 1;
while ( fChange )
{
fChange = 0;
Aig_ManIncrementTravId( p );
Aig_ManForEachPo( p, pObj, i )
{
if ( pObj->fMarkB )
continue;
if ( Aig_ManRetimeMark_rec( p, pObj ) )
{
if ( pObj->pNext )
pObj->pNext->fMarkB = 1;
fChange = 1;
}
}
}
// clean register mapping
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
pObjLo->pNext = pObjLi->pNext = NULL;
}
/**Function*************************************************************
Synopsis [Performs forward retiming.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManRetimeFrontier( Aig_Man_t * p, int nStepsMax )
{
Aig_Obj_t * pObj, * pObjNew, * pObjLo, * pObjLo0, * pObjLo1, * pObjLi, * pObjLi0, * pObjLi1;//, * pObjLi0_, * pObjLi1_, * pObjLi0__, * pObjLi1__;
int i, Counter, fCompl, fChange;
assert( Aig_ManRegNum(p) > 0 );
// remove structural hashing table
Aig_TableClear( p );
// mark the retimable nodes
Aig_ManRetimeMark( p );
// mark the register outputs
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
{
pObjLo->fMarkA = 1;
pObjLo->pNext = pObjLi;
pObjLi->pNext = pObjLo;
}
// go through the nodes and find retimable ones
Counter = 0;
fChange = 1;
while ( fChange )
{
fChange = 0;
Aig_ManForEachNode( p, pObj, i )
{
if ( !pObj->fMarkB )
continue;
if ( Aig_ObjIsBuf(pObj) )
continue;
// get the real inputs of the node (skipping the buffers)
pObjLo0 = Aig_ObjReal_rec( Aig_ObjChild0(pObj) );
pObjLo1 = Aig_ObjReal_rec( Aig_ObjChild1(pObj) );
if ( !Aig_Regular(pObjLo0)->fMarkA || !Aig_Regular(pObjLo1)->fMarkA )
continue;
// remember complemented attribute
fCompl = Aig_IsComplement(pObjLo0) & Aig_IsComplement(pObjLo1);
// get the register inputs
// pObjLi0_ = Aig_Regular(pObjLo0)->pNext;
// pObjLi1_ = Aig_Regular(pObjLo1)->pNext;
// pObjLi0__ = Aig_ObjChild0(Aig_Regular(pObjLo0)->pNext);
// pObjLi1__ = Aig_ObjChild0(Aig_Regular(pObjLo1)->pNext);
pObjLi0 = Aig_NotCond( Aig_ObjChild0(Aig_Regular(pObjLo0)->pNext), Aig_IsComplement(pObjLo0) );
pObjLi1 = Aig_NotCond( Aig_ObjChild0(Aig_Regular(pObjLo1)->pNext), Aig_IsComplement(pObjLo1) );
// create new node
pObjNew = Aig_And( p, pObjLi0, pObjLi1 );
pObjNew->fMarkB = 1;
// create new register
pObjLo = Aig_ObjCreatePi(p);
pObjLo->fMarkA = 1;
pObjLi = Aig_ObjCreatePo( p, Aig_NotCond(pObjNew, fCompl) );
p->nRegs++;
pObjLo->pNext = pObjLi;
pObjLi->pNext = pObjLo;
// add the buffer
Aig_ObjDisconnect( p, pObj );
pObj->Type = AIG_OBJ_BUF;
p->nObjs[AIG_OBJ_AND]--;
p->nObjs[AIG_OBJ_BUF]++;
Aig_ObjConnect( p, pObj, Aig_NotCond(pObjLo, fCompl), NULL );
// create HAIG if defined
if ( p->pManHaig )
{
// create HAIG latch
pObjLo->pHaig = Aig_ObjCreatePi( p->pManHaig );
pObjLi->pHaig = Aig_ObjCreatePo( p->pManHaig, Aig_ObjHaig( Aig_ObjChild0(pObjLi) ) );
// create equivalence class
assert( pObjLo->pHaig != NULL );
assert( pObjLo->pHaig->pHaig == NULL );
pObjLo->pHaig->pHaig = Aig_Regular(pObj->pHaig);
}
// mark the change
fChange = 1;
// check the limit
if ( ++Counter >= nStepsMax )
{
fChange = 0;
break;
}
}
}
// clean the markings
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
{
pObjLo->fMarkA = 0;
pObjLo->pNext = pObjLi->pNext = NULL;
}
Aig_ManForEachObj( p, pObj, i )
pObj->fMarkB = 0;
// remove useless registers
Aig_ManSeqCleanup( p );
// rehash the nodes
return Aig_ManDup( p, 1 );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/aig/aig/aigScl.c
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
Synopsis [Remaps the manager.] Synopsis [Remaps the manager.]
Description [Map in the array specifies for each CI nodes the node that Description [Map in the array specifies for each CI node the node that
should be used after remapping.] should be used after remapping.]
SideEffects [] SideEffects []
...@@ -101,7 +101,7 @@ void Aig_ManSeqCleanup_rec( Aig_Man_t * p, Aig_Obj_t * pObj, Vec_Ptr_t * vNodes ...@@ -101,7 +101,7 @@ void Aig_ManSeqCleanup_rec( Aig_Man_t * p, Aig_Obj_t * pObj, Vec_Ptr_t * vNodes
Vec_PtrPush( vNodes, pObj->pNext ); Vec_PtrPush( vNodes, pObj->pNext );
return; return;
} }
if ( Aig_ObjIsPo(pObj) ) if ( Aig_ObjIsPo(pObj) || Aig_ObjIsBuf(pObj) )
{ {
Aig_ManSeqCleanup_rec( p, Aig_ObjFanin0(pObj), vNodes ); Aig_ManSeqCleanup_rec( p, Aig_ObjFanin0(pObj), vNodes );
return; return;
...@@ -127,7 +127,7 @@ int Aig_ManSeqCleanup( Aig_Man_t * p ) ...@@ -127,7 +127,7 @@ int Aig_ManSeqCleanup( Aig_Man_t * p )
Vec_Ptr_t * vNodes, * vCis, * vCos; Vec_Ptr_t * vNodes, * vCis, * vCos;
Aig_Obj_t * pObj, * pObjLi, * pObjLo; Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int i, nTruePis, nTruePos; int i, nTruePis, nTruePos;
assert( Aig_ManBufNum(p) == 0 ); // assert( Aig_ManBufNum(p) == 0 );
// mark the PIs // mark the PIs
Aig_ManIncrementTravId( p ); Aig_ManIncrementTravId( p );
......
src/aig/aig/aigTable.c
...@@ -184,6 +184,8 @@ Aig_Obj_t * Aig_TableLookupTwo( Aig_Man_t * p, Aig_Obj_t * pFanin0, Aig_Obj_t * ...@@ -184,6 +184,8 @@ Aig_Obj_t * Aig_TableLookupTwo( Aig_Man_t * p, Aig_Obj_t * pFanin0, Aig_Obj_t *
void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj ) void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj )
{ {
Aig_Obj_t ** ppPlace; Aig_Obj_t ** ppPlace;
if ( p->pTable == NULL )
return;
assert( !Aig_IsComplement(pObj) ); assert( !Aig_IsComplement(pObj) );
assert( Aig_TableLookup(p, pObj) == NULL ); assert( Aig_TableLookup(p, pObj) == NULL );
if ( (pObj->Id & 0xFF) == 0 && 2 * p->nTableSize < Aig_ManNodeNum(p) ) if ( (pObj->Id & 0xFF) == 0 && 2 * p->nTableSize < Aig_ManNodeNum(p) )
...@@ -207,6 +209,8 @@ void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj ) ...@@ -207,6 +209,8 @@ void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj )
void Aig_TableDelete( Aig_Man_t * p, Aig_Obj_t * pObj ) void Aig_TableDelete( Aig_Man_t * p, Aig_Obj_t * pObj )
{ {
Aig_Obj_t ** ppPlace; Aig_Obj_t ** ppPlace;
if ( p->pTable == NULL )
return;
assert( !Aig_IsComplement(pObj) ); assert( !Aig_IsComplement(pObj) );
ppPlace = Aig_TableFind( p, pObj ); ppPlace = Aig_TableFind( p, pObj );
assert( *ppPlace == pObj ); // node should be in the table assert( *ppPlace == pObj ); // node should be in the table
...@@ -261,6 +265,23 @@ void Aig_TableProfile( Aig_Man_t * p ) ...@@ -261,6 +265,23 @@ void Aig_TableProfile( Aig_Man_t * p )
} }
} }
/**Function********************************************************************
Synopsis [Profiles the hash table.]
Description []
SideEffects []
SeeAlso []
******************************************************************************/
void Aig_TableClear( Aig_Man_t * p )
{
FREE( p->pTable );
p->nTableSize = 0;
}
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
......
src/aig/aig/aigUtil.c
...@@ -649,7 +649,7 @@ void Aig_ManDump( Aig_Man_t * p ) ...@@ -649,7 +649,7 @@ void Aig_ManDump( Aig_Man_t * p )
/**Function************************************************************* /**Function*************************************************************
Synopsis [Writes the AIG into the BLIF file.] Synopsis [Writes the AIG into a BLIF file.]
Description [] Description []
...@@ -680,7 +680,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName ) ...@@ -680,7 +680,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName )
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( vNodes, pObj, i )
pObj->iData = Counter++; pObj->iData = Counter++;
nDigits = Aig_Base10Log( Counter ); nDigits = Aig_Base10Log( Counter );
// write the file // write the file
pFile = fopen( pFileName, "w" ); pFile = fopen( pFileName, "w" );
fprintf( pFile, "# BLIF file written by procedure Aig_ManDumpBlif()\n" ); fprintf( pFile, "# BLIF file written by procedure Aig_ManDumpBlif()\n" );
// fprintf( pFile, "# http://www.eecs.berkeley.edu/~alanmi/abc/\n" ); // fprintf( pFile, "# http://www.eecs.berkeley.edu/~alanmi/abc/\n" );
...@@ -702,7 +702,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName ) ...@@ -702,7 +702,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName )
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i ) Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
fprintf( pFile, ".latch n%0*d n%0*d 0\n", nDigits, pObjLi->iData, nDigits, pObjLo->iData ); fprintf( pFile, ".latch n%0*d n%0*d 0\n", nDigits, pObjLi->iData, nDigits, pObjLo->iData );
fprintf( pFile, "\n" ); fprintf( pFile, "\n" );
} }
// write nodes // write nodes
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( vNodes, pObj, i )
{ {
...@@ -731,7 +731,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName ) ...@@ -731,7 +731,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName )
/**Function************************************************************* /**Function*************************************************************
Synopsis [Writes the AIG into the BLIF file.] Synopsis [Writes the AIG into a Verilog file.]
Description [] Description []
......
src/aig/fra/fraCore.c
...@@ -280,6 +280,8 @@ static inline void Fra_FraigNode( Fra_Man_t * p, Aig_Obj_t * pObj ) ...@@ -280,6 +280,8 @@ static inline void Fra_FraigNode( Fra_Man_t * p, Aig_Obj_t * pObj )
// Fra_FraigVerifyCounterEx( p, p->vCex ); // Fra_FraigVerifyCounterEx( p, p->vCex );
// simulate the counter-example and return the Fraig node // simulate the counter-example and return the Fraig node
Fra_SmlResimulate( p ); Fra_SmlResimulate( p );
if ( p->pManFraig->pData )
return;
if ( !p->pPars->nFramesK && Fra_ClassObjRepr(pObj) == pObjRepr ) if ( !p->pPars->nFramesK && Fra_ClassObjRepr(pObj) == pObjRepr )
printf( "Fra_FraigNode(): Error in class refinement!\n" ); printf( "Fra_FraigNode(): Error in class refinement!\n" );
assert( p->pPars->nFramesK || Fra_ClassObjRepr(pObj) != pObjRepr ); assert( p->pPars->nFramesK || Fra_ClassObjRepr(pObj) != pObjRepr );
......
src/aig/fra/fraInd.c
...@@ -402,16 +402,21 @@ p->timeTrav += clock() - clk2; ...@@ -402,16 +402,21 @@ p->timeTrav += clock() - clk2;
Fra_ClassesCountLits(p->pCla), p->pManFraig->nAsserts ); Fra_ClassesCountLits(p->pCla), p->pManFraig->nAsserts );
if ( p->pCla->vImps ) if ( p->pCla->vImps )
printf( "I = %6d. ", Vec_IntSize(p->pCla->vImps) ); printf( "I = %6d. ", Vec_IntSize(p->pCla->vImps) );
printf( "NR = %6d.\n", Aig_ManNodeNum(p->pManFraig) ); printf( "NR = %6d. ", Aig_ManNodeNum(p->pManFraig) );
printf( "\n" );
} }
// perform sweeping // perform sweeping
p->nSatCallsRecent = 0; p->nSatCallsRecent = 0;
p->nSatCallsSkipped = 0; p->nSatCallsSkipped = 0;
clk2 = clock();
Fra_FraigSweep( p ); Fra_FraigSweep( p );
if ( fVerbose )
{
// PRT( "t", clock() - clk2 );
}
// Sat_SolverPrintStats( stdout, p->pSat ); // Sat_SolverPrintStats( stdout, p->pSat );
// remove FRAIG and SAT solver // remove FRAIG and SAT solver
Aig_ManStop( p->pManFraig ); p->pManFraig = NULL; Aig_ManStop( p->pManFraig ); p->pManFraig = NULL;
sat_solver_delete( p->pSat ); p->pSat = NULL; sat_solver_delete( p->pSat ); p->pSat = NULL;
......
src/aig/fra/fraSec.c
...@@ -228,9 +228,11 @@ PRT( "Time", clock() - clk ); ...@@ -228,9 +228,11 @@ PRT( "Time", clock() - clk );
} }
if ( pNew->nRegs ) if ( pNew->nRegs )
pNew = Aig_ManConstReduce( pNew, 0 ); pNew = Aig_ManConstReduce( pNew, 0 );
// perform sequential simulation // perform sequential simulation
if ( pNew->nRegs )
{
clk = clock(); clk = clock();
pSml = Fra_SmlSimulateSeq( pNew, 0, 128 * nFrames, 1 + 16/(1+Aig_ManNodeNum(pNew)/1000) ); pSml = Fra_SmlSimulateSeq( pNew, 0, 128 * nFrames, 1 + 16/(1+Aig_ManNodeNum(pNew)/1000) );
if ( fVerbose ) if ( fVerbose )
...@@ -250,6 +252,7 @@ PRT( "Time", clock() - clkTotal ); ...@@ -250,6 +252,7 @@ PRT( "Time", clock() - clkTotal );
return RetValue; return RetValue;
} }
Fra_SmlStop( pSml ); Fra_SmlStop( pSml );
}
} }
// get the miter status // get the miter status
......
src/base/abc/abcCheck.c
...@@ -913,7 +913,7 @@ int Abc_NtkCheckUniqueCoNames( Abc_Ntk_t * pNtk ) ...@@ -913,7 +913,7 @@ int Abc_NtkCheckUniqueCoNames( Abc_Ntk_t * pNtk )
***********************************************************************/ ***********************************************************************/
int Abc_NtkCheckUniqueCioNames( Abc_Ntk_t * pNtk ) int Abc_NtkCheckUniqueCioNames( Abc_Ntk_t * pNtk )
{ {
Abc_Obj_t * pObj, * pObjCi; Abc_Obj_t * pObj, * pObjCi, * pFanin;
int i, nCiId, fRetValue = 1; int i, nCiId, fRetValue = 1;
assert( !Abc_NtkIsNetlist(pNtk) ); assert( !Abc_NtkIsNetlist(pNtk) );
Abc_NtkForEachCo( pNtk, pObj, i ) Abc_NtkForEachCo( pNtk, pObj, i )
...@@ -923,9 +923,11 @@ int Abc_NtkCheckUniqueCioNames( Abc_Ntk_t * pNtk ) ...@@ -923,9 +923,11 @@ int Abc_NtkCheckUniqueCioNames( Abc_Ntk_t * pNtk )
continue; continue;
pObjCi = Abc_NtkObj( pNtk, nCiId ); pObjCi = Abc_NtkObj( pNtk, nCiId );
assert( !strcmp( Abc_ObjName(pObj), Abc_ObjName(pObjCi) ) ); assert( !strcmp( Abc_ObjName(pObj), Abc_ObjName(pObjCi) ) );
if ( Abc_ObjFanin0(pObj) != pObjCi ) pFanin = Abc_ObjFanin0(pObj);
if ( pFanin != pObjCi )
{ {
printf( "Abc_NtkCheck: A CI/CO pair share the name (%s) but do not link directly.\n", Abc_ObjName(pObj) ); printf( "Abc_NtkCheck: A CI/CO pair share the name (%s) but do not link directly. The name of the CO fanin is %s.\n",
Abc_ObjName(pObj), Abc_ObjName(Abc_ObjFanin0(pObj)) );
fRetValue = 0; fRetValue = 0;
} }
} }
......
src/base/abci/abc.c
...@@ -164,6 +164,7 @@ static int Abc_CommandPipe ( Abc_Frame_t * pAbc, int argc, char ** arg ...@@ -164,6 +164,7 @@ static int Abc_CommandPipe ( Abc_Frame_t * pAbc, int argc, char ** arg
static int Abc_CommandSeq ( Abc_Frame_t * pAbc, int argc, char ** argv ); static int Abc_CommandSeq ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandUnseq ( Abc_Frame_t * pAbc, int argc, char ** argv ); static int Abc_CommandUnseq ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandRetime ( Abc_Frame_t * pAbc, int argc, char ** argv ); static int Abc_CommandRetime ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandDRetime ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandSeqFpga ( Abc_Frame_t * pAbc, int argc, char ** argv ); static int Abc_CommandSeqFpga ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandSeqMap ( Abc_Frame_t * pAbc, int argc, char ** argv ); static int Abc_CommandSeqMap ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandSeqSweep ( Abc_Frame_t * pAbc, int argc, char ** argv ); static int Abc_CommandSeqSweep ( Abc_Frame_t * pAbc, int argc, char ** argv );
...@@ -333,6 +334,7 @@ void Abc_Init( Abc_Frame_t * pAbc ) ...@@ -333,6 +334,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "Sequential", "undc", Abc_CommandUndc, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "undc", Abc_CommandUndc, 1 );
// Cmd_CommandAdd( pAbc, "Sequential", "pipe", Abc_CommandPipe, 1 ); // Cmd_CommandAdd( pAbc, "Sequential", "pipe", Abc_CommandPipe, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "retime", Abc_CommandRetime, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "retime", Abc_CommandRetime, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "dretime", Abc_CommandDRetime, 1 );
// Cmd_CommandAdd( pAbc, "Sequential", "sfpga", Abc_CommandSeqFpga, 1 ); // Cmd_CommandAdd( pAbc, "Sequential", "sfpga", Abc_CommandSeqFpga, 1 );
// Cmd_CommandAdd( pAbc, "Sequential", "smap", Abc_CommandSeqMap, 1 ); // Cmd_CommandAdd( pAbc, "Sequential", "smap", Abc_CommandSeqMap, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "ssweep", Abc_CommandSeqSweep, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "ssweep", Abc_CommandSeqSweep, 1 );
...@@ -6189,7 +6191,7 @@ usage: ...@@ -6189,7 +6191,7 @@ usage:
int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv ) int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
{ {
FILE * pOut, * pErr; FILE * pOut, * pErr;
Abc_Ntk_t * pNtk, * pNtkRes; Abc_Ntk_t * pNtk;//, * pNtkRes;
int c; int c;
int nLevels; int nLevels;
int fVerbose; int fVerbose;
...@@ -6204,14 +6206,16 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -6204,14 +6206,16 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
extern Abc_Ntk_t * Abc_NtkFilter( Abc_Ntk_t * pNtk ); extern Abc_Ntk_t * Abc_NtkFilter( Abc_Ntk_t * pNtk );
extern Abc_Ntk_t * Abc_NtkDarRetime( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose ); extern Abc_Ntk_t * Abc_NtkDarRetime( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose );
extern Abc_Ntk_t * Abc_NtkPcmTest( Abc_Ntk_t * pNtk, int fVerbose ); extern Abc_Ntk_t * Abc_NtkPcmTest( Abc_Ntk_t * pNtk, int fVerbose );
extern Abc_NtkDarHaigRecord( Abc_Ntk_t * pNtk );
extern int Abc_NtkDarClau( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose );
pNtk = Abc_FrameReadNtk(pAbc); pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc); pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc); pErr = Abc_FrameReadErr(pAbc);
// set defaults // set defaults
fVerbose = 0; fVerbose = 1;
nLevels = 1000; nLevels = 1000;
Extra_UtilGetoptReset(); Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "Nvh" ) ) != EOF ) while ( ( c = Extra_UtilGetopt( argc, argv, "Nvh" ) ) != EOF )
{ {
...@@ -6324,13 +6328,14 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -6324,13 +6328,14 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1; return 1;
} }
*/ */
/*
if ( !Abc_NtkIsStrash(pNtk) ) if ( !Abc_NtkIsStrash(pNtk) )
{ {
fprintf( stdout, "Currently only works for structurally hashed circuits.\n" ); fprintf( stdout, "Currently only works for structurally hashed circuits.\n" );
return 0; return 0;
} }
*/
/*
if ( Abc_NtkIsStrash(pNtk) ) if ( Abc_NtkIsStrash(pNtk) )
{ {
fprintf( stdout, "Currently only works for logic circuits.\n" ); fprintf( stdout, "Currently only works for logic circuits.\n" );
...@@ -6348,6 +6353,9 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -6348,6 +6353,9 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
} }
// replace the current network // replace the current network
Abc_FrameReplaceCurrentNetwork( pAbc, pNtkRes ); Abc_FrameReplaceCurrentNetwork( pAbc, pNtkRes );
*/
// Abc_NtkDarHaigRecord( pNtk );
Abc_NtkDarClau( pNtk, 1000, fVerbose );
return 0; return 0;
usage: usage:
fprintf( pErr, "usage: test [-h]\n" ); fprintf( pErr, "usage: test [-h]\n" );
...@@ -10818,6 +10826,106 @@ usage: ...@@ -10818,6 +10826,106 @@ usage:
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Abc_CommandDRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk, * pNtkRes;
int nStepsMax;
int fFastAlgo;
int fVerbose;
int c;
extern Abc_Ntk_t * Abc_NtkDarRetimeF( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose );
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
nStepsMax = 100000;
fFastAlgo = 0;
fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "Savh" ) ) != EOF )
{
switch ( c )
{
case 'S':
if ( globalUtilOptind >= argc )
{
fprintf( pErr, "Command line switch \"-S\" should be followed by a positive integer.\n" );
goto usage;
}
nStepsMax = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
if ( nStepsMax < 0 )
goto usage;
break;
case 'a':
fFastAlgo ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( !Abc_NtkLatchNum(pNtk) )
{
fprintf( pErr, "The network has no latches. Retiming is not performed.\n" );
return 0;
}
if ( !Abc_NtkIsStrash(pNtk) )
{
printf( "This command works only for structrally hashed networks. Run \"st\".\n" );
return 0;
}
// perform the retiming
if ( fFastAlgo )
pNtkRes = Abc_NtkDarRetime( pNtk, nStepsMax, fVerbose );
else
pNtkRes = Abc_NtkDarRetimeF( pNtk, nStepsMax, fVerbose );
if ( pNtkRes == NULL )
{
fprintf( pErr, "Retiming has failed.\n" );
return 1;
}
// replace the current network
Abc_FrameReplaceCurrentNetwork( pAbc, pNtkRes );
return 0;
usage:
fprintf( pErr, "usage: dretime [-S num] [-avh]\n" );
fprintf( pErr, "\t retimes the current network forward\n" );
fprintf( pErr, "\t-S num : the max number of retiming steps to perform [default = %d]\n", nStepsMax );
fprintf( pErr, "\t-a : enables a fast algorithm [default = %s]\n", fFastAlgo? "yes": "no" );
fprintf( pErr, "\t-v : enables verbose output [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv ) int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
{ {
FILE * pOut, * pErr; FILE * pOut, * pErr;
......
src/base/abci/abcDar.c
...@@ -87,7 +87,8 @@ Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fRegisters ) ...@@ -87,7 +87,8 @@ Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fRegisters )
if ( fRegisters ) if ( fRegisters )
{ {
pMan->nRegs = Abc_NtkLatchNum(pNtk); pMan->nRegs = Abc_NtkLatchNum(pNtk);
pMan->vFlopNums = Vec_IntStartNatural( pMan->nRegs ); // pMan->vFlopNums = Vec_IntStartNatural( pMan->nRegs );
pMan->vFlopNums = NULL;
} }
// transfer the pointers to the basic nodes // transfer the pointers to the basic nodes
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Aig_ManConst1(pMan); Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Aig_ManConst1(pMan);
...@@ -198,7 +199,7 @@ Abc_Ntk_t * Abc_NtkFromDarSeqSweep( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan ) ...@@ -198,7 +199,7 @@ Abc_Ntk_t * Abc_NtkFromDarSeqSweep( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan )
Abc_Ntk_t * pNtkNew; Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObjNew, * pLatch; Abc_Obj_t * pObjNew, * pLatch;
Aig_Obj_t * pObj, * pObjLo, * pObjLi; Aig_Obj_t * pObj, * pObjLo, * pObjLi;
int i; int i, iNodeId;
// assert( Aig_ManRegNum(pMan) != Abc_NtkLatchNum(pNtkOld) ); // assert( Aig_ManRegNum(pMan) != Abc_NtkLatchNum(pNtkOld) );
// perform strashing // perform strashing
pNtkNew = Abc_NtkStartFromNoLatches( pNtkOld, ABC_NTK_STRASH, ABC_FUNC_AIG ); pNtkNew = Abc_NtkStartFromNoLatches( pNtkOld, ABC_NTK_STRASH, ABC_FUNC_AIG );
...@@ -242,7 +243,12 @@ Abc_Ntk_t * Abc_NtkFromDarSeqSweep( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan ) ...@@ -242,7 +243,12 @@ Abc_Ntk_t * Abc_NtkFromDarSeqSweep( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan )
{ {
if ( pMan->nAsserts && i == Aig_ManPoNum(pMan) - pMan->nAsserts ) if ( pMan->nAsserts && i == Aig_ManPoNum(pMan) - pMan->nAsserts )
break; break;
Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), (Abc_Obj_t *)Aig_ObjChild0Copy(pObj) ); iNodeId = Nm_ManFindIdByNameTwoTypes( pNtkNew->pManName, Abc_ObjName(Abc_NtkCo(pNtkNew, i)), ABC_OBJ_PI, ABC_OBJ_BO );
if ( iNodeId >= 0 )
pObjNew = Abc_NtkObj( pNtkNew, iNodeId );
else
pObjNew = (Abc_Obj_t *)Aig_ObjChild0Copy(pObj);
Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), pObjNew );
} }
// if there are assertions, add them // if there are assertions, add them
if ( pMan->nAsserts > 0 ) if ( pMan->nAsserts > 0 )
...@@ -1270,6 +1276,9 @@ Abc_Ntk_t * Abc_NtkDarRetime( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose ) ...@@ -1270,6 +1276,9 @@ Abc_Ntk_t * Abc_NtkDarRetime( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose )
if ( pMan == NULL ) if ( pMan == NULL )
return NULL; return NULL;
// Aig_ManReduceLachesCount( pMan ); // Aig_ManReduceLachesCount( pMan );
if ( pMan->vFlopNums )
Vec_IntFree( pMan->vFlopNums );
pMan->vFlopNums = NULL;
pMan = Rtm_ManRetime( pTemp = pMan, 1, nStepsMax, 0 ); pMan = Rtm_ManRetime( pTemp = pMan, 1, nStepsMax, 0 );
Aig_ManStop( pTemp ); Aig_ManStop( pTemp );
...@@ -1284,6 +1293,65 @@ Abc_Ntk_t * Abc_NtkDarRetime( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose ) ...@@ -1284,6 +1293,65 @@ Abc_Ntk_t * Abc_NtkDarRetime( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose )
/**Function************************************************************* /**Function*************************************************************
Synopsis [Gives the current ABC network to AIG manager for processing.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkDarRetimeF( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose )
{
Abc_Ntk_t * pNtkAig;
Aig_Man_t * pMan, * pTemp;
pMan = Abc_NtkToDar( pNtk, 1 );
if ( pMan == NULL )
return NULL;
// Aig_ManReduceLachesCount( pMan );
if ( pMan->vFlopNums )
Vec_IntFree( pMan->vFlopNums );
pMan->vFlopNums = NULL;
pMan = Aig_ManRetimeFrontier( pTemp = pMan, nStepsMax );
Aig_ManStop( pTemp );
// pMan = Aig_ManReduceLaches( pMan, 1 );
// pMan = Aig_ManConstReduce( pMan, 1 );
pNtkAig = Abc_NtkFromDarSeqSweep( pNtk, pMan );
Aig_ManStop( pMan );
return pNtkAig;
}
/**Function*************************************************************
Synopsis [Gives the current ABC network to AIG manager for processing.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkDarHaigRecord( Abc_Ntk_t * pNtk )
{
Aig_Man_t * pMan;
pMan = Abc_NtkToDar( pNtk, 1 );
if ( pMan == NULL )
return;
// Aig_ManReduceLachesCount( pMan );
if ( pMan->vFlopNums )
Vec_IntFree( pMan->vFlopNums );
pMan->vFlopNums = NULL;
Aig_ManHaigRecord( pMan );
Aig_ManStop( pMan );
}
/**Function*************************************************************
Synopsis [Performs random simulation.] Synopsis [Performs random simulation.]
Description [] Description []
...@@ -1322,6 +1390,39 @@ int Abc_NtkDarSeqSim( Abc_Ntk_t * pNtk, int nFrames, int nWords, int fVerbose ) ...@@ -1322,6 +1390,39 @@ int Abc_NtkDarSeqSim( Abc_Ntk_t * pNtk, int nFrames, int nWords, int fVerbose )
return RetValue; return RetValue;
} }
/**Function*************************************************************
Synopsis [Gives the current ABC network to AIG manager for processing.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkDarClau( Abc_Ntk_t * pNtk, int nStepsMax, int fVerbose )
{
extern int Fra_Clau( Aig_Man_t * pMan, int nIters, int fVerbose );
Aig_Man_t * pMan;
if ( Abc_NtkPoNum(pNtk) != 1 )
{
printf( "The number of outputs should be 1.\n" );
return 1;
}
pMan = Abc_NtkToDar( pNtk, 1 );
if ( pMan == NULL )
return 1;
// Aig_ManReduceLachesCount( pMan );
if ( pMan->vFlopNums )
Vec_IntFree( pMan->vFlopNums );
pMan->vFlopNums = NULL;
Fra_Clau( pMan, nStepsMax, fVerbose );
Aig_ManStop( pMan );
return 1;
}
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
......
src/base/io/io.c
...@@ -348,6 +348,8 @@ int IoCommandReadBlif( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -348,6 +348,8 @@ int IoCommandReadBlif( Abc_Frame_t * pAbc, int argc, char ** argv )
{ {
Abc_Ntk_t * pTemp; Abc_Ntk_t * pTemp;
pNtk = Io_ReadBlif( pFileName, fCheck ); pNtk = Io_ReadBlif( pFileName, fCheck );
if ( pNtk == NULL )
return 1;
pNtk = Abc_NtkToLogic( pTemp = pNtk ); pNtk = Abc_NtkToLogic( pTemp = pNtk );
Abc_NtkDelete( pTemp ); Abc_NtkDelete( pTemp );
} }
......
src/base/ver/verCore.c
...@@ -58,6 +58,7 @@ static int Ver_ParseAlways( Ver_Man_t * p, Abc_Ntk_t * pNtk ); ...@@ -58,6 +58,7 @@ static int Ver_ParseAlways( Ver_Man_t * p, Abc_Ntk_t * pNtk );
static int Ver_ParseInitial( Ver_Man_t * p, Abc_Ntk_t * pNtk ); static int Ver_ParseInitial( Ver_Man_t * p, Abc_Ntk_t * pNtk );
static int Ver_ParseAssign( Ver_Man_t * p, Abc_Ntk_t * pNtk ); static int Ver_ParseAssign( Ver_Man_t * p, Abc_Ntk_t * pNtk );
static int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t GateType ); static int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t GateType );
static int Ver_ParseFlopStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk );
static int Ver_ParseGate( Ver_Man_t * p, Abc_Ntk_t * pNtk, Mio_Gate_t * pGate ); static int Ver_ParseGate( Ver_Man_t * p, Abc_Ntk_t * pNtk, Mio_Gate_t * pGate );
static int Ver_ParseBox( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkBox ); static int Ver_ParseBox( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkBox );
static int Ver_ParseConnectBox( Ver_Man_t * pMan, Abc_Obj_t * pBox ); static int Ver_ParseConnectBox( Ver_Man_t * pMan, Abc_Obj_t * pBox );
...@@ -472,6 +473,9 @@ int Ver_ParseModule( Ver_Man_t * pMan ) ...@@ -472,6 +473,9 @@ int Ver_ParseModule( Ver_Man_t * pMan )
else if ( !strcmp( pWord, "not" ) ) else if ( !strcmp( pWord, "not" ) )
RetValue = Ver_ParseGateStandard( pMan, pNtk, VER_GATE_NOT ); RetValue = Ver_ParseGateStandard( pMan, pNtk, VER_GATE_NOT );
else if ( !strcmp( pWord, "dff" ) )
RetValue = Ver_ParseFlopStandard( pMan, pNtk );
else if ( !strcmp( pWord, "assign" ) ) else if ( !strcmp( pWord, "assign" ) )
RetValue = Ver_ParseAssign( pMan, pNtk ); RetValue = Ver_ParseAssign( pMan, pNtk );
else if ( !strcmp( pWord, "always" ) ) else if ( !strcmp( pWord, "always" ) )
...@@ -1366,6 +1370,105 @@ int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t Ga ...@@ -1366,6 +1370,105 @@ int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t Ga
/**Function************************************************************* /**Function*************************************************************
Synopsis [Parses one directive.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Ver_ParseFlopStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk )
{
Ver_Stream_t * p = pMan->pReader;
Abc_Obj_t * pNetLi, * pNetLo, * pLatch;
char * pWord, Symbol;
// convert from the blackbox into the network with local functions representated by AIGs
if ( !Ver_ParseConvertNetwork( pMan, pNtk, pMan->fMapped ) )
return 0;
// this is gate name - throw it away
if ( Ver_StreamPopChar(p) != '(' )
{
sprintf( pMan->sError, "Cannot parse a standard gate (expected opening paranthesis)." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
Ver_ParseSkipComments( pMan );
// parse the output name
pWord = Ver_ParseGetName( pMan );
if ( pWord == NULL )
return 0;
// get the net corresponding to this output
pNetLo = Ver_ParseFindNet( pNtk, pWord );
if ( pNetLo == NULL )
{
sprintf( pMan->sError, "Net is missing in gate %s.", pWord );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
// check if it is the end of gate
Ver_ParseSkipComments( pMan );
Symbol = Ver_StreamPopChar(p);
if ( Symbol == ')' )
{
sprintf( pMan->sError, "Cannot parse the flop." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
// skip comma
if ( Symbol != ',' )
{
sprintf( pMan->sError, "Cannot parse the flop." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
Ver_ParseSkipComments( pMan );
// parse the output name
pWord = Ver_ParseGetName( pMan );
if ( pWord == NULL )
return 0;
// get the net corresponding to this output
pNetLi = Ver_ParseFindNet( pNtk, pWord );
if ( pNetLi == NULL )
{
sprintf( pMan->sError, "Net is missing in gate %s.", pWord );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
// check if it is the end of gate
Ver_ParseSkipComments( pMan );
Symbol = Ver_StreamPopChar(p);
if ( Symbol != ')' )
{
sprintf( pMan->sError, "Cannot parse the flop." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
// check if it is the end of gate
Ver_ParseSkipComments( pMan );
if ( Ver_StreamPopChar(p) != ';' )
{
sprintf( pMan->sError, "Cannot parse the flop." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
// create the latch
pLatch = Ver_ParseCreateLatch( pNtk, pNetLi, pNetLo );
Abc_LatchSetInit0( pLatch );
return 1;
}
/**Function*************************************************************
Synopsis [Returns the index of the given pin the gate.] Synopsis [Returns the index of the given pin the gate.]
Description [] Description []
...@@ -1606,6 +1709,12 @@ int Ver_ParseBox( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkBox ) ...@@ -1606,6 +1709,12 @@ int Ver_ParseBox( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkBox )
pNode->pCopy = (Abc_Obj_t *)vBundles; pNode->pCopy = (Abc_Obj_t *)vBundles;
while ( 1 ) while ( 1 )
{ {
/*
if ( Ver_StreamGetLineNumber(pMan->pReader) == 5967 )
{
int x = 0;
}
*/
// allocate the bundle (formal name + array of actual nets) // allocate the bundle (formal name + array of actual nets)
pBundle = ALLOC( Ver_Bundle_t, 1 ); pBundle = ALLOC( Ver_Bundle_t, 1 );
pBundle->pNameFormal = NULL; pBundle->pNameFormal = NULL;
......
src/map/fpga/fpgaLib.c
...@@ -113,10 +113,11 @@ Fpga_LutLib_t * Fpga_LutLibCreate( char * FileName, int fVerbose ) ...@@ -113,10 +113,11 @@ Fpga_LutLib_t * Fpga_LutLibCreate( char * FileName, int fVerbose )
i++; i++;
} }
p->LutMax = i-1; p->LutMax = i-1;
if ( p->LutMax > FPGA_MAX_LEAVES ) if ( p->LutMax > FPGA_MAX_LEAVES )
{ {
p->LutMax = FPGA_MAX_LEAVES; p->LutMax = FPGA_MAX_LEAVES;
printf( "Warning: LUTs with more than %d input will not be used.\n", FPGA_MAX_LEAVES ); printf( "Warning: LUTs with more than %d inputs will not be used.\n", FPGA_MAX_LEAVES );
} }
// check the library // check the library
......
src/misc/extra/extraUtilUtil.c
...@@ -193,7 +193,7 @@ char * Extra_UtilStrsav( char *s ) ...@@ -193,7 +193,7 @@ char * Extra_UtilStrsav( char *s )
Synopsis [util_tilde_expand()] Synopsis [util_tilde_expand()]
Description [] Description [The code contributed by Niklas Sorensson.]
SideEffects [] SideEffects []
...@@ -203,6 +203,32 @@ char * Extra_UtilStrsav( char *s ) ...@@ -203,6 +203,32 @@ char * Extra_UtilStrsav( char *s )
char * Extra_UtilTildeExpand( char *fname ) char * Extra_UtilTildeExpand( char *fname )
{ {
return Extra_UtilStrsav( fname ); return Extra_UtilStrsav( fname );
/*
int n_tildes = 0;
const char* home;
char* expanded;
int length;
int i, j, k;
for (i = 0; i < (int)strlen(fname); i++)
if (fname[i] == '~') n_tildes++;
home = getenv("HOME");
length = n_tildes * strlen(home) + strlen(fname);
expanded = ALLOC(char, length + 1);
j = 0;
for (i = 0; i < (int)strlen(fname); i++){
if (fname[i] == '~'){
for (k = 0; k < (int)strlen(home); k++)
expanded[j++] = home[k];
}else
expanded[j++] = fname[i];
}
expanded[j] = '\0';
return expanded;
*/
} }
/**Function************************************************************* /**Function*************************************************************
......
src/sat/bsat/satSolver.h
...@@ -188,4 +188,22 @@ struct sat_solver_t ...@@ -188,4 +188,22 @@ struct sat_solver_t
int nRoots; int nRoots;
}; };
static int sat_solver_var_value( sat_solver* s, int v )
{
assert( s->model.ptr != NULL && v < s->size );
return (int)(s->model.ptr[v] == l_True);
}
static int sat_solver_var_literal( sat_solver* s, int v )
{
assert( s->model.ptr != NULL && v < s->size );
return toLitCond( v, s->model.ptr[v] != l_True );
}
static void sat_solver_act_var_clear(sat_solver* s)
{
int i;
for (i = 0; i < s->size; i++)
s->activity[i] = 0.0;
s->var_inc = 1.0;
}
#endif #endif
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