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abc
Commit 32314347 by Alan Mishchenko
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Version abc90310

parent c03f9b51
Showing with 2859 additions and 370 deletions
Makefile
......@@ -26,7 +26,7 @@ MODULES := \
src/aig/bdc src/aig/bar src/aig/ntl src/aig/nwk \
src/aig/mfx src/aig/tim src/aig/saig src/aig/bbr \
src/aig/int src/aig/dch src/aig/ssw src/aig/cgt \
src/aig/cec src/aig/gia
src/aig/cec src/aig/gia src/aig/bbl
default: $(PROG)
......
abc.rc
# global parameters
#set check # checks intermediate networks
set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
#set backup # saves backup networks retrived by "undo" and "recall"
#set savesteps 1 # sets the maximum number of backup networks to save
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar
# program names for internal calls
......@@ -110,7 +110,7 @@ alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias rwsat "st; rw -l; b -l; rw -l; rf -l"
alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l"
alias drwsat2 "st; drw; b -l; drw; drf; ifraig -C 20; drw; b -l; drw; drf"
alias share "st; multi -m; fx; resyn2"
# resubstitution scripts for the IWLS paper
......
abcexe.dsp
......@@ -42,7 +42,7 @@ RSC=rc.exe
# PROP Ignore_Export_Lib 0
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c
# ADD BASE RSC /l 0x409 /d "NDEBUG"
# ADD RSC /l 0x409 /d "NDEBUG"
BSC32=bscmake.exe
......@@ -66,7 +66,7 @@ LINK32=link.exe
# PROP Ignore_Export_Lib 0
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c
# ADD BASE RSC /l 0x409 /d "_DEBUG"
# ADD RSC /l 0x409 /d "_DEBUG"
BSC32=bscmake.exe
......
abclib.dsp
......@@ -41,7 +41,7 @@ RSC=rc.exe
# PROP Intermediate_Dir "ReleaseLib"
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_MBCS" /D "_LIB" /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c
# ADD BASE RSC /l 0x409 /d "NDEBUG"
# ADD RSC /l 0x409 /d "NDEBUG"
BSC32=bscmake.exe
......@@ -64,7 +64,7 @@ LIB32=link.exe -lib
# PROP Intermediate_Dir "DebugLib"
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c
# ADD BASE RSC /l 0x409 /d "_DEBUG"
# ADD RSC /l 0x409 /d "_DEBUG"
BSC32=bscmake.exe
......@@ -279,6 +279,10 @@ SOURCE=.\src\base\abci\abcLut.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcLutmin.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcMap.c
# End Source File
# Begin Source File
......@@ -475,6 +479,10 @@ SOURCE=.\src\base\io\ioReadBaf.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadBblif.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadBench.c
# End Source File
# Begin Source File
......@@ -523,6 +531,10 @@ SOURCE=.\src\base\io\ioWriteBaf.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioWriteBblif.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioWriteBench.c
# End Source File
# Begin Source File
......@@ -1927,6 +1939,10 @@ SOURCE=.\src\map\if\ifReduce.c
# End Source File
# Begin Source File
SOURCE=.\src\map\if\ifSeq.c
# End Source File
# Begin Source File
SOURCE=.\src\map\if\ifTime.c
# End Source File
# Begin Source File
......@@ -3519,10 +3535,18 @@ SOURCE=.\src\aig\ssw\sswUnique.c
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\aig\cec\cec.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cec.h
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecCec.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecClass.c
# End Source File
# Begin Source File
......@@ -3535,6 +3559,10 @@ SOURCE=.\src\aig\cec\cecInt.h
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecIso.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecMan.c
# End Source File
# Begin Source File
......@@ -3543,8 +3571,16 @@ SOURCE=.\src\aig\cec\cecPat.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecSim.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecSolve.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecSweep.c
# End Source File
# End Group
# Begin Group "cgt"
......@@ -3586,10 +3622,6 @@ SOURCE=.\src\aig\cgt\cgtSat.c
# PROP Default_Filter ""
# End Group
# Begin Group "fsim"
# PROP Default_Filter ""
# End Group
# Begin Group "gia"
# PROP Default_Filter ""
......@@ -3627,6 +3659,14 @@ SOURCE=.\src\aig\gia\giaEmbed.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaEnable.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaEquiv.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaFanout.c
# End Source File
# Begin Source File
......@@ -3655,6 +3695,10 @@ SOURCE=.\src\aig\gia\giaMan.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaMap.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaScl.c
# End Source File
# Begin Source File
......@@ -3678,6 +3722,18 @@ SOURCE=.\src\aig\gia\giaTsim.c
SOURCE=.\src\aig\gia\giaUtil.c
# End Source File
# End Group
# Begin Group "bbl"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\aig\bbl\bblif.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\bbl\bblif.h
# End Source File
# End Group
# End Group
# End Group
# Begin Group "Header Files"
......
src/aig/bbl/module.make 0 → 100644
SRC += src/aig/bbl/bblif.c
src/aig/cec/cec.h
......@@ -45,24 +45,42 @@ struct Cec_ParSat_t_
int nSatVarMax; // the max number of SAT variables
int nCallsRecycle; // calls to perform before recycling SAT solver
int fPolarFlip; // flops polarity of variables
int fCheckMiter; // the circuit is the miter
int fFirstStop; // stop on the first sat output
int fVerbose; // verbose stats
};
// simulation parameters
typedef struct Cec_ParSim_t_ Cec_ParSim_t;
struct Cec_ParSim_t_
{
int nWords; // the number of simulation words
int nRounds; // the number of simulation rounds
int TimeLimit; // the runtime limit in seconds
int fDoubleOuts; // miter with separate outputs
int fCheckMiter; // the circuit is the miter
int fFirstStop; // stop on the first sat output
int fSeqSimulate; // performs sequential simulation
int fVeryVerbose; // verbose stats
int fVerbose; // verbose stats
};
// combinational SAT sweeping parameters
typedef struct Cec_ParCsw_t_ Cec_ParCsw_t;
struct Cec_ParCsw_t_
typedef struct Cec_ParFra_t_ Cec_ParFra_t;
struct Cec_ParFra_t_
{
int nWords; // the number of simulation words
int nRounds; // the number of simulation rounds
int nItersMax; // the maximum number of iterations of SAT sweeping
int nBTLimit; // conflict limit at a node
int nSatVarMax; // the max number of SAT variables
int nCallsRecycle; // calls to perform before recycling SAT solver
int TimeLimit; // the runtime limit in seconds
int nLevelMax; // restriction on the level nodes to be swept
int nDepthMax; // the depth in terms of steps of speculative reduction
int fRewriting; // enables AIG rewriting
int fCheckMiter; // the circuit is the miter
int fFirstStop; // stop on the first sat output
int fDoubleOuts; // miter with separate outputs
int fColorDiff; // miter with separate outputs
int fVeryVerbose; // verbose stats
int fVerbose; // verbose stats
};
......@@ -71,13 +89,12 @@ struct Cec_ParCsw_t_
typedef struct Cec_ParCec_t_ Cec_ParCec_t;
struct Cec_ParCec_t_
{
int nIters; // iterations of SAT solving/sweeping
int nBTLimitBeg; // starting backtrack limit
int nBTlimitMulti; // multiple of backtrack limit
int nBTLimit; // conflict limit at a node
int TimeLimit; // the runtime limit in seconds
int fFirstStop; // stop on the first sat output
int fUseSmartCnf; // use smart CNF computation
int fRewriting; // enables AIG rewriting
int fSatSweeping; // enables SAT sweeping
int fFirstStop; // stop on the first sat output
int fVeryVerbose; // verbose stats
int fVerbose; // verbose stats
};
......@@ -89,12 +106,17 @@ struct Cec_ParCec_t_
/// FUNCTION DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
/*=== cecCec.c ==========================================================*/
extern int Cec_ManVerify( Gia_Man_t * p, Cec_ParCec_t * pPars );
extern int Cec_ManVerifyTwo( Gia_Man_t * p0, Gia_Man_t * p1, int fVerbose );
/*=== cecCore.c ==========================================================*/
extern void Cec_ManSatSetDefaultParams( Cec_ParSat_t * p );
extern void Cec_ManCswSetDefaultParams( Cec_ParCsw_t * p );
extern void Cec_ManSimSetDefaultParams( Cec_ParSim_t * p );
extern void Cec_ManFraSetDefaultParams( Cec_ParFra_t * p );
extern void Cec_ManCecSetDefaultParams( Cec_ParCec_t * p );
extern Gia_Man_t * Cec_ManSatSweeping( Gia_Man_t * pAig, Cec_ParCsw_t * pPars );
extern Gia_Man_t * Cec_ManSatSweeping( Gia_Man_t * pAig, Cec_ParFra_t * pPars );
extern Gia_Man_t * Cec_ManSatSolving( Gia_Man_t * pAig, Cec_ParSat_t * pPars );
extern void Cec_ManSimulation( Gia_Man_t * pAig, Cec_ParSim_t * pPars );
#ifdef __cplusplus
}
......
src/aig/cec/cecCec.c 0 → 100644
/**CFile****************************************************************
FileName [cecCec.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.]
Synopsis [Integrated combinatinal equivalence checker.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: cecCec.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "cecInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Saves the input pattern with the given number.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cec_ManTransformPattern( Gia_Man_t * p, int iOut, int * pValues )
{
int i;
assert( p->pCexComb == NULL );
p->pCexComb = (Gia_Cex_t *)ABC_CALLOC( char,
sizeof(Gia_Cex_t) + sizeof(unsigned) * Aig_BitWordNum(Gia_ManCiNum(p)) );
p->pCexComb->iPo = iOut;
p->pCexComb->nPis = Gia_ManCiNum(p);
p->pCexComb->nBits = Gia_ManCiNum(p);
for ( i = 0; i < Gia_ManCiNum(p); i++ )
if ( pValues[i] )
Aig_InfoSetBit( p->pCexComb->pData, i );
}
/**Function*************************************************************
Synopsis [Interface to the old CEC engine]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_ManVerifyOld( Gia_Man_t * pMiter, int fVerbose )
{
extern int Fra_FraigCec( Aig_Man_t ** ppAig, int nConfLimit, int fVerbose );
extern int Ssw_SecCexResimulate( Aig_Man_t * p, int * pModel, int * pnOutputs );
Gia_Man_t * pTemp = Gia_ManTransformMiter( pMiter );
Aig_Man_t * pMiterCec = Gia_ManToAig( pTemp );
int RetValue, iOut, nOuts, clkTotal = clock();
Gia_ManStop( pTemp );
// run CEC on this miter
RetValue = Fra_FraigCec( &pMiterCec, 100000, fVerbose );
// report the miter
if ( RetValue == 1 )
{
printf( "Networks are equivalent. " );
ABC_PRT( "Time", clock() - clkTotal );
}
else if ( RetValue == 0 )
{
printf( "Networks are NOT EQUIVALENT. " );
ABC_PRT( "Time", clock() - clkTotal );
if ( pMiterCec->pData == NULL )
printf( "Counter-example is not available.\n" );
else
{
iOut = Ssw_SecCexResimulate( pMiterCec, pMiterCec->pData, &nOuts );
if ( iOut == -1 )
printf( "Counter-example verification has failed.\n" );
else
{
printf( "Primary output %d has failed in frame %d.\n", iOut );
printf( "The counter-example detected %d incorrect outputs.\n", nOuts );
}
Cec_ManTransformPattern( pMiter, iOut, pMiterCec->pData );
}
}
else
{
printf( "Networks are UNDECIDED. " );
ABC_PRT( "Time", clock() - clkTotal );
}
fflush( stdout );
Aig_ManStop( pMiterCec );
return RetValue;
}
/**Function*************************************************************
Synopsis [New CEC engine.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_ManVerify( Gia_Man_t * p, Cec_ParCec_t * pPars )
{
int fDumpUndecided = 1;
Cec_ParFra_t ParsFra, * pParsFra = &ParsFra;
Gia_Man_t * pNew;
int RetValue, clk = clock();
double clkTotal = clock();
// sweep for equivalences
Cec_ManFraSetDefaultParams( pParsFra );
pParsFra->nBTLimit = pPars->nBTLimit;
pParsFra->TimeLimit = pPars->TimeLimit;
pParsFra->fVerbose = pPars->fVerbose;
pParsFra->fCheckMiter = 1;
pParsFra->fFirstStop = 1;
pParsFra->fDoubleOuts = 1;
pNew = Cec_ManSatSweeping( p, pParsFra );
if ( pNew == NULL )
{
if ( !Gia_ManVerifyCounterExample( p, p->pCexComb, 1 ) )
printf( "Counter-example simulation has failed.\n" );
printf( "Networks are NOT EQUIVALENT. " );
ABC_PRT( "Time", clock() - clk );
return 0;
}
if ( Gia_ManAndNum(pNew) == 0 )
{
printf( "Networks are equivalent. " );
ABC_PRT( "Time", clock() - clk );
Gia_ManStop( pNew );
return 1;
}
printf( "Networks are UNDECIDED after the new CEC engine. " );
ABC_PRT( "Time", clock() - clk );
if ( fDumpUndecided )
{
Gia_WriteAiger( pNew, "gia_cec_undecided.aig", 0, 0 );
printf( "The result is written into file \"%s\".\n", "gia_cec_undecided.aig" );
}
if ( pPars->TimeLimit && ((double)clock() - clkTotal)/CLOCKS_PER_SEC >= pPars->TimeLimit )
{
Gia_ManStop( pNew );
return -1;
}
// call other solver
printf( "Calling the old CEC engine.\n" );
fflush( stdout );
RetValue = Cec_ManVerifyOld( pNew, pPars->fVerbose );
p->pCexComb = pNew->pCexComb; pNew->pCexComb = NULL;
if ( p->pCexComb && !Gia_ManVerifyCounterExample( p, p->pCexComb, 1 ) )
printf( "Counter-example simulation has failed.\n" );
Gia_ManStop( pNew );
return RetValue;
}
/**Function*************************************************************
Synopsis [New CEC engine applied to two circuits.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_ManVerifyTwo( Gia_Man_t * p0, Gia_Man_t * p1, int fVerbose )
{
Cec_ParCec_t ParsCec, * pPars = &ParsCec;
Gia_Man_t * pMiter;
int RetValue;
Cec_ManCecSetDefaultParams( pPars );
pPars->fVerbose = fVerbose;
pMiter = Gia_ManMiter( p0, p1, 0, 1, pPars->fVerbose );
if ( pMiter == NULL )
return -1;
RetValue = Cec_ManVerify( pMiter, pPars );
p0->pCexComb = pMiter->pCexComb; pMiter->pCexComb = NULL;
Gia_ManStop( pMiter );
return RetValue;
}
/**Function*************************************************************
Synopsis [New CEC engine applied to two circuits.]
Description [Returns 1 if equivalent, 0 if counter-example, -1 if undecided.
Counter-example is returned in the first manager as pAig0->pSeqModel.
The format is given in Gia_Cex_t (file "abc\src\aig\gia\gia.h").]
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_ManVerifyTwoAigs( Aig_Man_t * pAig0, Aig_Man_t * pAig1, int fVerbose )
{
Gia_Man_t * p0, * p1, * pTemp;
int RetValue;
p0 = Gia_ManFromAig( pAig0 );
p0 = Gia_ManCleanup( pTemp = p0 );
Gia_ManStop( pTemp );
p1 = Gia_ManFromAig( pAig1 );
p1 = Gia_ManCleanup( pTemp = p1 );
Gia_ManStop( pTemp );
RetValue = Cec_ManVerifyTwo( p0, p1, fVerbose );
pAig0->pSeqModel = p0->pCexComb; p0->pCexComb = NULL;
Gia_ManStop( p0 );
Gia_ManStop( p1 );
return RetValue;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/aig/cec/cecInt.h
......@@ -65,6 +65,7 @@ struct Cec_ManPat_t_
int timeSort; // sorting literals
int timePack; // packing into sim info structures
int timeTotal; // total runtime
int timeTotalSave; // total runtime for saving
};
// SAT solving manager
......@@ -100,38 +101,43 @@ struct Cec_ManSat_t_
int timeTotal; // total runtime
};
// combinational sweeping object
typedef struct Cec_ObjCsw_t_ Cec_ObjCsw_t;
struct Cec_ObjCsw_t_
{
int iRepr; // representative node
unsigned iNext : 30; // next node in the class
unsigned iProved : 1; // this node is proved
unsigned iFailed : 1; // this node is failed
unsigned SimNum; // simulation info number
};
// combinational simulation manager
typedef struct Cec_ManCsw_t_ Cec_ManCsw_t;
struct Cec_ManCsw_t_
typedef struct Cec_ManSim_t_ Cec_ManSim_t;
struct Cec_ManSim_t_
{
// parameters
Gia_Man_t * pAig; // the AIG to be used for simulation
Cec_ParCsw_t * pPars; // SAT sweeping parameters
Cec_ParSim_t * pPars; // simulation parameters
int nWords; // the number of simulation words
// equivalence classes
Cec_ObjCsw_t * pObjs; // objects used for SAT sweeping
// recycable memory
int * pSimInfo; // simulation information offsets
unsigned * pMems; // allocated simulaton memory
int nWordsAlloc; // the number of allocated entries
int nMems; // the number of used entries
int nMemsMax; // the max number of used entries
int MemFree; // next free entry
int nWordsOld; // the number of simulation words after previous relink
// bug catcher
Vec_Ptr_t * vCiSimInfo; // CI simulation info
Vec_Ptr_t * vCoSimInfo; // CO simulation info
void ** pCexes; // counter-examples for each output
int iOut; // first failed output
int nOuts; // the number of failed outputs
Gia_Cex_t * pCexComb; // counter-example for the first failed output
// temporaries
Vec_Int_t * vClassOld; // old class numbers
Vec_Int_t * vClassNew; // new class numbers
Vec_Int_t * vClassTemp; // temporary storage
Vec_Int_t * vRefinedC; // refined const reprs
};
// combinational simulation manager
typedef struct Cec_ManFra_t_ Cec_ManFra_t;
struct Cec_ManFra_t_
{
// parameters
Gia_Man_t * pAig; // the AIG to be used for simulation
Cec_ParFra_t * pPars; // SAT sweeping parameters
// simulation patterns
Vec_Int_t * vXorNodes; // nodes used in speculative reduction
int nAllProved; // total number of proved nodes
......@@ -139,6 +145,7 @@ struct Cec_ManCsw_t_
int nAllFailed; // total number of failed nodes
// runtime stats
int timeSim; // unsat
int timePat; // unsat
int timeSat; // sat
int timeTotal; // total runtime
};
......@@ -153,29 +160,31 @@ struct Cec_ManCsw_t_
/*=== cecCore.c ============================================================*/
/*=== cecClass.c ============================================================*/
extern int Cec_ManCswCountLitsAll( Cec_ManCsw_t * p );
extern int * Cec_ManCswDeriveReprs( Cec_ManCsw_t * p );
extern Gia_Man_t * Cec_ManCswSpecReduction( Cec_ManCsw_t * p );
extern Gia_Man_t * Cec_ManCswSpecReductionProved( Cec_ManCsw_t * p );
extern Gia_Man_t * Cec_ManCswDupWithClasses( Cec_ManCsw_t * p );
extern int Cec_ManCswClassesPrepare( Cec_ManCsw_t * p );
extern int Cec_ManCswClassesUpdate( Cec_ManCsw_t * p, Cec_ManPat_t * pPat, Gia_Man_t * pNew );
extern int Cec_ManSimClassesPrepare( Cec_ManSim_t * p );
extern int Cec_ManSimClassesRefine( Cec_ManSim_t * p );
extern int Cec_ManSimSimulateRound( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t * vInfoCos );
/*=== cecIso.c ============================================================*/
extern int * Cec_ManDetectIsomorphism( Gia_Man_t * p );
/*=== cecMan.c ============================================================*/
extern Cec_ManCsw_t * Cec_ManCswStart( Gia_Man_t * pAig, Cec_ParCsw_t * pPars );
extern void Cec_ManCswStop( Cec_ManCsw_t * p );
extern Cec_ManPat_t * Cec_ManPatStart();
extern void Cec_ManPatPrintStats( Cec_ManPat_t * p );
extern void Cec_ManPatStop( Cec_ManPat_t * p );
extern Cec_ManSat_t * Cec_ManSatCreate( Gia_Man_t * pAig, Cec_ParSat_t * pPars );
extern void Cec_ManSatPrintStats( Cec_ManSat_t * p );
extern void Cec_ManSatStop( Cec_ManSat_t * p );
extern Cec_ManPat_t * Cec_ManPatStart();
extern void Cec_ManPatPrintStats( Cec_ManPat_t * p );
extern void Cec_ManPatStop( Cec_ManPat_t * p );
extern Cec_ManSim_t * Cec_ManSimStart( Gia_Man_t * pAig, Cec_ParSim_t * pPars );
extern void Cec_ManSimStop( Cec_ManSim_t * p );
extern Cec_ManFra_t * Cec_ManFraStart( Gia_Man_t * pAig, Cec_ParFra_t * pPars );
extern void Cec_ManFraStop( Cec_ManFra_t * p );
/*=== cecPat.c ============================================================*/
extern void Cec_ManPatSavePattern( Cec_ManPat_t * pPat, Cec_ManSat_t * p, Gia_Obj_t * pObj );
extern Vec_Ptr_t * Cec_ManPatCollectPatterns( Cec_ManPat_t * pMan, int nInputs, int nWords );
/*=== cecSolve.c ============================================================*/
extern int Cec_ObjSatVarValue( Cec_ManSat_t * p, Gia_Obj_t * pObj );
extern void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPars );
/*=== cecUtil.c ============================================================*/
/*=== ceFraeep.c ============================================================*/
extern Gia_Man_t * Cec_ManFraSpecReduction( Cec_ManFra_t * p );
extern int Cec_ManFraClassesUpdate( Cec_ManFra_t * p, Cec_ManSim_t * pSim, Cec_ManPat_t * pPat, Gia_Man_t * pNew );
#ifdef __cplusplus
}
......
src/aig/cec/cecMan.c
......@@ -30,7 +30,7 @@
/**Function*************************************************************
Synopsis [Creates AIG.]
Synopsis [Creates the manager.]
Description []
......@@ -39,26 +39,25 @@
SeeAlso []
***********************************************************************/
Cec_ManCsw_t * Cec_ManCswStart( Gia_Man_t * pAig, Cec_ParCsw_t * pPars )
{
Cec_ManCsw_t * p;
p = ABC_ALLOC( Cec_ManCsw_t, 1 );
memset( p, 0, sizeof(Cec_ManCsw_t) );
p->pAig = pAig;
p->pPars = pPars;
p->pObjs = ABC_CALLOC( Cec_ObjCsw_t, Gia_ManObjNum(pAig) );
// temporaries
p->vClassOld = Vec_IntAlloc( 1000 );
p->vClassNew = Vec_IntAlloc( 1000 );
p->vClassTemp = Vec_IntAlloc( 1000 );
p->vRefinedC = Vec_IntAlloc( 10000 );
p->vXorNodes = Vec_IntAlloc( 1000 );
Cec_ManSat_t * Cec_ManSatCreate( Gia_Man_t * pAig, Cec_ParSat_t * pPars )
{
Cec_ManSat_t * p;
// create interpolation manager
p = ABC_ALLOC( Cec_ManSat_t, 1 );
memset( p, 0, sizeof(Cec_ManSat_t) );
p->pPars = pPars;
p->pAig = pAig;
// SAT solving
p->nSatVars = 1;
p->pSatVars = ABC_CALLOC( int, Gia_ManObjNum(pAig) );
p->vUsedNodes = Vec_PtrAlloc( 1000 );
p->vFanins = Vec_PtrAlloc( 100 );
return p;
}
/**Function*************************************************************
Synopsis [Deletes AIG.]
Synopsis [Prints statistics of the manager.]
Description []
......@@ -67,19 +66,46 @@ Cec_ManCsw_t * Cec_ManCswStart( Gia_Man_t * pAig, Cec_ParCsw_t * pPars )
SeeAlso []
***********************************************************************/
void Cec_ManCswStop( Cec_ManCsw_t * p )
void Cec_ManSatPrintStats( Cec_ManSat_t * p )
{
Vec_IntFree( p->vXorNodes );
Vec_IntFree( p->vClassOld );
Vec_IntFree( p->vClassNew );
Vec_IntFree( p->vClassTemp );
Vec_IntFree( p->vRefinedC );
ABC_FREE( p->pMems );
ABC_FREE( p->pObjs );
printf( "CO = %6d ", Gia_ManCoNum(p->pAig) );
printf( "Conf = %5d ", p->pPars->nBTLimit );
printf( "MinVar = %5d ", p->pPars->nSatVarMax );
printf( "MinCalls = %5d\n", p->pPars->nCallsRecycle );
printf( "Unsat calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatUnsat, 100.0*p->nSatUnsat/p->nSatTotal, p->nSatUnsat? 1.0*p->nConfUnsat/p->nSatUnsat :0.0 );
ABC_PRTP( "Time", p->timeSatUnsat, p->timeTotal );
printf( "Sat calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatSat, 100.0*p->nSatSat/p->nSatTotal, p->nSatSat? 1.0*p->nConfSat/p->nSatSat : 0.0 );
ABC_PRTP( "Time", p->timeSatSat, p->timeTotal );
printf( "Undef calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatUndec, 100.0*p->nSatUndec/p->nSatTotal, p->nSatUndec? 1.0*p->nConfUndec/p->nSatUndec : 0.0 );
ABC_PRTP( "Time", p->timeSatUndec, p->timeTotal );
}
/**Function*************************************************************
Synopsis [Frees the manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cec_ManSatStop( Cec_ManSat_t * p )
{
if ( p->pSat )
sat_solver_delete( p->pSat );
Vec_PtrFree( p->vUsedNodes );
Vec_PtrFree( p->vFanins );
ABC_FREE( p->pSatVars );
ABC_FREE( p );
}
/**Function*************************************************************
Synopsis [Creates AIG.]
......@@ -147,9 +173,11 @@ void Cec_ManPatStop( Cec_ManPat_t * p )
ABC_FREE( p );
}
/**Function*************************************************************
Synopsis [Creates the manager.]
Synopsis [Creates AIG.]
Description []
......@@ -158,25 +186,31 @@ void Cec_ManPatStop( Cec_ManPat_t * p )
SeeAlso []
***********************************************************************/
Cec_ManSat_t * Cec_ManSatCreate( Gia_Man_t * pAig, Cec_ParSat_t * pPars )
{
Cec_ManSat_t * p;
// create interpolation manager
p = ABC_ALLOC( Cec_ManSat_t, 1 );
memset( p, 0, sizeof(Cec_ManSat_t) );
p->pPars = pPars;
p->pAig = pAig;
// SAT solving
p->nSatVars = 1;
p->pSatVars = ABC_CALLOC( int, Gia_ManObjNum(pAig) );
p->vUsedNodes = Vec_PtrAlloc( 1000 );
p->vFanins = Vec_PtrAlloc( 100 );
Cec_ManSim_t * Cec_ManSimStart( Gia_Man_t * pAig, Cec_ParSim_t * pPars )
{
Cec_ManSim_t * p;
p = ABC_ALLOC( Cec_ManSim_t, 1 );
memset( p, 0, sizeof(Cec_ManSim_t) );
p->pAig = pAig;
p->pPars = pPars;
p->pSimInfo = ABC_CALLOC( int, Gia_ManObjNum(pAig) );
p->vClassOld = Vec_IntAlloc( 1000 );
p->vClassNew = Vec_IntAlloc( 1000 );
p->vClassTemp = Vec_IntAlloc( 1000 );
p->vRefinedC = Vec_IntAlloc( 10000 );
p->vCiSimInfo = Vec_PtrAllocSimInfo( Gia_ManCiNum(p->pAig), pPars->nWords );
if ( pPars->fCheckMiter || Gia_ManRegNum(p->pAig) )
{
p->vCoSimInfo = Vec_PtrAllocSimInfo( Gia_ManCoNum(p->pAig), pPars->nWords );
Vec_PtrCleanSimInfo( p->vCoSimInfo, 0, pPars->nWords );
}
p->iOut = -1;
return p;
}
/**Function*************************************************************
Synopsis [Prints statistics of the manager.]
Synopsis [Deletes AIG.]
Description []
......@@ -185,26 +219,27 @@ Cec_ManSat_t * Cec_ManSatCreate( Gia_Man_t * pAig, Cec_ParSat_t * pPars )
SeeAlso []
***********************************************************************/
void Cec_ManSatPrintStats( Cec_ManSat_t * p )
void Cec_ManSimStop( Cec_ManSim_t * p )
{
printf( "CO = %6d ", Gia_ManCoNum(p->pAig) );
printf( "Conf = %5d ", p->pPars->nBTLimit );
printf( "MinVar = %5d ", p->pPars->nSatVarMax );
printf( "MinCalls = %5d\n", p->pPars->nCallsRecycle );
printf( "Unsat calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatUnsat, 100.0*p->nSatUnsat/p->nSatTotal, p->nSatUnsat? 1.0*p->nConfUnsat/p->nSatUnsat :0.0 );
ABC_PRTP( "Time", p->timeSatUnsat, p->timeTotal );
printf( "Sat calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatSat, 100.0*p->nSatSat/p->nSatTotal, p->nSatSat? 1.0*p->nConfSat/p->nSatSat : 0.0 );
ABC_PRTP( "Time", p->timeSatSat, p->timeTotal );
printf( "Undef calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatUndec, 100.0*p->nSatUndec/p->nSatTotal, p->nSatUndec? 1.0*p->nConfUndec/p->nSatUndec : 0.0 );
ABC_PRTP( "Time", p->timeSatUndec, p->timeTotal );
Vec_IntFree( p->vClassOld );
Vec_IntFree( p->vClassNew );
Vec_IntFree( p->vClassTemp );
Vec_IntFree( p->vRefinedC );
if ( p->vCiSimInfo )
Vec_PtrFree( p->vCiSimInfo );
if ( p->vCoSimInfo )
Vec_PtrFree( p->vCoSimInfo );
ABC_FREE( p->pCexComb );
ABC_FREE( p->pCexes );
ABC_FREE( p->pMems );
ABC_FREE( p->pSimInfo );
ABC_FREE( p );
}
/**Function*************************************************************
Synopsis [Frees the manager.]
Synopsis [Creates AIG.]
Description []
......@@ -213,16 +248,35 @@ void Cec_ManSatPrintStats( Cec_ManSat_t * p )
SeeAlso []
***********************************************************************/
void Cec_ManSatStop( Cec_ManSat_t * p )
Cec_ManFra_t * Cec_ManFraStart( Gia_Man_t * pAig, Cec_ParFra_t * pPars )
{
Cec_ManFra_t * p;
p = ABC_ALLOC( Cec_ManFra_t, 1 );
memset( p, 0, sizeof(Cec_ManFra_t) );
p->pAig = pAig;
p->pPars = pPars;
p->vXorNodes = Vec_IntAlloc( 1000 );
return p;
}
/**Function*************************************************************
Synopsis [Deletes AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cec_ManFraStop( Cec_ManFra_t * p )
{
if ( p->pSat )
sat_solver_delete( p->pSat );
Vec_PtrFree( p->vUsedNodes );
Vec_PtrFree( p->vFanins );
ABC_FREE( p->pSatVars );
Vec_IntFree( p->vXorNodes );
ABC_FREE( p );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
......
src/aig/cec/cecPat.c
/**CFile****************************************************************
FileName [cec.c]
FileName [cecPat.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.]
Synopsis []
Synopsis [Simulation pattern manager.]
Author [Alan Mishchenko]
......@@ -14,7 +14,7 @@
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: cec.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
Revision [$Id: cecPat.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
......
src/aig/cec/cecSim.c 0 → 100644
/**CFile****************************************************************
FileName [cecSim.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinatinoal equivalence checking.]
Synopsis [Simulation manager.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: cecSim.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "cecInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/aig/cec/cecSolve.c
......@@ -390,6 +390,70 @@ void Cec_ManSatSolverRecycle( Cec_ManSat_t * p )
/**Function*************************************************************
Synopsis [Sets variable activities in the cone.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cec_SetActivityFactors_rec( Cec_ManSat_t * p, Gia_Obj_t * pObj, int LevelMin, int LevelMax )
{
float dActConeBumpMax = 20.0;
int iVar;
// skip visited variables
if ( Gia_ObjIsTravIdCurrent(p->pAig, pObj) )
return;
Gia_ObjSetTravIdCurrent(p->pAig, pObj);
// add the PI to the list
if ( Gia_ObjLevel(p->pAig, pObj) <= LevelMin || Gia_ObjIsCi(pObj) )
return;
// set the factor of this variable
// (LevelMax-LevelMin) / (pObj->Level-LevelMin) = p->pPars->dActConeBumpMax / ThisBump
if ( (iVar = Cec_ObjSatNum(p,pObj)) )
{
p->pSat->factors[iVar] = dActConeBumpMax * (Gia_ObjLevel(p->pAig, pObj) - LevelMin)/(LevelMax - LevelMin);
veci_push(&p->pSat->act_vars, iVar);
}
// explore the fanins
Cec_SetActivityFactors_rec( p, Gia_ObjFanin0(pObj), LevelMin, LevelMax );
Cec_SetActivityFactors_rec( p, Gia_ObjFanin1(pObj), LevelMin, LevelMax );
}
/**Function*************************************************************
Synopsis [Sets variable activities in the cone.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_SetActivityFactors( Cec_ManSat_t * p, Gia_Obj_t * pObj )
{
float dActConeRatio = 0.5;
int LevelMin, LevelMax;
// reset the active variables
veci_resize(&p->pSat->act_vars, 0);
// prepare for traversal
Gia_ManIncrementTravId( p->pAig );
// determine the min and max level to visit
assert( dActConeRatio > 0 && dActConeRatio < 1 );
LevelMax = Gia_ObjLevel(p->pAig,pObj);
LevelMin = (int)(LevelMax * (1.0 - dActConeRatio));
// traverse
Cec_SetActivityFactors_rec( p, pObj, LevelMin, LevelMax );
//Cec_PrintActivity( p );
return 1;
}
/**Function*************************************************************
Synopsis [Runs equivalence test for the two nodes.]
Description []
......@@ -402,7 +466,7 @@ void Cec_ManSatSolverRecycle( Cec_ManSat_t * p )
int Cec_ManSatCheckNode( Cec_ManSat_t * p, Gia_Obj_t * pObj )
{
int nBTLimit = p->pPars->nBTLimit;
int Lit, RetValue, status, clk, nConflicts;
int Lit, RetValue, status, clk, clk2, nConflicts;
p->nCallsSince++; // experiment with this!!!
p->nSatTotal++;
......@@ -415,7 +479,14 @@ int Cec_ManSatCheckNode( Cec_ManSat_t * p, Gia_Obj_t * pObj )
Cec_ManSatSolverRecycle( p );
// if the nodes do not have SAT variables, allocate them
clk2 = clock();
Cec_CnfNodeAddToSolver( p, Gia_ObjFanin0(pObj) );
//ABC_PRT( "cnf", clock() - clk2 );
//printf( "%d \n", p->pSat->size );
clk2 = clock();
// Cec_SetActivityFactors( p, Gia_ObjFanin0(pObj) );
//ABC_PRT( "act", clock() - clk2 );
// propage unit clauses
if ( p->pSat->qtail != p->pSat->qhead )
......@@ -435,8 +506,12 @@ int Cec_ManSatCheckNode( Cec_ManSat_t * p, Gia_Obj_t * pObj )
//Sat_SolverWriteDimacs( p->pSat, "temp.cnf", pLits, pLits + 2, 1 );
clk = clock();
nConflicts = p->pSat->stats.conflicts;
clk2 = clock();
RetValue = sat_solver_solve( p->pSat, &Lit, &Lit + 1,
(ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
//ABC_PRT( "sat", clock() - clk2 );
if ( RetValue == l_False )
{
p->timeSatUnsat += clock() - clk;
......@@ -466,6 +541,7 @@ p->timeSatUndec += clock() - clk;
}
}
/**Function*************************************************************
Synopsis [Performs one round of solving for the POs of the AIG.]
......@@ -486,7 +562,7 @@ void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPar
Bar_Progress_t * pProgress = NULL;
Cec_ManSat_t * p;
Gia_Obj_t * pObj;
int i, status, clk = clock();
int i, status, clk = clock(), clk2;
// sprintf( Buffer, "gia%03d.aig", Counter++ );
//Gia_WriteAiger( pAig, Buffer, 0, 0 );
......@@ -499,8 +575,9 @@ void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPar
pPat->nPats = 0;
pPat->nPatLits = 0;
pPat->nPatLitsMin = 0;
}
}
Gia_ManSetPhase( pAig );
Gia_ManLevelNum( pAig );
Gia_ManResetTravId( pAig );
p = Cec_ManSatCreate( pAig, pPars );
pProgress = Bar_ProgressStart( stdout, Gia_ManPoNum(pAig) );
......@@ -512,13 +589,19 @@ void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPar
pObj->fMark1 = 1;
continue;
}
//printf( "Output %6d : ", i );
Bar_ProgressUpdate( pProgress, i, "SAT..." );
clk2 = clock();
status = Cec_ManSatCheckNode( p, pObj );
pObj->fMark0 = (status == 0);
pObj->fMark1 = (status == 1);
/*
printf( "Output %6d : ", i );
printf( "conf = %6d ", p->pSat->stats.conflicts );
printf( "prop = %6d ", p->pSat->stats.propagations );
ABC_PRT( "time", clock() - clk2 );
*/
/*
if ( status == -1 )
{
Gia_Man_t * pTemp = Gia_ManDupDfsCone( pAig, pObj );
......@@ -531,7 +614,11 @@ void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPar
continue;
// save the pattern
if ( pPat )
{
int clk3 = clock();
Cec_ManPatSavePattern( pPat, p, pObj );
pPat->timeTotalSave += clock() - clk3;
}
// quit if one of them is solved
if ( pPars->fFirstStop )
break;
......
src/aig/cec/module.make
SRC += src/aig/cec/cecClass.c \
SRC += src/aig/cec/cecCec.c \
src/aig/cec/cecClass.c \
src/aig/cec/cecCore.c \
src/aig/cec/cecIso.c \
src/aig/cec/cecMan.c \
src/aig/cec/cecPat.c \
src/aig/cec/cecSolve.c
src/aig/cec/cecSim.c \
src/aig/cec/cecSolve.c \
src/aig/cec/cecSweep.c
src/aig/dar/darRefact.c
......@@ -113,7 +113,7 @@ Ref_Man_t * Dar_ManRefStart( Aig_Man_t * pAig, Dar_RefPar_t * pPars )
// other data
p->vCuts = Vec_VecStart( pPars->nCutsMax );
p->vTruthElem = Vec_PtrAllocTruthTables( pPars->nLeafMax );
p->vTruthStore = Vec_PtrAllocSimInfo( 256, Kit_TruthWordNum(pPars->nLeafMax) );
p->vTruthStore = Vec_PtrAllocSimInfo( 1024, Kit_TruthWordNum(pPars->nLeafMax) );
p->vMemory = Vec_IntAlloc( 1 << 16 );
p->vCutNodes = Vec_PtrAlloc( 256 );
p->vLeavesBest = Vec_PtrAlloc( pPars->nLeafMax );
......
src/aig/gia/giaAig.c
......@@ -92,10 +92,9 @@ Gia_Man_t * Gia_ManFromAig( Aig_Man_t * p )
}
// add logic for the POs
Aig_ManForEachPo( p, pObj, i )
{
Gia_ManFromAig_rec( pNew, Aig_ObjFanin0(pObj) );
Aig_ManForEachPo( p, pObj, i )
Gia_ManAppendCo( pNew, Gia_ObjChild0Copy(pObj) );
}
Gia_ManSetRegNum( pNew, Aig_ManRegNum(p) );
return pNew;
}
......@@ -133,10 +132,9 @@ Gia_Man_t * Gia_ManFromAigSwitch( Aig_Man_t * p )
}
// add logic for the POs
Aig_ManForEachPo( p, pObj, i )
{
Gia_ManFromAig_rec( pNew, Aig_ObjFanin0(pObj) );
Aig_ManForEachPo( p, pObj, i )
Gia_ManAppendCo( pNew, Gia_ObjChild0Copy(pObj) );
}
Gia_ManSetRegNum( pNew, Aig_ManRegNum(p) );
return pNew;
}
......
src/aig/gia/giaAiger.c
......@@ -175,6 +175,120 @@ char * Gia_TimeStamp()
/**Function*************************************************************
Synopsis [Read integer from the string.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ReadInt( unsigned char * pPos )
{
int i, Value = 0;
for ( i = 0; i < 4; i++ )
Value = (Value << 8) | *pPos++;
return Value;
}
/**Function*************************************************************
Synopsis [Read equivalence classes from the string.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Rpr_t * Gia_ReadEquivClasses( unsigned char ** ppPos, int nSize )
{
Gia_Rpr_t * pReprs;
unsigned char * pStop;
int i, Item, fProved, iRepr, iNode;
pStop = *ppPos;
pStop += Gia_ReadInt( *ppPos ); *ppPos += 4;
pReprs = ABC_CALLOC( Gia_Rpr_t, nSize );
for ( i = 0; i < nSize; i++ )
pReprs[i].iRepr = GIA_VOID;
iRepr = iNode = 0;
while ( *ppPos < pStop )
{
Item = Gia_ReadAigerDecode( ppPos );
if ( Item & 1 )
{
iRepr += (Item >> 1);
iNode = iRepr;
//printf( "\nRepr = %d ", iRepr );
continue;
}
Item >>= 1;
fProved = (Item & 1);
Item >>= 1;
iNode += Item;
pReprs[iNode].fProved = fProved;
pReprs[iNode].iRepr = iRepr;
//printf( "Node = %d ", iNode );
}
return pReprs;
}
/**Function*************************************************************
Synopsis [Reads decoded value.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
unsigned Gia_ReadDiffValue( char ** ppPos, int iPrev )
{
int Item = Gia_ReadAigerDecode( ppPos );
if ( Item & 1 )
return iPrev + (Item >> 1);
return iPrev - (Item >> 1);
}
/**Function*************************************************************
Synopsis [Read equivalence classes from the string.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int * Gia_ReadMapping( unsigned char ** ppPos, int nSize )
{
int * pMapping;
unsigned char * pStop;
int k, j, nFanins, nAlloc, iNode = 0, iOffset = nSize;
pStop = *ppPos;
pStop += Gia_ReadInt( *ppPos ); *ppPos += 4;
nAlloc = nSize + pStop - *ppPos;
pMapping = ABC_CALLOC( int, nAlloc );
while ( *ppPos < pStop )
{
k = iOffset;
pMapping[k++] = nFanins = Gia_ReadAigerDecode( ppPos );
for ( j = 0; j <= nFanins; j++ )
pMapping[k++] = iNode = Gia_ReadDiffValue( ppPos, iNode );
pMapping[iNode] = iOffset;
iOffset = k;
}
assert( iOffset <= nAlloc );
return pMapping;
}
/**Function*************************************************************
Synopsis [Reads the AIG in the binary AIGER format.]
Description []
......@@ -328,6 +442,38 @@ Gia_Man_t * Gia_ReadAiger( char * pFileName, int fCheck )
// create the latches
Gia_ManSetRegNum( pNew, nLatches );
// check if there are other types of information to read
pCur = pSymbols;
if ( pCur + 1 < pContents + nFileSize && *pCur == 'c' )
{
pCur++;
if ( *pCur == 'e' )
{
pCur++;
// read equivalence classes
pNew->pReprs = Gia_ReadEquivClasses( &pCur, Gia_ManObjNum(pNew) );
pNew->pNexts = Gia_ManDeriveNexts( pNew );
}
if ( *pCur == 'm' )
{
pCur++;
// read mapping
pNew->pMapping = Gia_ReadMapping( &pCur, Gia_ManObjNum(pNew) );
}
if ( *pCur == 'p' )
{
pCur++;
// read placement
}
if ( *pCur == 'n' )
{
pCur++;
// read model name
ABC_FREE( pNew->pName );
pNew->pName = Aig_UtilStrsav( pCur );
}
}
// skipping the comments
ABC_FREE( pContents );
Vec_IntFree( vNodes );
......@@ -443,6 +589,144 @@ Vec_Str_t * Gia_WriteEncodeLiterals( Vec_Int_t * vLits )
/**Function*************************************************************
Synopsis [Write integer into the string.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_WriteInt( unsigned char * pPos, int Value )
{
int i;
for ( i = 3; i >= 0; i-- )
*pPos++ = (Value >> (8*i)) & 255;
}
/**Function*************************************************************
Synopsis [Read equivalence classes from the string.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
unsigned char * Gia_WriteEquivClasses( Gia_Man_t * p, int * pEquivSize )
{
unsigned char * pBuffer;
int iRepr, iNode, iPrevRepr, iPrevNode, iLit, nItems, iPos;
assert( p->pReprs && p->pNexts );
// count the number of entries to be written
nItems = 0;
for ( iRepr = 1; iRepr < Gia_ManObjNum(p); iRepr++ )
{
nItems += Gia_ObjIsConst( p, iRepr );
if ( !Gia_ObjIsHead(p, iRepr) )
continue;
Gia_ClassForEachObj( p, iRepr, iNode )
nItems++;
}
pBuffer = ABC_ALLOC( char, sizeof(int) * (nItems + 1) );
// write constant class
iPos = Gia_WriteAigerEncode( pBuffer, 4, Gia_Var2Lit(0, 1) );
//printf( "\nRepr = %d ", 0 );
iPrevNode = 0;
for ( iNode = 1; iNode < Gia_ManObjNum(p); iNode++ )
if ( Gia_ObjIsConst(p, iNode) )
{
//printf( "Node = %d ", iNode );
iLit = Gia_Var2Lit( iNode - iPrevNode, Gia_ObjProved(p, iNode) );
iPrevNode = iNode;
iPos = Gia_WriteAigerEncode( pBuffer, iPos, Gia_Var2Lit(iLit, 0) );
}
// write non-constant classes
iPrevRepr = 0;
Gia_ManForEachClass( p, iRepr )
{
//printf( "\nRepr = %d ", iRepr );
iPos = Gia_WriteAigerEncode( pBuffer, iPos, Gia_Var2Lit(iRepr - iPrevRepr, 1) );
iPrevRepr = iPrevNode = iRepr;
Gia_ClassForEachObj1( p, iRepr, iNode )
{
//printf( "Node = %d ", iNode );
iLit = Gia_Var2Lit( iNode - iPrevNode, Gia_ObjProved(p, iNode) );
iPrevNode = iNode;
iPos = Gia_WriteAigerEncode( pBuffer, iPos, Gia_Var2Lit(iLit, 0) );
}
}
Gia_WriteInt( pBuffer, iPos );
*pEquivSize = iPos;
return pBuffer;
}
/**Function*************************************************************
Synopsis [Reads decoded value.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_WriteDiffValue( char * pPos, int iPos, int iPrev, int iThis )
{
if ( iPrev < iThis )
return Gia_WriteAigerEncode( pPos, iPos, Gia_Var2Lit(iThis - iPrev, 1) );
return Gia_WriteAigerEncode( pPos, iPos, Gia_Var2Lit(iPrev - iThis, 0) );
}
/**Function*************************************************************
Synopsis [Read equivalence classes from the string.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
unsigned char * Gia_WriteMapping( Gia_Man_t * p, int * pMapSize )
{
unsigned char * pBuffer;
int i, k, iPrev, iFan, nItems, iPos = 4;
assert( p->pMapping );
// count the number of entries to be written
nItems = 0;
Gia_ManForEachGate( p, i )
nItems += 2 + Gia_ObjGateSize( p, i );
pBuffer = ABC_ALLOC( char, sizeof(int) * (nItems + 1) );
// write non-constant classes
iPrev = 0;
Gia_ManForEachGate( p, i )
{
//printf( "\nSize = %d ", Gia_ObjGateSize(p, i) );
iPos = Gia_WriteAigerEncode( pBuffer, iPos, Gia_ObjGateSize(p, i) );
Gia_GateForEachFanin( p, i, iFan, k )
{
//printf( "Fan = %d ", iFan );
iPos = Gia_WriteDiffValue( pBuffer, iPos, iPrev, iFan );
iPrev = iFan;
}
iPos = Gia_WriteDiffValue( pBuffer, iPos, iPrev, i );
iPrev = i;
//printf( "Node = %d ", i );
}
//printf( "\n" );
Gia_WriteInt( pBuffer, iPos );
*pMapSize = iPos;
return pBuffer;
}
/**Function*************************************************************
Synopsis [Writes the AIG in the binary AIGER format.]
Description []
......@@ -536,10 +820,29 @@ void Gia_WriteAiger( Gia_Man_t * pInit, char * pFileName, int fWriteSymbols, int
ABC_FREE( pBuffer );
// write the comment
fprintf( pFile, "c\n" );
fprintf( pFile, "c" );
// write equivalences
if ( p->pReprs && p->pNexts )
{
int nEquivSize;
unsigned char * pEquivs = Gia_WriteEquivClasses( p, &nEquivSize );
fprintf( pFile, "e" );
fwrite( pEquivs, 1, nEquivSize, pFile );
ABC_FREE( pEquivs );
}
// write mapping
if ( p->pMapping )
{
int nMapSize;
unsigned char * pMaps = Gia_WriteMapping( p, &nMapSize );
fprintf( pFile, "m" );
fwrite( pMaps, 1, nMapSize, pFile );
ABC_FREE( pMaps );
}
// write placement
if ( p->pName )
fprintf( pFile, ".model %s\n", p->pName );
fprintf( pFile, "This file was produced by the AIG package on %s\n", Gia_TimeStamp() );
fprintf( pFile, "n%s%c", p->pName, '\0' );
fprintf( pFile, "\nThis file was produced by the GIA package in ABC on %s\n", Gia_TimeStamp() );
fprintf( pFile, "For information about AIGER format, refer to %s\n", "http://fmv.jku.at/aiger" );
fclose( pFile );
if ( p != pInit )
......
src/aig/gia/giaCof.c
......@@ -41,6 +41,7 @@ struct Cof_Obj_t_
unsigned fMark1 : 1; // second user-controlled mark
unsigned nFanins : 4; // the number of fanins
unsigned nFanouts : 24; // total number of fanouts
unsigned nFanoutsM; // total number of MUX ctrl fanouts
unsigned Value; // application specific data
int Id; // ID of the node
int iNext; // next one in the linked list
......@@ -124,6 +125,7 @@ Cof_Man_t * Cof_ManCreateLogicSimple( Gia_Man_t * pGia )
Cof_Man_t * p;
Cof_Obj_t * pObjLog, * pFanLog;
Gia_Obj_t * pObj;
int * pMuxRefs;
int i, iHandle = 0;
p = ABC_CALLOC( Cof_Man_t, 1 );
p->pGia = pGia;
......@@ -173,11 +175,14 @@ Cof_Man_t * Cof_ManCreateLogicSimple( Gia_Man_t * pGia )
p->nObjs++;
}
assert( iHandle == p->nObjData );
pMuxRefs = Gia_ManCreateMuxRefs( pGia );
Gia_ManForEachObj( pGia, pObj, i )
{
pObjLog = Cof_ManObj( p, Gia_ObjHandle(pObj) );
assert( pObjLog->nFanouts == pObjLog->Value );
pObjLog->nFanoutsM = pMuxRefs[i];
}
ABC_FREE( pMuxRefs );
return p;
}
......@@ -509,8 +514,7 @@ int Cof_ManCountRemoved( Cof_Man_t * p, Cof_Obj_t * pRoot, int fConst1 )
void Cof_ManPrintHighFanoutOne( Cof_Man_t * p, Cof_Obj_t * pObj )
{
printf( "%7d : ", pObj->Id );
printf( "fi =%2d ", Cof_ObjFaninNum(pObj) );
printf( "fo =%5d ", Cof_ObjFanoutNum(pObj) );
printf( "i/o/c =%2d %5d %5d ", Cof_ObjFaninNum(pObj), Cof_ObjFanoutNum(pObj), 2*pObj->nFanoutsM );
printf( "l =%4d ", Cof_ObjLevel(p, pObj) );
printf( "s =%5d ", Cof_ManSuppSize(p, &pObj, 1) );
printf( "TFI =%7d ", Cof_ManTfiSize(p, &pObj, 1) );
......
src/aig/gia/giaDup.c
......@@ -196,11 +196,11 @@ int Gia_ManDupDfs_rec( Gia_Man_t * pNew, Gia_Man_t * p, Gia_Obj_t * pObj )
{
if ( ~pObj->Value )
return pObj->Value;
if ( p->pReprs && ~p->pReprs[Gia_ObjId(p, pObj)] )
if ( p->pReprsOld && ~p->pReprsOld[Gia_ObjId(p, pObj)] )
{
Gia_Obj_t * pRepr = Gia_ManObj( p, p->pReprs[Gia_ObjId(p, pObj)] );
pObj->Value = Gia_ManDupDfs_rec( pNew, p, pRepr );
return pObj->Value = Gia_LitNotCond( pObj->Value, Gia_ObjPhaseReal(pRepr) ^ Gia_ObjPhaseReal(pObj) );
Gia_Obj_t * pRepr = Gia_ManObj( p, p->pReprsOld[Gia_ObjId(p, pObj)] );
pRepr->Value = Gia_ManDupDfs_rec( pNew, p, pRepr );
return pObj->Value = Gia_LitNotCond( pRepr->Value, Gia_ObjPhaseReal(pRepr) ^ Gia_ObjPhaseReal(pObj) );
}
if ( Gia_ObjIsCi(pObj) )
return pObj->Value = Gia_ManAppendCi(pNew);
......@@ -380,7 +380,7 @@ Gia_Man_t * Gia_ManDupNormalized( Gia_Man_t * p )
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManDupTrimmed( Gia_Man_t * p )
Gia_Man_t * Gia_ManDupTrimmed( Gia_Man_t * p, int fTrimCis, int fTrimCos )
{
Gia_Man_t * pNew;
Gia_Obj_t * pObj;
......@@ -391,12 +391,12 @@ Gia_Man_t * Gia_ManDupTrimmed( Gia_Man_t * p )
Gia_ManSetRefs( p );
Gia_ManConst0(p)->Value = 0;
Gia_ManForEachCi( p, pObj, i )
if ( pObj->Value > 0 || Gia_ObjIsRo(p, pObj) )
if ( !fTrimCis || pObj->Value > 0 || Gia_ObjIsRo(p, pObj) )
pObj->Value = Gia_ManAppendCi(pNew);
Gia_ManForEachAnd( p, pObj, i )
pObj->Value = Gia_ManAppendAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
Gia_ManForEachCo( p, pObj, i )
if ( !Gia_ObjIsConst0(Gia_ObjFanin0(pObj)) || Gia_ObjIsRi(p, pObj) )
if ( !fTrimCos || !Gia_ObjIsConst0(Gia_ObjFanin0(pObj)) || Gia_ObjIsRi(p, pObj) )
pObj->Value = Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
Gia_ManSetRegNum( pNew, Gia_ManRegNum(p) );
return pNew;
......@@ -413,11 +413,16 @@ Gia_Man_t * Gia_ManDupTrimmed( Gia_Man_t * p )
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManDupCofactored( Gia_Man_t * p, int iVar )
Gia_Man_t * Gia_ManDupCofactored( Gia_Man_t * p, int iVar, int nLimFan )
{
Gia_Man_t * pNew, * pTemp;
Gia_Obj_t * pObj, * pPivot;
int i, iCofVar = -1;
if ( nLimFan > 0 )
{
printf( "This feature is not implemented.\n" );
return NULL;
}
if ( !(iVar > 0 && iVar < Gia_ManObjNum(p)) )
{
printf( "Gia_ManDupCofactored(): Variable %d is out of range (%d; %d).\n", iVar, 0, Gia_ManObjNum(p) );
......@@ -502,7 +507,7 @@ void Gia_ManPrintRepr( Gia_Man_t * p )
Gia_Obj_t * pObj;
int i;
Gia_ManForEachObj( p, pObj, i )
if ( ~p->pReprs[i] )
if ( ~p->pReprsOld[i] )
printf( "%d->%d ", i, p->pReprs[i] );
printf( "\n" );
}
......@@ -569,7 +574,7 @@ Gia_Man_t * Gia_ManDupDfsClasses( Gia_Man_t * p )
Gia_Man_t * pNew, * pTemp;
Gia_Obj_t * pObj;
int i;
assert( p->pReprs != NULL );
assert( p->pReprsOld != NULL );
Gia_ManFillValue( p );
pNew = Gia_ManStart( Gia_ManObjNum(p) );
pNew->pName = Aig_UtilStrsav( p->pName );
......@@ -719,6 +724,195 @@ Gia_Man_t * Gia_ManDupTopAnd( Gia_Man_t * p, int fVerbose )
}
/**Function*************************************************************
Synopsis [Duplicates the AIG in the DFS order.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManMiter_rec( Gia_Man_t * pNew, Gia_Man_t * p, Gia_Obj_t * pObj )
{
if ( ~pObj->Value )
return pObj->Value;
assert( Gia_ObjIsAnd(pObj) );
Gia_ManMiter_rec( pNew, p, Gia_ObjFanin0(pObj) );
Gia_ManMiter_rec( pNew, p, Gia_ObjFanin1(pObj) );
return pObj->Value = Gia_ManHashAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
}
/**Function*************************************************************
Synopsis [Creates miter of two designs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManMiter( Gia_Man_t * p0, Gia_Man_t * p1, int fXorOuts, int fComb, int fVerbose )
{
Gia_Man_t * pNew, * pTemp;
Gia_Obj_t * pObj;
int i, iLit;
if ( fComb )
{
if ( Gia_ManCiNum(p0) != Gia_ManCiNum(p1) )
{
printf( "Gia_ManMiter(): Designs have different number of CIs.\n" );
return NULL;
}
if ( Gia_ManCoNum(p0) != Gia_ManCoNum(p1) )
{
printf( "Gia_ManMiter(): Designs have different number of COs.\n" );
return NULL;
}
}
else
{
if ( Gia_ManPiNum(p0) != Gia_ManPiNum(p1) )
{
printf( "Gia_ManMiter(): Designs have different number of PIs.\n" );
return NULL;
}
if ( Gia_ManPoNum(p0) != Gia_ManPoNum(p1) )
{
printf( "Gia_ManMiter(): Designs have different number of POs.\n" );
return NULL;
}
if ( Gia_ManRegNum(p0) == 0 || Gia_ManRegNum(p1) == 0 )
{
printf( "Gia_ManMiter(): At least one of the designs has no registers.\n" );
return NULL;
}
}
// start the manager
pNew = Gia_ManStart( Gia_ManObjNum(p0) + Gia_ManObjNum(p1) );
pNew->pName = Aig_UtilStrsav( "miter" );
// map combinational inputs
Gia_ManFillValue( p0 );
Gia_ManFillValue( p1 );
Gia_ManConst0(p0)->Value = 0;
Gia_ManConst0(p1)->Value = 0;
// map internal nodes and outputs
Gia_ManHashAlloc( pNew );
if ( fComb )
{
// create combinational inputs
Gia_ManForEachCi( p0, pObj, i )
pObj->Value = Gia_ManAppendCi( pNew );
Gia_ManForEachCi( p1, pObj, i )
pObj->Value = Gia_ObjToLit( pNew, Gia_ManCi(pNew, i) );
// create combinational outputs
Gia_ManForEachCo( p0, pObj, i )
{
Gia_ManMiter_rec( pNew, p0, Gia_ObjFanin0(pObj) );
Gia_ManMiter_rec( pNew, p1, Gia_ObjFanin0(Gia_ManCo(p1,i)) );
if ( fXorOuts )
{
iLit = Gia_ManHashXor( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin0Copy(Gia_ManCo(p1,i)) );
Gia_ManAppendCo( pNew, iLit );
}
else
{
Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(Gia_ManCo(p1,i)) );
}
}
}
else
{
// create primary inputs
Gia_ManForEachPi( p0, pObj, i )
pObj->Value = Gia_ManAppendCi( pNew );
Gia_ManForEachPi( p1, pObj, i )
pObj->Value = Gia_ObjToLit( pNew, Gia_ManPi(pNew, i) );
// create latch outputs
Gia_ManForEachRo( p0, pObj, i )
pObj->Value = Gia_ManAppendCi( pNew );
Gia_ManForEachRo( p1, pObj, i )
pObj->Value = Gia_ManAppendCi( pNew );
// create primary outputs
Gia_ManForEachPo( p0, pObj, i )
{
Gia_ManMiter_rec( pNew, p0, Gia_ObjFanin0(pObj) );
Gia_ManMiter_rec( pNew, p1, Gia_ObjFanin0(Gia_ManPo(p1,i)) );
if ( fXorOuts )
{
iLit = Gia_ManHashXor( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin0Copy(Gia_ManPo(p1,i)) );
Gia_ManAppendCo( pNew, iLit );
}
else
{
Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(Gia_ManPo(p1,i)) );
}
}
// create register inputs
Gia_ManForEachRi( p0, pObj, i )
{
Gia_ManMiter_rec( pNew, p0, Gia_ObjFanin0(pObj) );
pObj->Value = Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
}
Gia_ManForEachRi( p1, pObj, i )
{
Gia_ManMiter_rec( pNew, p1, Gia_ObjFanin0(pObj) );
pObj->Value = Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
}
Gia_ManSetRegNum( pNew, Gia_ManRegNum(p0) + Gia_ManRegNum(p1) );
}
Gia_ManHashStop( pNew );
pNew = Gia_ManCleanup( pTemp = pNew );
Gia_ManStop( pTemp );
return pNew;
}
/**Function*************************************************************
Synopsis [Transforms the circuit into a regular miter.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManTransformMiter( Gia_Man_t * p )
{
Gia_Man_t * pNew, * pTemp;
Gia_Obj_t * pObj, * pObj2;
int i, iLit;
assert( (Gia_ManPoNum(p) & 1) == 0 );
pNew = Gia_ManStart( Gia_ManObjNum(p) );
pNew->pName = Aig_UtilStrsav( p->pName );
Gia_ManConst0(p)->Value = 0;
Gia_ManHashAlloc( pNew );
Gia_ManForEachCi( p, pObj, i )
pObj->Value = Gia_ManAppendCi( pNew );
Gia_ManForEachAnd( p, pObj, i )
pObj->Value = Gia_ManHashAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
Gia_ManForEachPo( p, pObj, i )
{
pObj2 = Gia_ManPo( p, ++i );
iLit = Gia_ManHashXor( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin0Copy(pObj2) );
Gia_ManAppendCo( pNew, iLit );
}
Gia_ManForEachRi( p, pObj, i )
pObj->Value = Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
Gia_ManHashStop( pNew );
Gia_ManSetRegNum( pNew, Gia_ManRegNum(p) );
pNew = Gia_ManCleanup( pTemp = pNew );
Gia_ManStop( pTemp );
return pNew;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
......
src/aig/gia/giaEnable.c 0 → 100644
/**CFile****************************************************************
FileName [gia.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Scalable AIG package.]
Synopsis [Structural detection of enables, sets and resets.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: gia.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "gia.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_CollectSuper_rec( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Int_t * vSuper )
{
// if the new node is complemented or a PI, another gate begins
if ( Gia_IsComplement(pObj) || Gia_ObjIsCi(pObj) )
{
Vec_IntPushUnique( vSuper, Gia_ObjId(p, Gia_Regular(pObj)) );
return;
}
assert( Gia_ObjIsAnd(pObj) );
// go through the branches
Gia_CollectSuper_rec( p, Gia_ObjChild0(pObj), vSuper );
Gia_CollectSuper_rec( p, Gia_ObjChild1(pObj), vSuper );
}
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_CollectSuper( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Int_t * vSuper )
{
assert( !Gia_IsComplement(pObj) );
Vec_IntClear( vSuper );
// Gia_CollectSuper_rec( p, pObj, vSuper );
if ( Gia_ObjIsAnd(pObj) )
{
Vec_IntPushUnique( vSuper, Gia_ObjId(p, Gia_ObjFanin0(pObj)) );
Vec_IntPushUnique( vSuper, Gia_ObjId(p, Gia_ObjFanin1(pObj)) );
}
else
Vec_IntPushUnique( vSuper, Gia_ObjId(p, Gia_Regular(pObj)) );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManPrintSignals( Gia_Man_t * p, int * pFreq, char * pStr )
{
Vec_Int_t * vObjs;
int i, Counter = 0, nTotal = 0;
vObjs = Vec_IntAlloc( 100 );
for ( i = 0; i < Gia_ManObjNum(p); i++ )
if ( pFreq[i] > 1 )
{
nTotal += pFreq[i];
Counter++;
}
printf( "%s (total = %d driven = %d)\n", pStr, Counter, nTotal );
Counter = 0;
for ( i = 0; i < Gia_ManObjNum(p); i++ )
if ( pFreq[i] > 1 )
{
printf( "%3d : Obj = %6d Refs = %6d Freq = %6d\n",
++Counter, i, Gia_ObjRefs(p, Gia_ManObj(p,i)), pFreq[i] );
Vec_IntPush( vObjs, i );
}
Vec_IntFree( vObjs );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManDetectSeqSignals( Gia_Man_t * p, int fSetReset )
{
Vec_Int_t * vSuper;
Gia_Obj_t * pFlop, * pObjC, * pObj0, * pObj1, * pNode, * pTemp;
int i, k, Ent, * pSets, * pResets, * pEnables;
int nHaveSetReset = 0, nHaveEnable = 0;
assert( Gia_ManRegNum(p) > 0 );
pSets = ABC_CALLOC( int, Gia_ManObjNum(p) );
pResets = ABC_CALLOC( int, Gia_ManObjNum(p) );
pEnables = ABC_CALLOC( int, Gia_ManObjNum(p) );
vSuper = Vec_IntAlloc( 100 );
Gia_ManForEachRi( p, pFlop, i )
{
pNode = Gia_ObjFanin0(pFlop);
if ( !Gia_ObjIsAnd(pNode) )
continue;
// detect sets/resets
Gia_CollectSuper( p, pNode, vSuper );
if ( Gia_ObjFaninC0(pFlop) )
Vec_IntForEachEntry( vSuper, Ent, k )
pSets[Ent]++;
else
Vec_IntForEachEntry( vSuper, Ent, k )
pResets[Ent]++;
// detect enables
if ( !Gia_ObjIsMuxType(pNode) )
continue;
pObjC = Gia_ObjRecognizeMux( pNode, &pObj0, &pObj1 );
pTemp = Gia_ObjRiToRo( p, pFlop );
if ( Gia_Regular(pObj0) != pTemp && Gia_Regular(pObj1) != pTemp )
continue;
if ( !Gia_ObjFaninC0(pFlop) )
{
pObj0 = Gia_Not(pObj0);
pObj1 = Gia_Not(pObj1);
}
if ( Gia_IsComplement(pObjC) )
{
pObjC = Gia_Not(pObjC);
pTemp = pObj0;
pObj0 = pObj1;
pObj1 = pTemp;
}
// detect controls
// Gia_CollectSuper( p, pObjC, vSuper );
// Vec_IntForEachEntry( vSuper, Ent, k )
// pEnables[Ent]++;
pEnables[Gia_ObjId(p, pObjC)]++;
nHaveEnable++;
}
Gia_ManForEachRi( p, pFlop, i )
{
pNode = Gia_ObjFanin0(pFlop);
if ( !Gia_ObjIsAnd(pNode) )
continue;
// detect sets/resets
Gia_CollectSuper( p, pNode, vSuper );
Vec_IntForEachEntry( vSuper, Ent, k )
if ( pSets[Ent] > 1 || pResets[Ent] > 1 )
{
nHaveSetReset++;
break;
}
}
Vec_IntFree( vSuper );
Gia_ManCreateRefs( p );
printf( "Flops with set/reset = %6d. Flops with enable = %6d.\n", nHaveSetReset, nHaveEnable );
if ( fSetReset )
{
Gia_ManPrintSignals( p, pSets, "Set signals" );
Gia_ManPrintSignals( p, pResets, "Reset signals" );
}
Gia_ManPrintSignals( p, pEnables, "Enable signals" );
ABC_FREE( p->pRefs );
ABC_FREE( pSets );
ABC_FREE( pResets );
ABC_FREE( pEnables );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/aig/gia/giaMan.c
......@@ -68,8 +68,13 @@ void Gia_ManStop( Gia_Man_t * p )
{
Vec_IntFree( p->vCis );
Vec_IntFree( p->vCos );
ABC_FREE( p->pCexComb );
ABC_FREE( p->pIso );
ABC_FREE( p->pMapping );
ABC_FREE( p->pFanData );
ABC_FREE( p->pReprsOld );
ABC_FREE( p->pReprs );
ABC_FREE( p->pNexts );
ABC_FREE( p->pName );
ABC_FREE( p->pRefs );
ABC_FREE( p->pLevels );
......@@ -98,12 +103,16 @@ void Gia_ManPrintStats( Gia_Man_t * p )
printf( "ff =%7d ", Gia_ManRegNum(p) );
printf( "and =%8d ", Gia_ManAndNum(p) );
printf( "lev =%5d ", Gia_ManLevelNum(p) );
// printf( "cut =%5d ", Gia_ManCrossCut(p) );
printf( "cut =%5d ", Gia_ManCrossCut(p) );
printf( "mem =%5.2f Mb", 12.0*Gia_ManObjNum(p)/(1<<20) );
// printf( "obj =%5d ", Gia_ManObjNum(p) );
printf( "\n" );
// Gia_ManSatExperiment( p );
if ( p->pReprs && p->pNexts )
Gia_ManEquivPrintClasses( p, 0, 0.0 );
if ( p->pMapping )
Gia_ManPrintMappingStats( p );
}
/**Function*************************************************************
......
src/aig/gia/giaScl.c
......@@ -30,7 +30,7 @@
/**Function*************************************************************
Synopsis [Returns the number of unmarked nodes.]
Synopsis [Marks unreachable internal nodes and returned their number.]
Description []
......@@ -45,13 +45,13 @@ int Gia_ManCombMarkUsed_rec( Gia_Man_t * p, Gia_Obj_t * pObj )
return 0;
pObj->fMark0 = 0;
assert( Gia_ObjIsAnd(pObj) );
return Gia_ManCombMarkUsed_rec( p, Gia_ObjFanin0(pObj) ) +
Gia_ManCombMarkUsed_rec( p, Gia_ObjFanin1(pObj) ) + 1;
return 1 + Gia_ManCombMarkUsed_rec( p, Gia_ObjFanin0(pObj) )
+ Gia_ManCombMarkUsed_rec( p, Gia_ObjFanin1(pObj) );
}
/**Function*************************************************************
Synopsis [Returns the number of unused nodes.]
Synopsis [Marks unreachable internal nodes and returned their number.]
Description []
......@@ -90,7 +90,7 @@ Gia_Man_t * Gia_ManCleanup( Gia_Man_t * p )
/**Function*************************************************************
Synopsis [Marks CIs/COs reachable from POs.]
Synopsis [Marks CIs/COs/ANDs unreachable from POs.]
Description []
......@@ -99,29 +99,26 @@ Gia_Man_t * Gia_ManCleanup( Gia_Man_t * p )
SeeAlso []
***********************************************************************/
void Gia_ManSeqMarkUsed_rec( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Int_t * vRoots )
int Gia_ManSeqMarkUsed_rec( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Int_t * vRoots )
{
if ( !pObj->fMark0 )
return;
return 0;
pObj->fMark0 = 0;
if ( Gia_ObjIsCo(pObj) )
{
Gia_ManSeqMarkUsed_rec( p, Gia_ObjFanin0(pObj), vRoots );
return;
}
return Gia_ManSeqMarkUsed_rec( p, Gia_ObjFanin0(pObj), vRoots );
if ( Gia_ObjIsRo(p, pObj) )
{
Vec_IntPush( vRoots, Gia_ObjId(p, Gia_ObjRoToRi(p, pObj)) );
return;
return 0;
}
assert( Gia_ObjIsAnd(pObj) );
Gia_ManSeqMarkUsed_rec( p, Gia_ObjFanin0(pObj), vRoots );
Gia_ManSeqMarkUsed_rec( p, Gia_ObjFanin1(pObj), vRoots );
return 1 + Gia_ManSeqMarkUsed_rec( p, Gia_ObjFanin0(pObj), vRoots )
+ Gia_ManSeqMarkUsed_rec( p, Gia_ObjFanin1(pObj), vRoots );
}
/**Function*************************************************************
Synopsis [Performs sequential cleanup.]
Synopsis [Marks CIs/COs/ANDs unreachable from POs.]
Description []
......@@ -130,19 +127,38 @@ void Gia_ManSeqMarkUsed_rec( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Int_t * vRoots
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManSeqCleanup( Gia_Man_t * p )
int Gia_ManSeqMarkUsed( Gia_Man_t * p )
{
Vec_Int_t * vRoots;
Gia_Obj_t * pObj;
int i;
int i, nNodes = 0;
Gia_ManSetMark0( p );
Gia_ManConst0(p)->fMark0 = 0;
Gia_ManForEachPi( p, pObj, i )
pObj->fMark0 = 0;
Gia_ManForEachPo( p, pObj, i )
pObj->fMark0 = 0;
vRoots = Gia_ManCollectPoIds( p );
Gia_ManForEachObjVec( vRoots, p, pObj, i )
Gia_ManSeqMarkUsed_rec( p, pObj, vRoots );
nNodes += Gia_ManSeqMarkUsed_rec( p, pObj, vRoots );
Vec_IntFree( vRoots );
return nNodes;
}
/**Function*************************************************************
Synopsis [Performs sequential cleanup.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManSeqCleanup( Gia_Man_t * p )
{
Gia_ManSeqMarkUsed( p );
return Gia_ManDupMarked( p );
}
......
src/aig/gia/giaSort.c
......@@ -245,12 +245,15 @@ void minisat_sort3(float* array, int* perm, int size)
SeeAlso []
***********************************************************************/
int * Gia_SortFloats( float * pArray, int nSize )
int * Gia_SortFloats( float * pArray, int * pPerm, int nSize )
{
int i, * pPerm;
pPerm = ABC_ALLOC( int, nSize );
for ( i = 0; i < nSize; i++ )
pPerm[i] = i;
int i;
if ( pPerm == NULL )
{
pPerm = ABC_ALLOC( int, nSize );
for ( i = 0; i < nSize; i++ )
pPerm[i] = i;
}
minisat_sort3( pArray, pPerm, nSize );
// for ( i = 1; i < nSize; i++ )
// assert( pArray[i-1] <= pArray[i] );
......
src/aig/gia/giaUtil.c
......@@ -300,6 +300,34 @@ void Gia_ManCreateRefs( Gia_Man_t * p )
/**Function*************************************************************
Synopsis [Assigns references.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int * Gia_ManCreateMuxRefs( Gia_Man_t * p )
{
Gia_Obj_t * pObj, * pCtrl, * pFan0, * pFan1;
int i, * pMuxRefs;
pMuxRefs = ABC_CALLOC( int, Gia_ManObjNum(p) );
Gia_ManForEachObj( p, pObj, i )
{
if ( Gia_ObjRecognizeExor( pObj, &pFan0, &pFan1 ) )
continue;
if ( !Gia_ObjIsMuxType(pObj) )
continue;
pCtrl = Gia_ObjRecognizeMux( pObj, &pFan0, &pFan1 );
pMuxRefs[ Gia_ObjId(p, Gia_Regular(pCtrl)) ]++;
}
return pMuxRefs;
}
/**Function*************************************************************
Synopsis [Computes the maximum frontier size.]
Description []
......@@ -549,6 +577,45 @@ Gia_Obj_t * Gia_ObjRecognizeMux( Gia_Obj_t * pNode, Gia_Obj_t ** ppNodeT, Gia_Ob
return NULL;
}
/**Function*************************************************************
Synopsis [Resimulates the counter-example.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManVerifyCounterExample( Gia_Man_t * pAig, Gia_Cex_t * p, int fDoubleOuts )
{
Gia_Obj_t * pObj, * pObjRi, * pObjRo;
int RetValue, i, k, iBit = 0;
Gia_ManForEachRo( pAig, pObj, i )
pObj->fMark0 = Aig_InfoHasBit(p->pData, iBit++);
for ( i = 0; i <= p->iFrame; i++ )
{
Gia_ManForEachPi( pAig, pObj, k )
pObj->fMark0 = Aig_InfoHasBit(p->pData, iBit++);
Gia_ManForEachAnd( pAig, pObj, k )
pObj->fMark0 = (Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj)) &
(Gia_ObjFanin1(pObj)->fMark0 ^ Gia_ObjFaninC1(pObj));
Gia_ManForEachCo( pAig, pObj, k )
pObj->fMark0 = Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj);
Gia_ManForEachRiRo( pAig, pObjRi, pObjRo, k )
pObjRo->fMark0 = pObjRi->fMark0;
}
assert( iBit == p->nBits );
if ( fDoubleOuts )
RetValue = Gia_ManPo(pAig, 2*p->iPo)->fMark0 ^ Gia_ManPo(pAig, 2*p->iPo+1)->fMark0;
else
RetValue = Gia_ManPo(pAig, p->iPo)->fMark0;
Gia_ManCleanMark0(pAig);
return RetValue;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
......
src/aig/gia/module.make
......@@ -5,6 +5,8 @@ SRC += src/aig/gia/gia.c \
src/aig/gia/giaDfs.c \
src/aig/gia/giaDup.c \
src/aig/gia/giaEmbed.c \
src/aig/gia/giaEnable.c \
src/aig/gia/giaEquiv.c \
src/aig/gia/giaFanout.c \
src/aig/gia/giaForce.c \
src/aig/gia/giaFrames.c \
......@@ -12,6 +14,7 @@ SRC += src/aig/gia/gia.c \
src/aig/gia/giaGlitch.c \
src/aig/gia/giaHash.c \
src/aig/gia/giaMan.c \
src/aig/gia/giaMap.c \
src/aig/gia/giaScl.c \
src/aig/gia/giaSim.c \
src/aig/gia/giaSort.c \
......
src/aig/ioa/ioaReadAig.c
......@@ -341,6 +341,18 @@ Aig_Man_t * Ioa_ReadAiger( char * pFileName, int fCheck )
Aig_ManShortNames( pNew );
}
*/
pCur = pSymbols;
if ( pCur + 1 < pContents + nFileSize && *pCur == 'c' )
{
pCur++;
if ( *pCur == 'n' )
{
pCur++;
// read model name
ABC_FREE( pNew->pName );
pNew->pName = Aig_UtilStrsav( pCur );
}
}
// skipping the comments
ABC_FREE( pContents );
......
src/aig/ioa/ioaWriteAig.c
......@@ -375,10 +375,10 @@ void Ioa_WriteAiger( Aig_Man_t * pMan, char * pFileName, int fWriteSymbols, int
}
*/
// write the comment
fprintf( pFile, "c\n" );
fprintf( pFile, "c" );
if ( pMan->pName )
fprintf( pFile, ".model %s\n", pMan->pName );
fprintf( pFile, "This file was produced by the AIG package on %s\n", Ioa_TimeStamp() );
fprintf( pFile, "n%s%c", pMan->pName, '\0' );
fprintf( pFile, "\nThis file was produced by the IOA package in ABC on %s\n", Ioa_TimeStamp() );
fprintf( pFile, "For information about AIGER format, refer to %s\n", "http://fmv.jku.at/aiger" );
fclose( pFile );
}
......
src/aig/saig/saigMiter.c
......@@ -568,13 +568,17 @@ int Saig_ManDemiterSimpleDiff( Aig_Man_t * p, Aig_Man_t ** ppAig0, Aig_Man_t **
printf( "The output number %d of the miter is constant 1.\n", i );
Counter++;
continue;
}
}
if ( !Aig_ObjIsNode(pFanin) || !Aig_ObjRecognizeExor( pFanin, &pObj0, &pObj1 ) )
{
/*
printf( "The miter cannot be demitered.\n" );
Vec_PtrFree( vSet0 );
Vec_PtrFree( vSet1 );
return 0;
*/
printf( "The output number %d cannot be demitered.\n", i );
continue;
}
if ( Aig_ObjFaninC0(pObj) )
pObj0 = Aig_Not(pObj0);
......
src/aig/ssw/sswCore.c
......@@ -179,7 +179,8 @@ clk = clock();
printf( "Cex =%5d. ", p->nSatCallsSat-nSatCallsSat );
printf( "R =%4d. ", p->nRecycles-nRecycles );
}
printf( "F =%5d. ", p->nSatFailsReal-nSatFailsReal );
printf( "F =%5d. %s ", p->nSatFailsReal-nSatFailsReal,
(Saig_ManPoNum(p->pAig)==1 && Ssw_ObjIsConst1Cand(p->pAig,Aig_ObjFanin0(Aig_ManPo(p->pAig,0))))? "+" : "-" );
ABC_PRT( "T", clock() - clk );
}
// if ( p->pPars->fDynamic && p->nSatCallsSat-nSatCallsSat < 100 )
......
src/base/abc/abcFanio.c
......@@ -92,6 +92,12 @@ void Abc_ObjAddFanin( Abc_Obj_t * pObj, Abc_Obj_t * pFanin )
{
printf( "Abc_ObjAddFanin(): Error! Creating net \"%s\" with two fanins.\n", Abc_ObjName(pObj) );
}
/*
if ( Abc_ObjIsCo(pFanin) )
{
printf( "Abc_ObjAddFanin(): Error! Creating fanout of a CO.\n", Abc_ObjName(pFanin) );
}
*/
}
......
src/base/abci/abcDar.c
......@@ -702,35 +702,6 @@ Abc_Ntk_t * Abc_NtkDarFraig( Abc_Ntk_t * pNtk, int nConfLimit, int fDoSparse, in
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkDarSatSweep( Abc_Ntk_t * pNtk, Cec_ParCsw_t * pPars )
{
/*
extern Aig_Man_t * Cec_ManSatSweep( Aig_Man_t * pAig, Cec_ParCsw_t * pPars );
Abc_Ntk_t * pNtkAig;
Aig_Man_t * pMan, * pTemp;
pMan = Abc_NtkToDar( pNtk, 0, 0 );
if ( pMan == NULL )
return NULL;
pMan = Cec_ManSatSweep( pTemp = pMan, pPars );
Aig_ManStop( pTemp );
pNtkAig = Abc_NtkFromDar( pNtk, pMan );
Aig_ManStop( pMan );
return pNtkAig;
*/
return NULL;
}
/**Function*************************************************************
Synopsis [Gives the current ABC network to AIG manager for processing.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkDarFraigPart( Abc_Ntk_t * pNtk, int nPartSize, int nConfLimit, int nLevelMax, int fVerbose )
{
Abc_Ntk_t * pNtkAig;
......@@ -1184,7 +1155,17 @@ int Abc_NtkDarCec( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nConfLimit, int fPa
Aig_Man_t * pMan, * pMan1, * pMan2;
Abc_Ntk_t * pMiter;
int RetValue, clkTotal = clock();
/*
{
extern void Cec_ManVerifyTwoAigs( Aig_Man_t * pAig0, Aig_Man_t * pAig1, int fVerbose );
Aig_Man_t * pAig0 = Abc_NtkToDar( pNtk1, 0, 0 );
Aig_Man_t * pAig1 = Abc_NtkToDar( pNtk2, 0, 0 );
Cec_ManVerifyTwoAigs( pAig0, pAig1, 1 );
Aig_ManStop( pAig0 );
Aig_ManStop( pAig1 );
return 1;
}
*/
// cannot partition if it is already a miter
if ( pNtk2 == NULL && fPartition == 1 )
{
......@@ -1285,82 +1266,6 @@ ABC_PRT( "Time", clock() - clkTotal );
SeeAlso []
***********************************************************************/
int Abc_NtkDarCec2( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, Cec_ParCec_t * pPars )
{
Aig_Man_t * pMan1, * pMan2 = NULL;
int RetValue, clkTotal = clock();
if ( pNtk2 )
{
if ( Abc_NtkPiNum(pNtk1) != Abc_NtkPiNum(pNtk2) )
{
printf( "Networks have different number of PIs.\n" );
return -1;
}
if ( Abc_NtkPoNum(pNtk1) != Abc_NtkPoNum(pNtk2) )
{
printf( "Networks have different number of POs.\n" );
return -1;
}
}
if ( pNtk1 )
{
pMan1 = Abc_NtkToDar( pNtk1, 0, 0 );
if ( pMan1 == NULL )
{
printf( "Converting into AIG has failed.\n" );
return -1;
}
}
if ( pNtk2 )
{
pMan2 = Abc_NtkToDar( pNtk2, 0, 0 );
if ( pMan2 == NULL )
{
Aig_ManStop( pMan1 );
printf( "Converting into AIG has failed.\n" );
return -1;
}
}
// perform verification
// RetValue = Cec_Solve( pMan1, pMan2, pPars );
RetValue = -1;
// transfer model if given
pNtk1->pModel = pMan1->pData, pMan1->pData = NULL;
Aig_ManStop( pMan1 );
if ( pMan2 )
Aig_ManStop( pMan2 );
// report the miter
if ( RetValue == 1 )
{
printf( "Networks are equivalent. " );
ABC_PRT( "Time", clock() - clkTotal );
}
else if ( RetValue == 0 )
{
printf( "Networks are NOT EQUIVALENT. " );
ABC_PRT( "Time", clock() - clkTotal );
}
else
{
printf( "Networks are UNDECIDED. " );
ABC_PRT( "Time", clock() - clkTotal );
}
fflush( stdout );
return RetValue;
}
/**Function*************************************************************
Synopsis [Gives the current ABC network to AIG manager for processing.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkDarSeqSweep( Abc_Ntk_t * pNtk, Fra_Ssw_t * pPars )
{
Fraig_Params_t Params;
......@@ -1797,8 +1702,8 @@ int Abc_NtkDarDemiter( Abc_Ntk_t * pNtk )
Aig_ManStop( pPart1 );
Aig_ManStop( pMan );
return 1;
}
}
/**Function*************************************************************
Synopsis [Gives the current ABC network to AIG manager for processing.]
......@@ -1826,6 +1731,7 @@ int Abc_NtkDarProve( Abc_Ntk_t * pNtk, Fra_Sec_t * pSecPar )
Abc_NtkMakeComb( pNtkComb, 1 );
// solve it using combinational equivalence checking
Prove_ParamsSetDefault( pParams );
pParams->fVerbose = 1;
RetValue = Abc_NtkIvyProve( &pNtkComb, pParams );
// transfer model if given
// pNtk->pModel = pNtkComb->pModel; pNtkComb->pModel = NULL;
......
src/base/abci/abcDsd.c
......@@ -161,7 +161,8 @@ void Abc_NtkDsdConstruct( Dsd_Manager_t * pManDsd, Abc_Ntk_t * pNtk, Abc_Ntk_t *
int i, nNodesDsd;
// save the CI nodes in the DSD nodes
Dsd_NodeSetMark( Dsd_ManagerReadConst1(pManDsd), (int)(ABC_PTRINT_T)Abc_NtkCreateNodeConst1(pNtkNew) );
Abc_AigConst1(pNtk)->pCopy = pNodeNew = Abc_NtkCreateNodeConst1(pNtkNew);
Dsd_NodeSetMark( Dsd_ManagerReadConst1(pManDsd), (int)(ABC_PTRINT_T)pNodeNew );
Abc_NtkForEachCi( pNtk, pNode, i )
{
pNodeDsd = Dsd_ManagerReadInput( pManDsd, i );
......
src/base/abci/abcLutmin.c 0 → 100644
/**CFile****************************************************************
FileName [abcLutmin.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Minimization of the number of LUTs.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: abcLutmin.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts the node to MUXes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NtkCreateNodeLut( Abc_Ntk_t * pNtkNew, DdManager * dd, DdNode * bFunc, Abc_Obj_t * pNode, int nLutSize )
{
DdNode * bFuncNew;
Abc_Obj_t * pNodeNew;
int i, nStart = ABC_MIN( 0, Abc_ObjFaninNum(pNode) - nLutSize );
// create a new node
pNodeNew = Abc_NtkCreateNode( pNtkNew );
// add the fanins in the order, in which they appear in the reordered manager
for ( i = nStart; i < Abc_ObjFaninNum(pNode); i++ )
Abc_ObjAddFanin( pNodeNew, Abc_ObjFanin(pNode, i)->pCopy );
// transfer the function
bFuncNew = Extra_bddMove( dd, bFunc, nStart ); Cudd_Ref( bFuncNew );
assert( Cudd_SupportSize(dd, bFuncNew) <= nLutSize );
pNodeNew->pData = Extra_TransferLevelByLevel( dd, pNtkNew->pManFunc, bFuncNew ); Cudd_Ref( pNodeNew->pData );
Cudd_RecursiveDeref( dd, bFuncNew );
return pNodeNew;
}
/**Function*************************************************************
Synopsis [Converts the node to MUXes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NodeBddToMuxesLut_rec( DdManager * dd, DdNode * bFunc, Abc_Ntk_t * pNtkNew, st_table * tBdd2Node, Abc_Obj_t * pNode, int nLutSize )
{
Abc_Obj_t * pNodeNew, * pNodeNew0, * pNodeNew1, * pNodeNewC;
assert( !Cudd_IsComplement(bFunc) );
if ( bFunc == b1 )
return Abc_NtkCreateNodeConst1(pNtkNew);
if ( st_lookup( tBdd2Node, (char *)bFunc, (char **)&pNodeNew ) )
return pNodeNew;
if ( dd->perm[bFunc->index] >= Abc_ObjFaninNum(pNode) - nLutSize )
{
pNodeNew = Abc_NtkCreateNodeLut( pNtkNew, dd, bFunc, pNode, nLutSize );
st_insert( tBdd2Node, (char *)bFunc, (char *)pNodeNew );
return pNodeNew;
}
// solve for the children nodes
pNodeNew0 = Abc_NodeBddToMuxesLut_rec( dd, Cudd_Regular(cuddE(bFunc)), pNtkNew, tBdd2Node, pNode, nLutSize );
if ( Cudd_IsComplement(cuddE(bFunc)) )
pNodeNew0 = Abc_NtkCreateNodeInv( pNtkNew, pNodeNew0 );
pNodeNew1 = Abc_NodeBddToMuxesLut_rec( dd, cuddT(bFunc), pNtkNew, tBdd2Node, pNode, nLutSize );
if ( !st_lookup( tBdd2Node, (char *)Cudd_bddIthVar(dd, bFunc->index), (char **)&pNodeNewC ) )
assert( 0 );
// create the MUX node
pNodeNew = Abc_NtkCreateNodeMux( pNtkNew, pNodeNewC, pNodeNew1, pNodeNew0 );
st_insert( tBdd2Node, (char *)bFunc, (char *)pNodeNew );
return pNodeNew;
}
/**Function*************************************************************
Synopsis [Converts the node to MUXes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NodeBddToMuxesLut( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, int nLutSize )
{
DdManager * dd = pNodeOld->pNtk->pManFunc;
DdNode * bFunc = pNodeOld->pData;
Abc_Obj_t * pFaninOld, * pNodeNew;
st_table * tBdd2Node;
int i;
// create the table mapping BDD nodes into the ABC nodes
tBdd2Node = st_init_table( st_ptrcmp, st_ptrhash );
// add the constant and the elementary vars
Abc_ObjForEachFanin( pNodeOld, pFaninOld, i )
st_insert( tBdd2Node, (char *)Cudd_bddIthVar(dd, i), (char *)pFaninOld->pCopy );
// create the new nodes recursively
pNodeNew = Abc_NodeBddToMuxesLut_rec( dd, Cudd_Regular(bFunc), pNtkNew, tBdd2Node, pNodeOld, nLutSize );
st_free_table( tBdd2Node );
if ( Cudd_IsComplement(bFunc) )
pNodeNew = Abc_NtkCreateNodeInv( pNtkNew, pNodeNew );
return pNodeNew;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkLutminConstruct( Abc_Ntk_t * pNtkClp, Abc_Ntk_t * pNtkDec, int nLutSize )
{
Abc_Obj_t * pObj, * pDriver;
int i;
Abc_NtkForEachCo( pNtkClp, pObj, i )
{
pDriver = Abc_ObjFanin0( pObj );
if ( !Abc_ObjIsNode(pDriver) )
continue;
if ( Abc_ObjFaninNum(pDriver) == 0 )
pDriver->pCopy = Abc_NtkDupObj( pNtkDec, pDriver, 0 );
else
pDriver->pCopy = Abc_NodeBddToMuxesLut( pNtkDec, pDriver, nLutSize );
}
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkLutmin( Abc_Ntk_t * pNtk, int nLutSize, int fVerbose )
{
extern void Abc_NtkBddReorder( Abc_Ntk_t * pNtk, int fVerbose );
Abc_Ntk_t * pNtkDec, * pNtkClp, * pTemp;
// collapse the network and reorder BDDs
if ( Abc_NtkIsStrash(pNtk) )
pTemp = Abc_NtkDup( pNtk );
else
pTemp = Abc_NtkStrash( pNtk, 0, 1, 0 );
pNtkClp = Abc_NtkCollapse( pTemp, 10000, 0, 1, 0 );
Abc_NtkDelete( pTemp );
if ( pNtkClp == NULL )
return NULL;
if ( !Abc_NtkIsBddLogic(pNtkClp) )
Abc_NtkToBdd( pNtkClp );
Abc_NtkBddReorder( pNtkClp, fVerbose );
// decompose one output at a time
pNtkDec = Abc_NtkStartFrom( pNtkClp, ABC_NTK_LOGIC, ABC_FUNC_BDD );
// make sure the new manager has enough inputs
Cudd_bddIthVar( pNtkDec->pManFunc, nLutSize );
// put the results into the new network (save new CO drivers in old CO drivers)
Abc_NtkLutminConstruct( pNtkClp, pNtkDec, nLutSize );
// finalize the new network
Abc_NtkFinalize( pNtkClp, pNtkDec );
Abc_NtkDelete( pNtkClp );
// make the network minimum base
Abc_NtkMinimumBase( pNtkDec );
// fix the problem with complemented and duplicated CO edges
Abc_NtkLogicMakeSimpleCos( pNtkDec, 0 );
// make sure everything is okay
if ( !Abc_NtkCheck( pNtkDec ) )
{
printf( "Abc_NtkLutmin: The network check has failed.\n" );
return 0;
}
return pNtkDec;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/base/abci/module.make
......@@ -24,6 +24,7 @@ SRC += src/base/abci/abc.c \
src/base/abci/abcIf.c \
src/base/abci/abcIvy.c \
src/base/abci/abcLut.c \
src/base/abci/abcLutmin.c \
src/base/abci/abcMap.c \
src/base/abci/abcMerge.c \
src/base/abci/abcMini.c \
......
src/base/cmd/cmd.c
......@@ -1737,6 +1737,73 @@ usage:
}
/**Function*************************************************************
Synopsis [Computes dimentions of the graph.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManGnuplotShow( char * pPlotFileName )
{
FILE * pFile;
void * pAbc;
char * pProgNameGnuplotWin = "wgnuplot.exe";
char * pProgNameGnuplotUnix = "gnuplot";
char * pProgNameGnuplot;
// read in the Capo plotting output
if ( (pFile = fopen( pPlotFileName, "r" )) == NULL )
{
fprintf( stdout, "Cannot open the plot file \"%s\".\n\n", pPlotFileName );
return;
}
fclose( pFile );
pAbc = Abc_FrameGetGlobalFrame();
// get the names from the plotting software
if ( Cmd_FlagReadByName(pAbc, "gnuplotwin") )
pProgNameGnuplotWin = Cmd_FlagReadByName(pAbc, "gnuplotwin");
if ( Cmd_FlagReadByName(pAbc, "gnuplotunix") )
pProgNameGnuplotUnix = Cmd_FlagReadByName(pAbc, "gnuplotunix");
// check if Gnuplot is available
if ( (pFile = fopen( pProgNameGnuplotWin, "r" )) )
pProgNameGnuplot = pProgNameGnuplotWin;
else if ( (pFile = fopen( pProgNameGnuplotUnix, "r" )) )
pProgNameGnuplot = pProgNameGnuplotUnix;
else if ( pFile == NULL )
{
fprintf( stdout, "Cannot find \"%s\" or \"%s\" in the current directory.\n", pProgNameGnuplotWin, pProgNameGnuplotUnix );
return;
}
fclose( pFile );
// spawn the viewer
#ifdef WIN32
if ( _spawnl( _P_NOWAIT, pProgNameGnuplot, pProgNameGnuplot, pPlotFileName, NULL ) == -1 )
{
fprintf( stdout, "Cannot find \"%s\".\n", pProgNameGnuplot );
return;
}
#else
{
char Command[1000];
sprintf( Command, "%s %s ", pProgNameGnuplot, pPlotFileName );
if ( system( Command ) == -1 )
{
fprintf( stdout, "Cannot execute \"%s\".\n", Command );
return;
}
}
#endif
}
/**Function********************************************************************
Synopsis [Calls Capo internally.]
......
src/base/io/io.c
......@@ -28,6 +28,7 @@
static int IoCommandRead ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandReadAiger ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandReadBaf ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandReadBblif ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandReadBlif ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandReadBlifMv ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandReadBench ( Abc_Frame_t * pAbc, int argc, char **argv );
......@@ -45,6 +46,7 @@ static int IoCommandWrite ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteHie ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteAiger ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBaf ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBblif ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBlif ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBlifMv ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBench ( Abc_Frame_t * pAbc, int argc, char **argv );
......@@ -83,6 +85,7 @@ void Io_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "I/O", "read", IoCommandRead, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_aiger", IoCommandReadAiger, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_baf", IoCommandReadBaf, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_bblif", IoCommandReadBblif, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_blif", IoCommandReadBlif, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_blif_mv", IoCommandReadBlifMv, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_bench", IoCommandReadBench, 1 );
......@@ -100,6 +103,7 @@ void Io_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "I/O", "write_hie", IoCommandWriteHie, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_aiger", IoCommandWriteAiger, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_baf", IoCommandWriteBaf, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_bblif", IoCommandWriteBblif, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_blif", IoCommandWriteBlif, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_blif_mv", IoCommandWriteBlifMv, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_bench", IoCommandWriteBench, 0 );
......@@ -316,6 +320,60 @@ usage:
SeeAlso []
***********************************************************************/
int IoCommandReadBblif( Abc_Frame_t * pAbc, int argc, char ** argv )
{
Abc_Ntk_t * pNtk;
char * pFileName;
int fCheck;
int c;
fCheck = 1;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "ch" ) ) != EOF )
{
switch ( c )
{
case 'c':
fCheck ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
}
if ( argc != globalUtilOptind + 1 )
goto usage;
// get the input file name
pFileName = argv[globalUtilOptind];
// read the file using the corresponding file reader
pNtk = Io_Read( pFileName, IO_FILE_BBLIF, fCheck );
if ( pNtk == NULL )
return 1;
// replace the current network
Abc_FrameReplaceCurrentNetwork( pAbc, pNtk );
return 0;
usage:
fprintf( pAbc->Err, "usage: read_bblif [-ch] <file>\n" );
fprintf( pAbc->Err, "\t read the network in a binary BLIF format\n" );
fprintf( pAbc->Err, "\t-c : toggle network check after reading [default = %s]\n", fCheck? "yes":"no" );
fprintf( pAbc->Err, "\t-h : prints the command summary\n" );
fprintf( pAbc->Err, "\tfile : the name of a file to read\n" );
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int IoCommandReadBlif( Abc_Frame_t * pAbc, int argc, char ** argv )
{
Abc_Ntk_t * pNtk;
......@@ -1329,6 +1387,54 @@ usage:
SeeAlso []
***********************************************************************/
int IoCommandWriteBblif( Abc_Frame_t * pAbc, int argc, char **argv )
{
char * pFileName;
int c;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "h" ) ) != EOF )
{
switch ( c )
{
case 'h':
goto usage;
default:
goto usage;
}
}
if ( pAbc->pNtkCur == NULL )
{
fprintf( pAbc->Out, "Empty network.\n" );
return 0;
}
if ( argc != globalUtilOptind + 1 )
goto usage;
// get the output file name
pFileName = argv[globalUtilOptind];
// call the corresponding file writer
Io_Write( pAbc->pNtkCur, pFileName, IO_FILE_BBLIF );
return 0;
usage:
fprintf( pAbc->Err, "usage: write_bblif [-h] <file>\n" );
fprintf( pAbc->Err, "\t write the network into a binary BLIF file\n" );
fprintf( pAbc->Err, "\t-h : print the help massage\n" );
fprintf( pAbc->Err, "\tfile : the name of the file to write (extension .bblif)\n" );
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int IoCommandWriteBlif( Abc_Frame_t * pAbc, int argc, char **argv )
{
char * pFileName;
......
src/base/io/ioAbc.h
......@@ -44,6 +44,7 @@ typedef enum {
IO_FILE_NONE = 0,
IO_FILE_AIGER,
IO_FILE_BAF,
IO_FILE_BBLIF,
IO_FILE_BLIF,
IO_FILE_BLIFMV,
IO_FILE_BENCH,
......@@ -73,6 +74,8 @@ typedef enum {
extern Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck );
/*=== abcReadBaf.c ============================================================*/
extern Abc_Ntk_t * Io_ReadBaf( char * pFileName, int fCheck );
/*=== abcReadBblif.c ============================================================*/
extern Abc_Ntk_t * Io_ReadBblif( char * pFileName, int fCheck );
/*=== abcReadBlif.c ===========================================================*/
extern Abc_Ntk_t * Io_ReadBlif( char * pFileName, int fCheck );
/*=== abcReadBlifMv.c =========================================================*/
......@@ -91,6 +94,8 @@ extern Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck );
extern void Io_WriteAiger( Abc_Ntk_t * pNtk, char * pFileName, int fWriteSymbols, int fCompact );
/*=== abcWriteBaf.c ===========================================================*/
extern void Io_WriteBaf( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteBblif.c ===========================================================*/
extern void Io_WriteBblif( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteBlif.c ==========================================================*/
extern void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * pFileName, int fWriteLatches );
extern void Io_WriteBlif( Abc_Ntk_t * pNtk, char * pFileName, int fWriteLatches );
......
src/base/io/ioReadAiger.c
......@@ -463,19 +463,19 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
}
// read the name of the model if given
if ( *pCur == 'c' && pCur < pContents + nFileSize )
pCur = pSymbols;
if ( pCur + 1 < pContents + nFileSize && *pCur == 'c' )
{
if ( !strncmp( pCur + 2, ".model", 6 ) )
pCur++;
if ( *pCur == 'n' )
{
char * pTemp;
for ( pTemp = pCur + 9; *pTemp && *pTemp != '\n'; pTemp++ );
*pTemp = 0;
pCur++;
// read model name
ABC_FREE( pNtkNew->pName );
pNtkNew->pName = Extra_UtilStrsav( pCur + 9 );
pNtkNew->pName = Extra_UtilStrsav( pCur );
}
}
// skipping the comments
ABC_FREE( pContents );
Vec_PtrFree( vNodes );
......
src/base/io/ioUtil.c
......@@ -51,6 +51,8 @@ Io_FileType_t Io_ReadFileType( char * pFileName )
return IO_FILE_AIGER;
if ( !strcmp( pExt, "baf" ) )
return IO_FILE_BAF;
if ( !strcmp( pExt, "bblif" ) )
return IO_FILE_BBLIF;
if ( !strcmp( pExt, "blif" ) )
return IO_FILE_BLIF;
if ( !strcmp( pExt, "bench" ) )
......@@ -108,12 +110,14 @@ Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck
}
fclose( pFile );
// read the AIG
if ( FileType == IO_FILE_AIGER || FileType == IO_FILE_BAF )
if ( FileType == IO_FILE_AIGER || FileType == IO_FILE_BAF || FileType == IO_FILE_BBLIF )
{
if ( FileType == IO_FILE_AIGER )
pNtk = Io_ReadAiger( pFileName, fCheck );
else // if ( FileType == IO_FILE_BAF )
else if ( FileType == IO_FILE_BAF )
pNtk = Io_ReadBaf( pFileName, fCheck );
else // if ( FileType == IO_FILE_BBLIF )
pNtk = Io_ReadBblif( pFileName, fCheck );
if ( pNtk == NULL )
{
fprintf( stdout, "Reading AIG from file has failed.\n" );
......@@ -258,7 +262,7 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType )
}
if ( FileType == IO_FILE_AIGER )
Io_WriteAiger( pNtk, pFileName, 1, 0 );
else // if ( FileType == IO_FILE_BAF )
else //if ( FileType == IO_FILE_BAF )
Io_WriteBaf( pNtk, pFileName );
return;
}
......@@ -278,6 +282,18 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType )
Io_WriteGml( pNtk, pFileName );
return;
}
if ( FileType == IO_FILE_BBLIF )
{
if ( !Abc_NtkIsLogic(pNtk) )
{
fprintf( stdout, "Writing Binary BLIF is only possible for logic networks.\n" );
return;
}
if ( !Abc_NtkHasSop(pNtk) )
Abc_NtkToSop( pNtk, 0 );
Io_WriteBblif( pNtk, pFileName );
return;
}
/*
if ( FileType == IO_FILE_BLIFMV )
{
......
src/base/io/ioWriteAiger.c
......@@ -726,10 +726,10 @@ void Io_WriteAiger( Abc_Ntk_t * pNtk, char * pFileName, int fWriteSymbols, int f
}
// write the comment
fprintfBz2Aig( &b, "c\n" );
fprintfBz2Aig( &b, "c" );
if ( pNtk->pName && strlen(pNtk->pName) > 0 )
fprintfBz2Aig( &b, ".model %s\n", pNtk->pName );
fprintfBz2Aig( &b, "This file was produced by ABC on %s\n", Extra_TimeStamp() );
fprintfBz2Aig( &b, "n%s%c", pNtk->pName, '\0' );
fprintfBz2Aig( &b, "\nThis file was written by ABC on %s\n", Extra_TimeStamp() );
fprintfBz2Aig( &b, "For information about AIGER format, refer to %s\n", "http://fmv.jku.at/aiger" );
// close the file
......
src/base/io/ioWriteBblif.c 0 → 100644
/**CFile****************************************************************
FileName [ioWriteBblif.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Command processing package.]
Synopsis [Procedures to write AIG in the binary format.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: ioWriteBblif.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "ioAbc.h"
#include "bblif.h"
// For description of Binary BLIF format, refer to "abc/src/aig/bbl/bblif.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Fnction*************************************************************
Synopsis [Construct manager from the ABC network.]
Description [In the ABC network each object has a unique integer ID.
This ID is used when we construct objects of the BBLIF manager
corresponding to each object of the ABC network. The objects can be
added to the manager in any order (although below they are added in the
topological order), but by the time fanin/fanout connections are created,
corresponding objects are already constructed. In the end the checking
procedure is called.]
SideEffects []
SeeAlso []
***********************************************************************/
Bbl_Man_t * Bbl_ManFromAbc( Abc_Ntk_t * pNtk )
{
Bbl_Man_t * p;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanin;
int i, k;
assert( Abc_NtkIsSopLogic(pNtk) );
// start the data manager
p = Bbl_ManStart( Abc_NtkName(pNtk) );
// collect internal nodes to be added
vNodes = Abc_NtkDfs( pNtk, 0 );
// create combinational inputs
Abc_NtkForEachCi( pNtk, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_CI, Abc_ObjId(pObj), 0, NULL );
// create internal nodes
Vec_PtrForEachEntry( vNodes, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_NODE, Abc_ObjId(pObj), Abc_ObjFaninNum(pObj), pObj->pData );
// create combinational outputs
Abc_NtkForEachCo( pNtk, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_CO, Abc_ObjId(pObj), 1, NULL );
// create fanin/fanout connections for internal nodes
Vec_PtrForEachEntry( vNodes, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
Bbl_ManAddFanin( p, Abc_ObjId(pObj), Abc_ObjId(pFanin) );
// create fanin/fanout connections for combinational outputs
Abc_NtkForEachCo( pNtk, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
Bbl_ManAddFanin( p, Abc_ObjId(pObj), Abc_ObjId(pFanin) );
Vec_PtrFree( vNodes );
// sanity check
Bbl_ManCheck( p );
return p;
}
/**Function*************************************************************
Synopsis [Writes the AIG in the binary format.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteBblif( Abc_Ntk_t * pNtk, char * pFileName )
{
Bbl_Man_t * p;
p = Bbl_ManFromAbc( pNtk );
//Bbl_ManPrintStats( p );
//Bbl_ManDumpBlif( p, "test_bbl.blif" );
Bbl_ManDumpBinaryBlif( p, pFileName );
Bbl_ManStop( p );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/base/io/module.make
SRC += src/base/io/io.c \
src/base/io/ioReadAiger.c \
src/base/io/ioReadBaf.c \
src/base/io/ioReadBblif.c \
src/base/io/ioReadBench.c \
src/base/io/ioReadBlif.c \
src/base/io/ioReadBlifAig.c \
......@@ -13,6 +14,7 @@ SRC += src/base/io/io.c \
src/base/io/ioUtil.c \
src/base/io/ioWriteAiger.c \
src/base/io/ioWriteBaf.c \
src/base/io/ioWriteBblif.c \
src/base/io/ioWriteBench.c \
src/base/io/ioWriteBlif.c \
src/base/io/ioWriteBlifMv.c \
......
src/base/ver/verCore.c
......@@ -623,7 +623,7 @@ void Ver_ParseRemoveSuffixTable( Ver_Man_t * pMan )
***********************************************************************/
int Ver_ParseSignalPrefix( Ver_Man_t * pMan, char ** ppWord, int * pnMsb, int * pnLsb )
{
char * pWord = *ppWord;
char * pWord = *ppWord, * pTemp;
int nMsb, nLsb;
assert( pWord[0] == '[' );
// get the beginning
......@@ -654,6 +654,17 @@ int Ver_ParseSignalPrefix( Ver_Man_t * pMan, char ** ppWord, int * pnMsb, int *
}
assert( *pWord == ']' );
pWord++;
// fix the case when \<name> follows after [] without space
if ( *pWord == '\\' )
{
pWord++;
pTemp = pWord;
while ( *pTemp && *pTemp != ' ' )
pTemp++;
if ( *pTemp == ' ' )
*pTemp = 0;
}
}
assert( nMsb >= 0 && nLsb >= 0 );
// return
......
src/base/ver/verParse.c
......@@ -101,6 +101,15 @@ char * Ver_ParseGetName( Ver_Man_t * pMan )
pMan->fNameLast = 1;
Ver_StreamPopChar( p );
pWord = Ver_StreamGetWord( p, " \r\n" );
Ver_StreamSkipChars( p, " \r\n" );
if ( Ver_StreamScanChar(p) == '[' )
{
char This, * pEnd = pWord + strlen( pWord );
while ( (This = Ver_StreamPopChar(p)) != ']' )
*pEnd++ = This;
*pEnd++ = This;
*pEnd = 0;
}
}
else
pWord = Ver_StreamGetWord( p, " \t\n\r(),;" );
......
src/map/amap/amapLiberty.c
......@@ -346,6 +346,7 @@ int Amap_LibertyPrintGenlib( Amap_Tree_t * p, char * pFileName )
{
FILE * pFile;
Amap_Item_t * pCell, * pArea, * pFunc, * pPin, * pOutput;
char * pForm;
int Counter;
if ( pFileName == NULL )
pFile = stdout;
......@@ -408,6 +409,12 @@ int Amap_LibertyPrintGenlib( Amap_Tree_t * p, char * pFileName )
}
pOutput = Amap_LibertyCellOutput( p, pCell );
pFunc = Amap_LibertyPinFunction( p, pOutput );
pForm = Amap_LibertyGetStringFormula( p, pFunc->Head );
if ( !strcmp(pForm, "0") || !strcmp(pForm, "1") )
{
printf( "Amap_LibertyPrintGenlib() skipped cell \"%s\" with constant formula \"%s\".\n", Amap_LibertyGetString(p, pCell->Head), pForm );
continue;
}
fprintf( pFile, "GATE " );
fprintf( pFile, "%16s ", Amap_LibertyGetString(p, pCell->Head) );
......@@ -542,13 +549,17 @@ static inline int Amap_LibertyCharIsSpace( char c )
SeeAlso []
***********************************************************************/
static inline int Amap_LibertySkipSpaces( Amap_Tree_t * p, char ** ppPos, char * pEnd )
static inline int Amap_LibertySkipSpaces( Amap_Tree_t * p, char ** ppPos, char * pEnd, int fStopAtNewLine )
{
char * pPos = *ppPos;
for ( ; pPos < pEnd; pPos++ )
{
if ( *pPos == '\n' )
{
p->nLines++;
if ( fStopAtNewLine )
break;
}
if ( !Amap_LibertyCharIsSpace(*pPos) )
break;
}
......@@ -582,9 +593,9 @@ static inline int Amap_LibertySkipEntry( char ** ppPos, char * pEnd )
else
{
for ( ; pPos < pEnd; pPos++ )
if ( *pPos == ' ' ||
*pPos == ':' || *pPos == ';' ||
*pPos == '(' || *pPos == ')' ||
if ( *pPos == ' ' || *pPos == '\r' || *pPos == '\n' ||
*pPos == ':' || *pPos == ';' ||
*pPos == '(' || *pPos == ')' ||
*pPos == '{' || *pPos == '}' )
break;
}
......@@ -708,28 +719,28 @@ int Amap_LibertyBuildItem( Amap_Tree_t * p, char ** ppPos, char * pEnd )
Amap_Item_t * pItem;
Amap_Pair_t Key, Head, Body;
char * pNext, * pStop;
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd ) )
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd, 0 ) )
return -2;
Key.Beg = *ppPos - p->pContents;
if ( Amap_LibertySkipEntry( ppPos, pEnd ) )
goto exit;
Key.End = *ppPos - p->pContents;
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd ) )
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd, 0 ) )
goto exit;
pNext = *ppPos;
if ( *pNext == ':' )
{
*ppPos = pNext + 1;
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd ) )
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd, 0 ) )
goto exit;
Head.Beg = *ppPos - p->pContents;
if ( Amap_LibertySkipEntry( ppPos, pEnd ) )
goto exit;
Head.End = *ppPos - p->pContents;
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd ) )
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd, 1 ) )
goto exit;
pNext = *ppPos;
if ( *pNext != ';' )
if ( *pNext != ';' && *pNext != '\n' )
goto exit;
*ppPos = pNext + 1;
// end of equation
......@@ -747,7 +758,7 @@ int Amap_LibertyBuildItem( Amap_Tree_t * p, char ** ppPos, char * pEnd )
Head.Beg = pNext - p->pContents + 1;
Head.End = pStop - p->pContents;
*ppPos = pStop + 1;
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd ) )
if ( Amap_LibertySkipSpaces( p, ppPos, pEnd, 0 ) )
{
// end of list
pItem = Amap_LibertyNewItem( p, AMAP_LIBERTY_LIST );
......@@ -883,7 +894,7 @@ int Amap_LibertyParse( char * pFileName, char * pFileGenlib, int fVerbose )
{
if ( fVerbose )
printf( "Parsing finished successfully.\n" );
// Amap_LibertyPrintLiberty( p, "temp.lib" );
// Amap_LibertyPrintLiberty( p, "temp_.lib" );
Amap_LibertyPrintGenlib( p, "temp.genlib" );
RetValue = 1;
}
......
src/map/amap/amapParse.c
......@@ -35,6 +35,7 @@
#define AMAP_EQN_SYM_AND '*' // logic AND
#define AMAP_EQN_SYM_XOR '^' // logic XOR
#define AMAP_EQN_SYM_OR '+' // logic OR
#define AMAP_EQN_SYM_OR2 '|' // logic OR
// the list of opcodes (also specifying operation precedence)
#define AMAP_EQN_OPER_NEG 10 // negation
......@@ -180,6 +181,7 @@ Hop_Obj_t * Amap_ParseFormula( FILE * pOutput, char * pFormInit, Vec_Ptr_t * vVa
break;
case AMAP_EQN_SYM_AND:
case AMAP_EQN_SYM_OR:
case AMAP_EQN_SYM_OR2:
case AMAP_EQN_SYM_XOR:
if ( Flag != AMAP_EQN_FLAG_VAR )
{
......@@ -189,7 +191,7 @@ Hop_Obj_t * Amap_ParseFormula( FILE * pOutput, char * pFormInit, Vec_Ptr_t * vVa
}
if ( *pTemp == AMAP_EQN_SYM_AND )
Vec_IntPush( pStackOp, AMAP_EQN_OPER_AND );
else if ( *pTemp == AMAP_EQN_SYM_OR )
else if ( *pTemp == AMAP_EQN_SYM_OR || *pTemp == AMAP_EQN_SYM_OR2 )
Vec_IntPush( pStackOp, AMAP_EQN_OPER_OR );
else //if ( *pTemp == AMAP_EQN_SYM_XOR )
Vec_IntPush( pStackOp, AMAP_EQN_OPER_XOR );
......@@ -246,9 +248,9 @@ Hop_Obj_t * Amap_ParseFormula( FILE * pOutput, char * pFormInit, Vec_Ptr_t * vVa
// scan the next name
for ( i = 0; pTemp[i] &&
pTemp[i] != ' ' && pTemp[i] != '\t' && pTemp[i] != '\r' && pTemp[i] != '\n' &&
pTemp[i] != AMAP_EQN_SYM_AND && pTemp[i] != AMAP_EQN_SYM_OR &&
pTemp[i] != AMAP_EQN_SYM_XOR && pTemp[i] != AMAP_EQN_SYM_NEGAFT &&
pTemp[i] != AMAP_EQN_SYM_CLOSE; i++ )
pTemp[i] != AMAP_EQN_SYM_AND && pTemp[i] != AMAP_EQN_SYM_OR && pTemp[i] != AMAP_EQN_SYM_OR2 &&
pTemp[i] != AMAP_EQN_SYM_XOR && pTemp[i] != AMAP_EQN_SYM_NEGAFT && pTemp[i] != AMAP_EQN_SYM_CLOSE;
i++ )
{
if ( pTemp[i] == AMAP_EQN_SYM_NEG || pTemp[i] == AMAP_EQN_SYM_OPEN )
{
......
src/map/if/ifCore.c
......@@ -55,13 +55,10 @@ int If_ManPerformMapping( If_Man_t * p )
// try sequential mapping
if ( p->pPars->fSeqMap )
{
int RetValue = 1;
printf( "Currently sequential mapping is not performed.\n" );
// RetValue = If_ManPerformMappingSeq( p );
return RetValue;
// return 1;
// if ( p->pPars->fVerbose )
printf( "Performing sequential mapping without retiming.\n" );
return If_ManPerformMappingSeq( p );
}
return If_ManPerformMappingComb( p );
}
......
src/map/if/ifMap.c
......@@ -169,7 +169,7 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
If_ObjForEachCut( pObj, pCut, i )
p->pPars->pFuncUser( p, pObj, pCut );
// ABC_FREE the cuts
// free the cuts
If_ManDerefNodeCutSet( p, pObj );
}
......@@ -253,7 +253,7 @@ void If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fP
if ( Mode && pObj->nRefs > 0 )
If_CutAreaRef( p, If_ObjCutBest(pObj) );
// ABC_FREE the cuts
// free the cuts
If_ManDerefChoiceCutSet( p, pObj );
}
......
src/map/if/ifSeq.c
......@@ -124,6 +124,16 @@ int If_ManPerformMappingRoundSeq( If_Man_t * p, int nIter )
int fVeryVerbose = 0;
int fChange = 0;
if ( nIter == 1 )
{
// if some latches depend on PIs, update their values
Vec_PtrForEachEntry( p->vLatchOrder, pObj, i )
{
If_ObjSetLValue( pObj, If_ObjLValue(If_ObjFanin0(pObj)) - p->Period );
If_ObjSetArrTime( pObj, If_ObjLValue(pObj) );
}
}
// map the internal nodes
p->nCutsMerged = 0;
If_ManForEachNode( p, pObj, i )
......@@ -158,13 +168,14 @@ int If_ManPerformMappingRoundSeq( If_Man_t * p, int nIter )
}
// compute area and delay
If_ManMarkMapping( p );
if ( fVeryVerbose )
{
p->RequiredGlo = If_ManDelayMax( p, 1 );
p->AreaGlo = If_ManScanMapping(p);
// p->AreaGlo = If_ManScanMapping(p);
printf( "S%d: Fi = %6.2f. Del = %6.2f. Area = %8.2f. Cuts = %8d. ",
nIter, (float)p->Period, p->RequiredGlo, p->AreaGlo, p->nCutsMerged );
PRT( "T", clock() - clk );
ABC_PRT( "T", clock() - clk );
}
return fChange;
}
......@@ -185,26 +196,26 @@ int If_ManBinarySearchPeriod( If_Man_t * p )
If_Obj_t * pObj;
int i, c, fConverged;
int fResetRefs = 0;
p->nAttempts++;
// reset initial LValues (PIs to 0; others to -inf)
If_ManForEachObj( p, pObj, i )
{
if ( If_ObjIsPi(pObj) || If_ObjIsConst1(pObj) )
{
If_ObjSetLValue( pObj, (float)0.0 );
If_ObjSetArrTime( pObj, (float)0.0 );
}
else
{
If_ObjSetLValue( pObj, (float)-IF_INFINITY );
If_ObjSetArrTime( pObj, (float)-IF_INFINITY );
}
If_ObjSetLValue( pObj, (float)-IF_INFINITY );
If_ObjSetArrTime( pObj, (float)-IF_INFINITY );
// undo any previous mapping, except for CIs
if ( If_ObjIsAnd(pObj) )
If_ObjCutBest(pObj)->nLeaves = 0;
}
pObj = If_ManConst1( p );
If_ObjSetLValue( pObj, (float)0.0 );
If_ObjSetArrTime( pObj, (float)0.0 );
If_ManForEachPi( p, pObj, i )
{
pObj = If_ManCi( p, i );
If_ObjSetLValue( pObj, (float)0.0 );
If_ObjSetArrTime( pObj, (float)0.0 );
}
// update all values iteratively
fConverged = 0;
......@@ -223,9 +234,10 @@ int If_ManBinarySearchPeriod( If_Man_t * p )
}
// report the results
If_ManMarkMapping( p );
if ( p->pPars->fVerbose )
{
p->AreaGlo = If_ManScanMapping(p);
// p->AreaGlo = If_ManScanMapping(p);
printf( "Attempt = %2d. Iters = %3d. Area = %10.2f. Fi = %6.2f. ", p->nAttempts, c, p->AreaGlo, (float)p->Period );
if ( fConverged )
printf( " Feasible" );
......@@ -279,15 +291,6 @@ void If_ManPerformMappingSeqPost( If_Man_t * p )
If_Obj_t * pObjLi, * pObjLo, * pObj;
int i;
// link the latch outputs (CIs) directly to the drivers of latch inputs (COs)
for ( i = 0; i < p->pPars->nLatches; i++ )
{
pObjLi = If_ManLi( p, i );
pObjLo = If_ManLo( p, i );
// printf( "%3d : %2d -> %2d \n", i,
// (int)If_ObjLValue(If_ObjFanin0(pObjLo)), (int)If_ObjLValue(pObjLo) );
}
// set arrival times
assert( p->pPars->pTimesArr != NULL );
If_ManForEachLatchOutput( p, pObjLo, i )
......@@ -295,7 +298,7 @@ void If_ManPerformMappingSeqPost( If_Man_t * p )
// set the required times
assert( p->pPars->pTimesReq == NULL );
p->pPars->pTimesReq = ALLOC( float, If_ManCoNum(p) );
p->pPars->pTimesReq = ABC_ALLOC( float, If_ManCoNum(p) );
If_ManForEachPo( p, pObj, i )
{
p->pPars->pTimesReq[i] = p->RequiredGlo2;
......@@ -338,7 +341,7 @@ int If_ManPerformMappingSeq( If_Man_t * p )
// perform combinational mapping to get the upper bound on the clock period
If_ManPerformMappingRound( p, 1, 0, 0, NULL );
p->RequiredGlo = If_ManDelayMax( p, 0 );
p->RequiredGlo = If_ManDelayMax( p, 0 );
p->RequiredGlo2 = p->RequiredGlo;
// set direct linking of latches with their inputs
......@@ -373,24 +376,12 @@ int If_ManPerformMappingSeq( If_Man_t * p )
return 0;
}
}
if ( p->pPars->fVerbose )
// if ( p->pPars->fVerbose )
{
/*
{
FILE * pTable;
pTable = fopen( "iscas/stats_new.txt", "a+" );
// fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%d ", p->Period );
// fprintf( pTable, "%.2f ", (float)(s_MappingMem)/(float)(1<<20) );
// fprintf( pTable, "%.2f", (float)(s_MappingTime)/(float)(CLOCKS_PER_SEC) );
// fprintf( pTable, "\n" );
fclose( pTable );
}
*/
printf( "The best clock period is %3d. ", p->Period );
PRT( "Sequential time", clock() - clkTotal );
ABC_PRT( "Time", clock() - clkTotal );
}
p->RequiredGlo = (float)PeriodBest;
p->RequiredGlo = (float)(PeriodBest);
// postprocess it using combinational mapping
If_ManPerformMappingSeqPost( p );
......
src/map/if/module.make
......@@ -4,6 +4,7 @@ SRC += src/map/if/ifCore.c \
src/map/if/ifMan.c \
src/map/if/ifMap.c \
src/map/if/ifReduce.c \
src/map/if/ifSeq.c \
src/map/if/ifTime.c \
src/map/if/ifTruth.c \
src/map/if/ifUtil.c
src/misc/vec/vecFlt.h
......@@ -383,6 +383,8 @@ static inline void Vec_FltFillExtra( Vec_Flt_t * p, int nSize, float Entry )
int i;
if ( p->nSize >= nSize )
return;
if ( nSize < 2 * p->nSize )
nSize = 2 * p->nSize;
Vec_FltGrow( p, nSize );
for ( i = p->nSize; i < nSize; i++ )
p->pArray[i] = Entry;
......
src/misc/vec/vecInt.h
......@@ -409,10 +409,9 @@ static inline void Vec_IntFillExtra( Vec_Int_t * p, int nSize, int Fill )
int i;
if ( p->nSize >= nSize )
return;
if ( 2 * p->nSize > nSize )
Vec_IntGrow( p, 2 * nSize );
else
Vec_IntGrow( p, nSize );
if ( nSize < 2 * p->nSize )
nSize = 2 * p->nSize;
Vec_IntGrow( p, nSize );
for ( i = p->nSize; i < nSize; i++ )
p->pArray[i] = Fill;
p->nSize = nSize;
......@@ -743,6 +742,28 @@ static inline int Vec_IntFindMin( Vec_Int_t * p )
/**Function*************************************************************
Synopsis [Reverses the order of entries.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_IntReverseOrder( Vec_Int_t * p )
{
int i, Temp;
for ( i = 0; i < p->nSize/2; i++ )
{
Temp = p->pArray[i];
p->pArray[i] = p->pArray[p->nSize-1-i];
p->pArray[p->nSize-1-i] = Temp;
}
}
/**Function*************************************************************
Synopsis [Comparison procedure for two integers.]
Description []
......
src/misc/vec/vecPtr.h
......@@ -388,10 +388,9 @@ static inline void Vec_PtrFillExtra( Vec_Ptr_t * p, int nSize, void * Entry )
if ( p->nSize >= nSize )
return;
assert( p->nSize < nSize );
if ( 2 * p->nSize > nSize )
Vec_PtrGrow( p, 2 * nSize );
else
Vec_PtrGrow( p, nSize );
if ( nSize < 2 * p->nSize )
nSize = 2 * p->nSize;
Vec_PtrGrow( p, nSize );
for ( i = p->nSize; i < nSize; i++ )
p->pArray[i] = Entry;
p->nSize = nSize;
......@@ -616,6 +615,29 @@ static inline void Vec_PtrReorder( Vec_Ptr_t * p, int nItems )
/**Function*************************************************************
Synopsis [Reverses the order of entries.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_PtrReverseOrder( Vec_Ptr_t * p )
{
void * Temp;
int i;
for ( i = 0; i < p->nSize/2; i++ )
{
Temp = p->pArray[i];
p->pArray[i] = p->pArray[p->nSize-1-i];
p->pArray[p->nSize-1-i] = Temp;
}
}
/**Function*************************************************************
Synopsis [Sorting the entries by their integer value.]
Description []
......
src/misc/vec/vecStr.h
......@@ -361,10 +361,9 @@ static inline void Vec_StrFillExtra( Vec_Str_t * p, int nSize, char Fill )
int i;
if ( p->nSize >= nSize )
return;
if ( 2 * p->nSize > nSize )
Vec_StrGrow( p, 2 * nSize );
else
Vec_StrGrow( p, nSize );
if ( nSize < 2 * p->nSize )
nSize = 2 * p->nSize;
Vec_StrGrow( p, nSize );
for ( i = p->nSize; i < nSize; i++ )
p->pArray[i] = Fill;
p->nSize = nSize;
......
src/opt/dec/decAbc.c
......@@ -66,6 +66,53 @@ Abc_Obj_t * Dec_GraphToNetwork( Abc_Ntk_t * pNtk, Dec_Graph_t * pGraph )
Synopsis [Transforms the decomposition graph into the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Dec_SopToAig( Abc_Ntk_t * pNtk, char * pSop, Vec_Ptr_t * vFaninAigs )
{
Abc_Obj_t * pFunc;
Dec_Graph_t * pFForm;
Dec_Node_t * pNode;
int i;
pFForm = Dec_Factor( pSop );
Dec_GraphForEachLeaf( pFForm, pNode, i )
pNode->pFunc = Vec_PtrEntry( vFaninAigs, i );
pFunc = Dec_GraphToNetwork( pNtk, pFForm );
Dec_GraphFree( pFForm );
return pFunc;
}
/**Function*************************************************************
Synopsis [Transforms the decomposition graph into the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Dec_GraphToAig( Abc_Ntk_t * pNtk, Dec_Graph_t * pFForm, Vec_Ptr_t * vFaninAigs )
{
Abc_Obj_t * pFunc;
Dec_Node_t * pNode;
int i;
Dec_GraphForEachLeaf( pFForm, pNode, i )
pNode->pFunc = Vec_PtrEntry( vFaninAigs, i );
pFunc = Dec_GraphToNetwork( pNtk, pFForm );
return pFunc;
}
/**Function*************************************************************
Synopsis [Transforms the decomposition graph into the AIG.]
Description [AIG nodes for the fanins should be assigned to pNode->pFunc
of the leaves of the graph before calling this procedure.]
......
src/sat/bsat/satSolver.c
......@@ -851,6 +851,7 @@ static lbool sat_solver_search(sat_solver* s, ABC_INT64_T nof_conflicts, ABC_INT
// use activity factors in every even restart
if ( (s->nRestarts & 1) && veci_size(&s->act_vars) > 0 )
// if ( veci_size(&s->act_vars) > 0 )
for ( i = 0; i < s->act_vars.size; i++ )
act_var_bump_factor(s, s->act_vars.ptr[i]);
......
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