Logic sharing for multi-input gates.

abclib.dsp

@@ -423,6 +423,10 @@ SOURCE=.\src\base\abci\abcSense.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\base\abci\abcShare.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\base\abci\abcSpeedup.c
 # End Source File
 # Begin Source File

src/base/abc/abc.h

@@ -400,6 +400,9 @@ static inline Abc_Obj_t * Abc_ObjChild1Data( Abc_Obj_t * pObj )      { return Ab
 //static inline Hop_Obj_t * Abc_ObjChild0Equiv( Abc_Obj_t * pObj )     { return Hop_NotCond( Abc_ObjFanin0(pObj)->pEquiv, Abc_ObjFaninC0(pObj) );      }
 //static inline Hop_Obj_t * Abc_ObjChild1Equiv( Abc_Obj_t * pObj )     { return Hop_NotCond( Abc_ObjFanin1(pObj)->pEquiv, Abc_ObjFaninC1(pObj) );      }
 
+static inline Abc_Obj_t * Abc_ObjFromLit( Abc_Ntk_t * p, int iLit )  { return Abc_ObjNotCond( Abc_NtkObj(p, Abc_Lit2Var(iLit)), Abc_LitIsCompl(iLit) );           }
+static inline int         Abc_ObjToLit( Abc_Obj_t * p )              { return Abc_Var2Lit( Abc_ObjId(Abc_ObjRegular(p)), Abc_ObjIsComplement(p) );                }
+
 // checking the AIG node types
 static inline int         Abc_AigNodeIsConst( Abc_Obj_t * pNode )    { assert(Abc_NtkIsStrash(Abc_ObjRegular(pNode)->pNtk));  return Abc_ObjRegular(pNode)->Type == ABC_OBJ_CONST1;       }
 static inline int         Abc_AigNodeIsAnd( Abc_Obj_t * pNode )      { assert(!Abc_ObjIsComplement(pNode)); assert(Abc_NtkIsStrash(pNode->pNtk)); return Abc_ObjFaninNum(pNode) == 2;                         }

src/base/abci/abc.c

@@ -9009,6 +9009,7 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
 
     if ( pNtk )
     {
+/*
         Aig_Man_t * pAig = Abc_NtkToDar( pNtk, 0, 1 );
         if ( fNewAlgo )
             Saig_IsoDetectFast( pAig );
@@ -9018,6 +9019,9 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
             Aig_ManStopP( &pRes );
         }
         Aig_ManStop( pAig );
+*/
+        extern void Abc_NtkShareXor( Abc_Ntk_t * pNtk );
+        Abc_NtkShareXor( pNtk );
     }
 
 //    Abc2_NtkTestGia( "", 1 );

src/base/abci/module.make

@@ -55,6 +55,7 @@ SRC +=    src/base/abci/abc.c \
     src/base/abci/abcSat.c \
     src/base/abci/abcScorr.c \
     src/base/abci/abcSense.c \
+    src/base/abci/abcShare.c \
     src/base/abci/abcSpeedup.c \
     src/base/abci/abcStrash.c \
     src/base/abci/abcSweep.c \

src/misc/vec/vecInt.h

@@ -1251,6 +1251,38 @@ static inline Vec_Int_t * Vec_IntTwoMerge( Vec_Int_t * vArr1, Vec_Int_t * vArr2
     return vArr;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Returns the result of merging the two vectors.]
+
+  Description [Assumes that the vectors are sorted in the increasing order.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+static inline void Vec_IntTwoSplit( Vec_Int_t * vArr1, Vec_Int_t * vArr2, Vec_Int_t * vArr, Vec_Int_t * vArr1n, Vec_Int_t * vArr2n )
+{
+    int * pBeg1 = vArr1->pArray;
+    int * pBeg2 = vArr2->pArray;
+    int * pEnd1 = vArr1->pArray + vArr1->nSize;
+    int * pEnd2 = vArr2->pArray + vArr2->nSize;
+    while ( pBeg1 < pEnd1 && pBeg2 < pEnd2 )
+    {
+        if ( *pBeg1 == *pBeg2 )
+            Vec_IntPush( vArr, *pBeg1++ ), pBeg2++;
+        else if ( *pBeg1 < *pBeg2 )
+            Vec_IntPush( vArr1n, *pBeg1++ );
+        else 
+            Vec_IntPush( vArr2n, *pBeg2++ );
+    }
+    while ( pBeg1 < pEnd1 )
+        Vec_IntPush( vArr1n, *pBeg1++ );
+    while ( pBeg2 < pEnd2 )
+        Vec_IntPush( vArr2n, *pBeg2++ );
+}
+
 
 /**Function*************************************************************