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Commit 236d4122 by Alan Mishchenko
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Experiments with CEC for arithmetic circuits.

parent 40d90ae6
Showing with 687 additions and 23 deletions
Makefile
......@@ -27,7 +27,7 @@ MODULES := \
src/bool/bdc src/bool/deco src/bool/dec src/bool/kit src/bool/lucky \
src/bool/rsb src/bool/rpo \
src/proof/pdr src/proof/abs src/proof/live src/proof/ssc src/proof/int \
src/proof/cec src/proof/dch src/proof/fraig src/proof/fra src/proof/ssw \
src/proof/cec src/proof/acec src/proof/dch src/proof/fraig src/proof/fra src/proof/ssw \
src/aig/aig src/aig/saig src/aig/gia src/aig/ioa src/aig/ivy src/aig/hop \
src/aig/miniaig
......
abclib.dsp
......@@ -4231,10 +4231,6 @@ SOURCE=.\src\aig\gia\giaEsop.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaFadds.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaFalse.c
# End Source File
# Begin Source File
......@@ -4347,10 +4343,6 @@ SOURCE=.\src\aig\gia\giaPf.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaPolyn.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaQbf.c
# End Source File
# Begin Source File
......@@ -5298,6 +5290,38 @@ SOURCE=.\src\proof\ssc\sscUtil.c
# PROP Default_Filter ""
# End Group
# Begin Group "acec"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\proof\acec\acec.h
# End Source File
# Begin Source File
SOURCE=.\src\proof\acec\acecCore.c
# End Source File
# Begin Source File
SOURCE=.\src\proof\acec\acecFadds.c
# End Source File
# Begin Source File
SOURCE=.\src\proof\acec\acecInt.h
# End Source File
# Begin Source File
SOURCE=.\src\proof\acec\acecOrder.c
# End Source File
# Begin Source File
SOURCE=.\src\proof\acec\acecPolyn.c
# End Source File
# Begin Source File
SOURCE=.\src\proof\acec\acecUtil.c
# End Source File
# End Group
# End Group
# End Group
# Begin Group "Header Files"
......
src/aig/gia/gia.h
......@@ -1149,6 +1149,7 @@ extern Gia_Man_t * Gia_ManDupCofAllInt( Gia_Man_t * p, Vec_Int_t * vSigs
extern Gia_Man_t * Gia_ManDupCofAll( Gia_Man_t * p, int nFanLim, int fVerbose );
/*=== giaDfs.c ============================================================*/
extern void Gia_ManCollectCis( Gia_Man_t * p, int * pNodes, int nNodes, Vec_Int_t * vSupp );
extern void Gia_ManCollectAnds_rec( Gia_Man_t * p, int iObj, Vec_Int_t * vNodes );
extern void Gia_ManCollectAnds( Gia_Man_t * p, int * pNodes, int nNodes, Vec_Int_t * vNodes, Vec_Int_t * vLeaves );
extern Vec_Int_t * Gia_ManCollectNodesCis( Gia_Man_t * p, int * pNodes, int nNodes );
extern int Gia_ManSuppSize( Gia_Man_t * p, int * pNodes, int nNodes );
......@@ -1209,10 +1210,15 @@ extern Gia_Man_t * Gia_ManTransformToDual( Gia_Man_t * p );
extern Gia_Man_t * Gia_ManChoiceMiter( Vec_Ptr_t * vGias );
extern Gia_Man_t * Gia_ManDupWithConstraints( Gia_Man_t * p, Vec_Int_t * vPoTypes );
extern Gia_Man_t * Gia_ManDupCones( Gia_Man_t * p, int * pPos, int nPos, int fTrimPis );
extern Gia_Man_t * Gia_ManDupAndCones( Gia_Man_t * p, int * pAnds, int nAnds, int fTrimPis );
extern Gia_Man_t * Gia_ManDupOneHot( Gia_Man_t * p );
extern Gia_Man_t * Gia_ManDupLevelized( Gia_Man_t * p );
extern Gia_Man_t * Gia_ManDupFromVecs( Gia_Man_t * p, Vec_Int_t * vCis, Vec_Int_t * vAnds, Vec_Int_t * vCos, int nRegs );
extern Gia_Man_t * Gia_ManDupSliced( Gia_Man_t * p, int nSuppMax );
extern Gia_Man_t * Gia_ManDupDemiter( Gia_Man_t * p, int fVerbose );
extern Gia_Man_t * Gia_ManDemiterToDual( Gia_Man_t * p );
extern int Gia_ManDemiterDual( Gia_Man_t * p, Gia_Man_t ** pp0, Gia_Man_t ** pp1 );
extern int Gia_ManDemiterTwoWords( Gia_Man_t * p, Gia_Man_t ** pp0, Gia_Man_t ** pp1 );
/*=== giaEdge.c ==========================================================*/
extern void Gia_ManEdgeFromArray( Gia_Man_t * p, Vec_Int_t * vArray );
extern Vec_Int_t * Gia_ManEdgeToArray( Gia_Man_t * p );
......
src/aig/gia/giaBalLut.c
......@@ -568,7 +568,7 @@ static inline void Vec_IntSelectSortCostLit( Vec_Int_t * vSuper, Vec_Int_t * vCo
ABC_SWAP( int, pArray[i], pArray[best_i] );
}
}
static inline void Vec_IntPushOrderCost( Vec_Int_t * vSuper, Vec_Int_t * vCosts, int iLit )
static inline void Vec_IntPushOrderCost2( Vec_Int_t * vSuper, Vec_Int_t * vCosts, int iLit )
{
int i, nSize, * pArray;
Vec_IntPush( vSuper, iLit );
......@@ -853,7 +853,7 @@ static inline int Gia_ManBalanceGate( Gia_Man_t * pNew, Gia_Obj_t * pObj, Vec_In
else
iLit = Gia_ManHashAnd( pNew, iBest, kBest );
Bal_ManSetGateLevel( p, pObj, iLit );
Vec_IntPushOrderCost( vSuper, p->vCosts, iLit );
Vec_IntPushOrderCost2( vSuper, p->vCosts, iLit );
}
}
// consider trivial case
......
src/aig/gia/giaDfs.c
......@@ -136,7 +136,7 @@ void Gia_ManCollectAnds( Gia_Man_t * p, int * pNodes, int nNodes, Vec_Int_t * vN
Gia_Obj_t * pObj = Gia_ManObj( p, pNodes[i] );
if ( Gia_ObjIsCo(pObj) )
Gia_ManCollectAnds_rec( p, Gia_ObjFaninId0(pObj, pNodes[i]), vNodes );
else
else if ( Gia_ObjIsAnd(pObj) )
Gia_ManCollectAnds_rec( p, pNodes[i], vNodes );
}
}
......
src/aig/gia/giaHash.c
......@@ -575,6 +575,7 @@ int Gia_ManHashMuxReal( Gia_Man_t * p, int iLitC, int iLit1, int iLit0 )
***********************************************************************/
int Gia_ManHashAnd( Gia_Man_t * p, int iLit0, int iLit1 )
{
// return Gia_ManAppendAnd2( p, iLit0, iLit1 );
if ( iLit0 < 2 )
return iLit0 ? iLit1 : 0;
if ( iLit1 < 2 )
......
src/aig/gia/giaMuxes.c
......@@ -100,7 +100,7 @@ Gia_Man_t * Gia_ManDupMuxes( Gia_Man_t * p, int Limit )
Gia_Obj_t * pObj, * pFan0, * pFan1, * pFanC, * pSiblNew, * pObjNew;
int i;
assert( p->pMuxes == NULL );
assert( Limit >= 2 );
assert( Limit >= 1 ); // allows to create AIG with XORs without MUXes
ABC_FREE( p->pRefs );
Gia_ManCreateRefs( p );
// start the new manager
......
src/aig/gia/giaShow.c
......@@ -50,9 +50,9 @@ void Gia_WriteDotAig( Gia_Man_t * pMan, char * pFileName, Vec_Int_t * vBold )
int LevelMax, Prev, Level, i;
int fConstIsUsed = 0;
if ( Gia_ManAndNum(pMan) > 200 )
if ( Gia_ManAndNum(pMan) > 300 )
{
fprintf( stdout, "Cannot visualize AIG with more than 200 nodes.\n" );
fprintf( stdout, "Cannot visualize AIG with more than 300 nodes.\n" );
return;
}
if ( (pFile = fopen( pFileName, "w" )) == NULL )
......
src/aig/gia/module.make
......@@ -23,7 +23,6 @@ SRC += src/aig/gia/giaAig.c \
src/aig/gia/giaEra.c \
src/aig/gia/giaEra2.c \
src/aig/gia/giaEsop.c \
src/aig/gia/giaFadds.c \
src/aig/gia/giaFalse.c \
src/aig/gia/giaFanout.c \
src/aig/gia/giaForce.c \
......@@ -52,7 +51,6 @@ SRC += src/aig/gia/giaAig.c \
src/aig/gia/giaPack.c \
src/aig/gia/giaPat.c \
src/aig/gia/giaPf.c \
src/aig/gia/giaPolyn.c \
src/aig/gia/giaQbf.c \
src/aig/gia/giaResub.c \
src/aig/gia/giaRetime.c \
......
src/base/wlc/wlc.h
......@@ -125,6 +125,7 @@ typedef struct Wlc_Ntk_t_ Wlc_Ntk_t;
struct Wlc_Ntk_t_
{
char * pName; // model name
char * pSpec; // input file name
Vec_Int_t vPis; // primary inputs
Vec_Int_t vPos; // primary outputs
Vec_Int_t vCis; // combinational inputs
......
src/base/wlc/wlcBlast.c
......@@ -1327,6 +1327,7 @@ Gia_Man_t * Wlc_NtkBitBlast( Wlc_Ntk_t * p, Vec_Int_t * vBoxIds )
}
assert( Vec_PtrSize(pNew->vNamesOut) == Gia_ManCoNum(pNew) );
*/
pNew->pSpec = Abc_UtilStrsav( p->pSpec ? p->pSpec : p->pName );
return pNew;
}
......
src/base/wlc/wlcNtk.c
......@@ -223,6 +223,7 @@ void Wlc_NtkFree( Wlc_Ntk_t * p )
ABC_FREE( p->pInits );
ABC_FREE( p->pObjs );
ABC_FREE( p->pName );
ABC_FREE( p->pSpec );
ABC_FREE( p );
}
int Wlc_NtkMemUsage( Wlc_Ntk_t * p )
......@@ -587,6 +588,8 @@ Wlc_Ntk_t * Wlc_NtkDupDfs( Wlc_Ntk_t * p )
if ( p->pInits )
pNew->pInits = Abc_UtilStrsav( p->pInits );
Vec_IntFree( vFanins );
if ( p->pSpec )
pNew->pSpec = Abc_UtilStrsav( p->pSpec );
return pNew;
}
void Wlc_NtkTransferNames( Wlc_Ntk_t * pNew, Wlc_Ntk_t * p )
......@@ -658,6 +661,8 @@ Wlc_Ntk_t * Wlc_NtkDupSingleNodes( Wlc_Ntk_t * p )
}
Vec_IntFree( vFanins );
Wlc_NtkTransferNames( pNew, p );
if ( p->pSpec )
pNew->pSpec = Abc_UtilStrsav( p->pSpec );
return pNew;
}
......
src/base/wlc/wlcReadVer.c
......@@ -1264,6 +1264,7 @@ Wlc_Ntk_t * Wlc_ReadVer( char * pFileName )
finish:
Wlc_PrsPrintErrorMessage( p );
Wlc_PrsStop( p );
pNtk->pSpec = Abc_UtilStrsav( pFileName );
return pNtk;
}
......
src/misc/vec/vecInt.h
......@@ -804,6 +804,24 @@ static inline void Vec_IntPushOrder( Vec_Int_t * p, int Entry )
break;
p->pArray[i+1] = Entry;
}
static inline void Vec_IntPushOrderCost( Vec_Int_t * p, int Entry, Vec_Int_t * vCost )
{
int i;
if ( p->nSize == p->nCap )
{
if ( p->nCap < 16 )
Vec_IntGrow( p, 16 );
else
Vec_IntGrow( p, 2 * p->nCap );
}
p->nSize++;
for ( i = p->nSize-2; i >= 0; i-- )
if ( Vec_IntEntry(vCost, p->pArray[i]) > Vec_IntEntry(vCost, Entry) )
p->pArray[i+1] = p->pArray[i];
else
break;
p->pArray[i+1] = Entry;
}
/**Function*************************************************************
......@@ -855,6 +873,15 @@ static inline int Vec_IntPushUniqueOrder( Vec_Int_t * p, int Entry )
Vec_IntPushOrder( p, Entry );
return 0;
}
static inline int Vec_IntPushUniqueOrderCost( Vec_Int_t * p, int Entry, Vec_Int_t * vCost )
{
int i;
for ( i = 0; i < p->nSize; i++ )
if ( p->pArray[i] == Entry )
return 1;
Vec_IntPushOrderCost( p, Entry, vCost );
return 0;
}
/**Function*************************************************************
......
src/proof/acec/acec.c 0 → 100644
/**CFile****************************************************************
FileName [acec.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis []
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: acec.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "acecInt.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END
src/proof/acec/acec.h 0 → 100644
/**CFile****************************************************************
FileName [acec.h]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis [External declarations.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: acec.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#ifndef ABC__proof__acec__acec_h
#define ABC__proof__acec__acec_h
////////////////////////////////////////////////////////////////////////
/// INCLUDES ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_HEADER_START
////////////////////////////////////////////////////////////////////////
/// BASIC TYPES ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// MACRO DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// ITERATORS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
/*=== acecCore.c ========================================================*/
extern int Gia_PolynCec( Gia_Man_t * pGia0, Gia_Man_t * pGia1, Cec_ParCec_t * pPars );
/*=== acecMiter.c ========================================================*/
extern int Gia_ManDemiterDual( Gia_Man_t * p, Gia_Man_t ** pp0, Gia_Man_t ** pp1 );
extern int Gia_ManDemiterXor( Gia_Man_t * p, Gia_Man_t ** pp0, Gia_Man_t ** pp1 );
ABC_NAMESPACE_HEADER_END
#endif
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/proof/acec/acecCore.c 0 → 100644
/**CFile****************************************************************
FileName [acecCore.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis [Core procedures.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: acecCore.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "acecInt.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_PolynCec( Gia_Man_t * pGia0, Gia_Man_t * pGia1, Cec_ParCec_t * pPars )
{
Vec_Int_t * vOrder0 = Gia_PolynReorder( pGia0, pPars->fVerbose );
Vec_Int_t * vOrder1 = Gia_PolynReorder( pGia1, pPars->fVerbose );
Gia_PolynBuild( pGia0, vOrder0, pPars->fVerbose );
Gia_PolynBuild( pGia1, vOrder1, pPars->fVerbose );
return 1;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END
src/aig/gia/giaFadds.c → src/proof/acec/acecFadds.c
/**CFile****************************************************************
FileName [giaFadds.c]
FileName [acecFadds.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Scalable AIG package.]
PackageName [CEC for arithmetic circuits.]
Synopsis [Extraction of full-adders.]
Synopsis [Detecting half-adders and full-adders.]
Author [Alan Mishchenko]
......@@ -14,11 +14,11 @@
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: giaFadds.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
Revision [$Id: acecFadds.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "gia.h"
#include "acecInt.h"
#include "misc/vec/vecWec.h"
#include "misc/tim/tim.h"
......@@ -38,6 +38,70 @@ ABC_NAMESPACE_IMPL_START
/**Function*************************************************************
Synopsis [Detecting HADDs in the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Gia_ManDetectHalfAdders( Gia_Man_t * p, int fVerbose )
{
Vec_Int_t * vHadds = Vec_IntAlloc( 1000 );
Gia_Obj_t * pObj, * pFan0, * pFan1;
int i, iLit, iFan0, iFan1, fComplDiff, Count, Counts[5] = {0};
ABC_FREE( p->pRefs );
Gia_ManCreateRefs( p );
Gia_ManHashStart( p );
Gia_ManForEachAnd( p, pObj, i )
{
if ( !Gia_ObjRecognizeExor(pObj, &pFan0, &pFan1) )
continue;
Count = 0;
if ( Gia_ObjRefNumId(p, Gia_ObjFaninId0(pObj, i)) > 1 )
Vec_IntPushTwo( vHadds, i, Gia_ObjFaninId0(pObj, i) ), Count++;
if ( Gia_ObjRefNumId(p, Gia_ObjFaninId1(pObj, i)) > 1 )
Vec_IntPushTwo( vHadds, i, Gia_ObjFaninId1(pObj, i) ), Count++;
iFan0 = Gia_ObjId( p, pFan0 );
iFan1 = Gia_ObjId( p, pFan1 );
fComplDiff = (Gia_ObjFaninC0(Gia_ObjFanin0(pObj)) ^ Gia_ObjFaninC1(Gia_ObjFanin0(pObj)));
assert( fComplDiff == (Gia_ObjFaninC0(Gia_ObjFanin1(pObj)) ^ Gia_ObjFaninC1(Gia_ObjFanin1(pObj))) );
if ( fComplDiff )
{
if ( (iLit = Gia_ManHashLookupInt(p, Abc_Var2Lit(iFan0, 0), Abc_Var2Lit(iFan1, 0))) )
Vec_IntPushTwo( vHadds, i, Abc_Lit2Var(iLit) ), Count++;
if ( (iLit = Gia_ManHashLookupInt(p, Abc_Var2Lit(iFan0, 1), Abc_Var2Lit(iFan1, 1))) )
Vec_IntPushTwo( vHadds, i, Abc_Lit2Var(iLit) ), Count++;
}
else
{
if ( (iLit = Gia_ManHashLookupInt(p, Abc_Var2Lit(iFan0, 0), Abc_Var2Lit(iFan1, 1))) )
Vec_IntPushTwo( vHadds, i, Abc_Lit2Var(iLit) ), Count++;
if ( (iLit = Gia_ManHashLookupInt(p, Abc_Var2Lit(iFan0, 1), Abc_Var2Lit(iFan1, 0))) )
Vec_IntPushTwo( vHadds, i, Abc_Lit2Var(iLit) ), Count++;
}
Counts[Count]++;
}
Gia_ManHashStop( p );
ABC_FREE( p->pRefs );
if ( fVerbose )
{
int iXor, iAnd;
printf( "Found %d half-adders with XOR gates: ", Vec_IntSize(vHadds)/2 );
for ( i = 0; i <= 4; i++ )
printf( "%d=%d ", i, Counts[i] );
printf( "\n" );
Vec_IntForEachEntryDouble( vHadds, iXor, iAnd, i )
printf( "%3d : %5d %5d\n", i, iXor, iAnd );
}
return vHadds;
}
/**Function*************************************************************
Synopsis [Derive GIA with boxes containing adder-chains.]
Description []
......@@ -176,6 +240,7 @@ int Dtc_ObjComputeTruth( Gia_Man_t * p, int iObj, int * pCut, int * pTruth )
}
void Dtc_ManCutMerge( Gia_Man_t * p, int iObj, int * pList0, int * pList1, Vec_Int_t * vCuts, Vec_Int_t * vCutsXor, Vec_Int_t * vCutsMaj )
{
int fVerbose = 0;
Vec_Int_t * vTemp;
int i, k, c, Type, * pCut0, * pCut1, pCut[4];
Vec_IntFill( vCuts, 2, 1 );
......@@ -196,8 +261,16 @@ void Dtc_ManCutMerge( Gia_Man_t * p, int iObj, int * pList0, int * pList1, Vec_I
if ( Type == 0 )
continue;
vTemp = Type == 1 ? vCutsXor : vCutsMaj;
if ( fVerbose )
printf( "%d = %s(", iObj, Type == 1 ? "XOR" : "MAJ" );
for ( c = 1; c <= pCut[0]; c++ )
{
if ( fVerbose )
printf( " %d", pCut[c] );
Vec_IntPush( vTemp, pCut[c] );
}
if ( fVerbose )
printf( " )\n" );
Vec_IntPush( vTemp, iObj );
}
}
......@@ -307,7 +380,8 @@ Vec_Int_t * Gia_ManDetectFullAdders( Gia_Man_t * p, int fVerbose )
qsort( Vec_IntArray(vFadds), Vec_IntSize(vFadds)/5, 20, (int (*)(const void *, const void *))Dtc_ManCompare2 );
if ( fVerbose )
printf( "XOR3 cuts = %d. MAJ cuts = %d. Full-adders = %d.\n", Vec_IntSize(vCutsXor)/4, Vec_IntSize(vCutsMaj)/4, Vec_IntSize(vFadds)/5 );
//Dtc_ManPrintFadds( vFadds );
if ( fVerbose )
Dtc_ManPrintFadds( vFadds );
Vec_IntFree( vCutsXor );
Vec_IntFree( vCutsMaj );
return vFadds;
......
src/proof/acec/acecInt.h 0 → 100644
/**CFile****************************************************************
FileName [acecInt.h]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis [Internal declarations.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: acecInt.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#ifndef ABC__proof__acec__acec__int_h
#define ABC__proof__acec__acec__int_h
////////////////////////////////////////////////////////////////////////
/// INCLUDES ///
////////////////////////////////////////////////////////////////////////
#include "aig/gia/gia.h"
#include "proof/cec/cec.h"
#include "acec.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_HEADER_START
////////////////////////////////////////////////////////////////////////
/// BASIC TYPES ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// MACRO DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// ITERATORS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
/*=== acecFadds.c ========================================================*/
extern Vec_Int_t * Gia_ManDetectFullAdders( Gia_Man_t * p, int fVerbose );
extern Vec_Int_t * Gia_ManDetectHalfAdders( Gia_Man_t * p, int fVerbose );
/*=== acecOrder.c ========================================================*/
extern Vec_Int_t * Gia_PolynReorder( Gia_Man_t * pGia, int fVerbose );
/*=== acecPolyn.c ========================================================*/
extern void Gia_PolynBuild( Gia_Man_t * pGia, Vec_Int_t * vOrder, int fVerbose );
/*=== acecUtil.c ========================================================*/
extern void Gia_PolynAnalyzeXors( Gia_Man_t * pGia, int fVerbose );
ABC_NAMESPACE_HEADER_END
#endif
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/proof/acec/acecOrder.c 0 → 100644
/**CFile****************************************************************
FileName [acecOrder.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis [Node ordering.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: acecOrder.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "acecInt.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Gia_PolynReorder( Gia_Man_t * pGia, int fVerbose )
{
int fDumpLeftOver = 0;
Vec_Int_t * vOrder, * vOrder2;
Gia_Obj_t * pFan0, * pFan1;
int i, k, iDriver, Iter, iXor, iMaj, Entry, fFound;
Vec_Int_t * vFadds = Gia_ManDetectFullAdders( pGia, fVerbose );
Vec_Int_t * vHadds = Gia_ManDetectHalfAdders( pGia, fVerbose );
Vec_Int_t * vRecord = Vec_IntAlloc( 100 );
Vec_Int_t * vMap = Vec_IntStart( Gia_ManObjNum(pGia) );
Gia_ManForEachCoDriverId( pGia, iDriver, i )
Vec_IntWriteEntry( vMap, iDriver, 1 );
for ( Iter = 0; ; Iter++ )
{
int fFoundAll = 0;
printf( "Iteration %d\n", Iter );
// find the last one
iDriver = -1;
Vec_IntForEachEntryReverse( vMap, Entry, i )
if ( Entry )
{
iDriver = i;
break;
}
if ( iDriver > 0 && Gia_ObjRecognizeExor(Gia_ManObj(pGia, iDriver), &pFan0, &pFan1) && Vec_IntFind(vFadds, iDriver) == -1 && Vec_IntFind(vHadds, iDriver) == -1 )
{
Vec_IntWriteEntry( vMap, iDriver, 0 );
Vec_IntWriteEntry( vMap, Gia_ObjId(pGia, pFan0), 1 );
Vec_IntWriteEntry( vMap, Gia_ObjId(pGia, pFan1), 1 );
Vec_IntPush( vRecord, iDriver );
printf( "Recognizing %d => XOR(%d %d)\n", iDriver, Gia_ObjId(pGia, pFan0), Gia_ObjId(pGia, pFan1) );
}
// check if we can extract FADDs
do {
fFound = 0;
for ( i = 0; i < Vec_IntSize(vFadds)/5; i++ )
{
iXor = Vec_IntEntry(vFadds, 5*i+3);
iMaj = Vec_IntEntry(vFadds, 5*i+4);
if ( Vec_IntEntry(vMap, iXor) && Vec_IntEntry(vMap, iMaj) )
{
Vec_IntWriteEntry( vMap, iXor, 0 );
Vec_IntWriteEntry( vMap, iMaj, 0 );
Vec_IntWriteEntry( vMap, Vec_IntEntry(vFadds, 5*i+0), 1 );
Vec_IntWriteEntry( vMap, Vec_IntEntry(vFadds, 5*i+1), 1 );
Vec_IntWriteEntry( vMap, Vec_IntEntry(vFadds, 5*i+2), 1 );
Vec_IntPush( vRecord, iXor );
Vec_IntPush( vRecord, iMaj );
fFound = 1;
fFoundAll = 1;
printf( "Recognizing (%d %d) => FA(%d %d %d)\n", iXor, iMaj, Vec_IntEntry(vFadds, 5*i+0), Vec_IntEntry(vFadds, 5*i+1), Vec_IntEntry(vFadds, 5*i+2) );
}
}
} while ( fFound );
// check if we can extract HADDs
do {
fFound = 0;
Vec_IntForEachEntryDouble( vHadds, iXor, iMaj, i )
{
if ( Vec_IntEntry(vMap, iXor) && Vec_IntEntry(vMap, iMaj) )
{
Gia_Obj_t * pAnd = Gia_ManObj( pGia, iMaj );
Vec_IntWriteEntry( vMap, iXor, 0 );
Vec_IntWriteEntry( vMap, iMaj, 0 );
Vec_IntWriteEntry( vMap, Gia_ObjFaninId0(pAnd, iMaj), 1 );
Vec_IntWriteEntry( vMap, Gia_ObjFaninId1(pAnd, iMaj), 1 );
Vec_IntPush( vRecord, iXor );
Vec_IntPush( vRecord, iMaj );
fFound = 1;
fFoundAll = 1;
printf( "Recognizing (%d %d) => HA(%d %d)\n", iXor, iMaj, Gia_ObjFaninId0(pAnd, iMaj), Gia_ObjFaninId1(pAnd, iMaj) );
}
}
} while ( fFound );
if ( fFoundAll == 0 )
break;
}
//Vec_IntPrint( vRecord );
printf( "Remaining: " );
Vec_IntForEachEntry( vMap, Entry, i )
if ( Entry )
printf( "%d ", i );
printf( "\n" );
// collect remaining nodes
k = 0;
Vec_IntForEachEntry( vMap, Entry, i )
if ( Entry && Gia_ObjIsAnd(Gia_ManObj(pGia, i)) )
Vec_IntWriteEntry( vMap, k++, i );
Vec_IntShrink( vMap, k );
// dump remaining nodes as an AIG
if ( fDumpLeftOver )
{
Gia_Man_t * pNew = Gia_ManDupAndCones( pGia, Vec_IntArray(vMap), Vec_IntSize(vMap), 0 );
Gia_AigerWrite( pNew, "leftover.aig", 0, 0 );
Gia_ManStop( pNew );
}
// collect nodes
vOrder = Vec_IntAlloc( Gia_ManAndNum(pGia) );
Gia_ManIncrementTravId( pGia );
Gia_ManCollectAnds( pGia, Vec_IntArray(vMap), Vec_IntSize(vMap), vOrder, NULL );
Vec_IntForEachEntryReverse( vRecord, Entry, i )
Gia_ManCollectAnds_rec( pGia, Entry, vOrder );
assert( Vec_IntSize(vOrder) == Gia_ManAndNum(pGia) );
// remap order
vOrder2 = Vec_IntStart( Gia_ManObjNum(pGia) );
Vec_IntForEachEntry( vOrder, Entry, i )
Vec_IntWriteEntry( vOrder2, Entry, i+1 );
Vec_IntFree( vOrder );
Vec_IntFree( vMap );
Vec_IntFree( vRecord );
Vec_IntFree( vFadds );
Vec_IntFree( vHadds );
return vOrder2;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END
src/proof/acec/acecUtil.c 0 → 100644
/**CFile****************************************************************
FileName [acecUtil.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis [Various utilities.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: acecUtil.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "acecInt.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_PolynCollectXors_rec( Gia_Man_t * pGia, int iObj, Vec_Int_t * vXors )
{
Gia_Obj_t * pObj = Gia_ManObj( pGia, iObj );
if ( Gia_ObjIsTravIdCurrent(pGia, pObj) )
return;
Gia_ObjSetTravIdCurrent(pGia, pObj);
if ( !Gia_ObjIsAnd(pObj) || !Gia_ObjIsXor(pObj) )
return;
Vec_IntPush( vXors, iObj );
Gia_PolynCollectXors_rec( pGia, Gia_ObjFaninId0(pObj, iObj), vXors );
Gia_PolynCollectXors_rec( pGia, Gia_ObjFaninId1(pObj, iObj), vXors );
}
void Gia_PolynAnalyzeXors( Gia_Man_t * pGia, int fVerbose )
{
int i, iDriver, Count = 0;
Vec_Int_t * vXors = Vec_IntAlloc( 100 );
if ( pGia->pMuxes == NULL )
{
printf( "AIG does not have XORs extracted.\n" );
return;
}
assert( pGia->pMuxes );
Gia_ManForEachCoDriverId( pGia, iDriver, i )
{
Vec_IntClear( vXors );
Gia_ManIncrementTravId( pGia );
Gia_PolynCollectXors_rec( pGia, iDriver, vXors );
//printf( "%3d : ", i );
//Vec_IntPrint( vXors );
printf( "%d=%d ", i, Vec_IntSize(vXors) );
Count += Vec_IntSize(vXors);
}
printf( "Total = %d.\n", Count );
Vec_IntFree( vXors );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END
src/proof/acec/module.make 0 → 100644
SRC += src/proof/acec/acecCore. \
src/proof/acec/acecFadds.c \
src/proof/acec/acecOrder.c \
src/proof/acec/acecPolyn.c \
src/proof/acec/acecUtil.c
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