Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
A
abc
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
abc
Commits
21c7dad7
Commit
21c7dad7
authored
May 24, 2018
by
Alan Mishchenko
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Supporting NMUX and SEL in NDR.
parent
8cb55037
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
88 additions
and
2 deletions
+88
-2
src/aig/miniaig/ndr.h
+55
-0
src/base/wlc/wlc.h
+1
-0
src/base/wlc/wlcCom.c
+1
-1
src/base/wlc/wlcNdr.c
+2
-0
src/base/wlc/wlcWriteVer.c
+29
-1
No files found.
src/aig/miniaig/ndr.h
View file @
21c7dad7
...
...
@@ -951,6 +951,61 @@ static inline void Ndr_ModuleTestFlop()
Ndr_Delete
(
pDesign
);
}
// This testing procedure creates and writes into a Verilog file
// the following design composed of one selector
// module sel ( input [3:0] c, input [2:0] d0, input [2:0] d1, input [2:0] d2, input [2:0] d3, input [2:0] out );
// wire [2:0] s7 ;
// always @( c or d0 or d1 or d2 or d3 )
// begin
// case ( c )
// 4'b0001 : s7 = d0 ;
// 4'b0010 : s7 = d1 ;
// 4'b0100 : s7 = d2 ;
// 4'b1000 : s7 = d3 ;
// endcase
// end
// assign out = s7 ;
// endmodule
static
inline
void
Ndr_ModuleTestSelSel
()
{
// map name IDs into char strings
char
*
ppNames
[
12
]
=
{
NULL
,
"sel"
,
"c"
,
"d0"
,
"d1"
,
"d2"
,
"d3"
,
"out"
};
// name IDs
int
NameIdC
=
2
;
int
NameIdD0
=
3
;
int
NameIdD1
=
4
;
int
NameIdD2
=
5
;
int
NameIdD3
=
6
;
int
NameIdOut
=
7
;
// array of fanins of node s
int
Fanins
[
8
]
=
{
NameIdC
,
NameIdD0
,
NameIdD1
,
NameIdD2
,
NameIdD3
};
// create a new module
void
*
pDesign
=
Ndr_Create
(
1
);
int
ModuleID
=
Ndr_AddModule
(
pDesign
,
1
);
// add objects to the modele
Ndr_AddObject
(
pDesign
,
ModuleID
,
ABC_OPER_CI
,
0
,
3
,
0
,
0
,
0
,
NULL
,
1
,
&
NameIdC
,
NULL
);
Ndr_AddObject
(
pDesign
,
ModuleID
,
ABC_OPER_CI
,
0
,
2
,
0
,
0
,
0
,
NULL
,
1
,
&
NameIdD0
,
NULL
);
Ndr_AddObject
(
pDesign
,
ModuleID
,
ABC_OPER_CI
,
0
,
2
,
0
,
0
,
0
,
NULL
,
1
,
&
NameIdD1
,
NULL
);
Ndr_AddObject
(
pDesign
,
ModuleID
,
ABC_OPER_CI
,
0
,
2
,
0
,
0
,
0
,
NULL
,
1
,
&
NameIdD2
,
NULL
);
Ndr_AddObject
(
pDesign
,
ModuleID
,
ABC_OPER_CI
,
0
,
2
,
0
,
0
,
0
,
NULL
,
1
,
&
NameIdD3
,
NULL
);
Ndr_AddObject
(
pDesign
,
ModuleID
,
ABC_OPER_SEL_SEL
,
0
,
2
,
0
,
0
,
5
,
Fanins
,
1
,
&
NameIdOut
,
NULL
);
Ndr_AddObject
(
pDesign
,
ModuleID
,
ABC_OPER_CO
,
0
,
2
,
0
,
0
,
1
,
&
NameIdOut
,
0
,
NULL
,
NULL
);
// write Verilog for verification
//Ndr_WriteVerilog( NULL, pDesign, ppNames );
Ndr_Write
(
"sel.ndr"
,
pDesign
);
Ndr_Delete
(
pDesign
);
}
ABC_NAMESPACE_HEADER_END
#endif
...
...
src/base/wlc/wlc.h
View file @
21c7dad7
...
...
@@ -99,6 +99,7 @@ typedef enum {
WLC_OBJ_READ
,
// 54: read port
WLC_OBJ_WRITE
,
// 55: write port
WLC_OBJ_ARI_ADDSUB
,
// 56: adder-subtractor
WLC_OBJ_SEL
,
// 57: positionally encoded selector
WLC_OBJ_NUMBER
// 57: unused
}
Wlc_ObjType_t
;
// when adding new types, remember to update table Wlc_Names in "wlcNtk.c"
...
...
src/base/wlc/wlcCom.c
View file @
21c7dad7
...
...
@@ -1672,7 +1672,7 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
//Wlc_NtkSimulateTest( (Wlc_Ntk_t *)pAbc->pAbcWlc );
//pNtk = Wlc_NtkDupSingleNodes( pNtk );
//Wlc_AbcUpdateNtk( pAbc, pNtk );
Ndr_ModuleTest
Memory
();
Ndr_ModuleTest
SelSel
();
//pNtk = Wlc_NtkMemAbstractTest( pNtk );
//Wlc_AbcUpdateNtk( pAbc, pNtk );
return
0
;
...
...
src/base/wlc/wlcNdr.c
View file @
21c7dad7
...
...
@@ -70,6 +70,7 @@ int Ndr_TypeNdr2Wlc( int Type )
if
(
Type
==
ABC_OPER_LOGIC_OR
)
return
WLC_OBJ_LOGIC_OR
;
// 29: logic OR
if
(
Type
==
ABC_OPER_LOGIC_XOR
)
return
WLC_OBJ_LOGIC_XOR
;
// 30: logic XOR
if
(
Type
==
ABC_OPER_SEL_NMUX
)
return
WLC_OBJ_MUX
;
// 08: multiplexer
if
(
Type
==
ABC_OPER_SEL_SEL
)
return
WLC_OBJ_SEL
;
// 57: selector
if
(
Type
==
ABC_OPER_COMP_EQU
)
return
WLC_OBJ_COMP_EQU
;
// 31: compare equal
if
(
Type
==
ABC_OPER_COMP_NOTEQU
)
return
WLC_OBJ_COMP_NOTEQU
;
// 32: compare not equal
if
(
Type
==
ABC_OPER_COMP_LESS
)
return
WLC_OBJ_COMP_LESS
;
// 33: compare less
...
...
@@ -127,6 +128,7 @@ int Ndr_TypeWlc2Ndr( int Type )
if
(
Type
==
WLC_OBJ_LOGIC_AND
)
return
ABC_OPER_LOGIC_AND
;
// 28: logic AND
if
(
Type
==
WLC_OBJ_LOGIC_OR
)
return
ABC_OPER_LOGIC_OR
;
// 29: logic OR
if
(
Type
==
WLC_OBJ_LOGIC_XOR
)
return
ABC_OPER_LOGIC_XOR
;
// 30: logic XOR
if
(
Type
==
WLC_OBJ_SEL
)
return
ABC_OPER_SEL_SEL
;
// 57: selector
if
(
Type
==
WLC_OBJ_COMP_EQU
)
return
ABC_OPER_COMP_EQU
;
// 31: compare equal
if
(
Type
==
WLC_OBJ_COMP_NOTEQU
)
return
ABC_OPER_COMP_NOTEQU
;
// 32: compare not equal
if
(
Type
==
WLC_OBJ_COMP_LESS
)
return
ABC_OPER_COMP_LESS
;
// 33: compare less
...
...
src/base/wlc/wlcWriteVer.c
View file @
21c7dad7
...
...
@@ -147,7 +147,7 @@ void Wlc_WriteVerIntVec( FILE * pFile, Wlc_Ntk_t * p, Vec_Int_t * vVec, int Star
void
Wlc_WriteVerInt
(
FILE
*
pFile
,
Wlc_Ntk_t
*
p
,
int
fNoFlops
)
{
Wlc_Obj_t
*
pObj
;
int
i
,
k
,
iFanin
;
int
i
,
k
,
j
,
iFanin
;
char
Range
[
100
];
fprintf
(
pFile
,
"module %s ( "
,
p
->
pName
);
fprintf
(
pFile
,
"
\n
"
);
...
...
@@ -253,6 +253,34 @@ void Wlc_WriteVerInt( FILE * pFile, Wlc_Ntk_t * p, int fNoFlops )
fprintf
(
pFile
,
"end
\n
"
);
continue
;
}
else
if
(
pObj
->
Type
==
WLC_OBJ_SEL
)
{
fprintf
(
pFile
,
"%s ;
\n
"
,
Wlc_ObjName
(
p
,
i
)
);
fprintf
(
pFile
,
" "
);
fprintf
(
pFile
,
"always @( "
);
Wlc_ObjForEachFanin
(
pObj
,
iFanin
,
k
)
fprintf
(
pFile
,
"%s%s"
,
k
?
" or "
:
""
,
Wlc_ObjName
(
p
,
Wlc_ObjFaninId
(
pObj
,
k
))
);
fprintf
(
pFile
,
" )
\n
"
);
fprintf
(
pFile
,
" "
);
fprintf
(
pFile
,
"begin
\n
"
);
fprintf
(
pFile
,
" "
);
fprintf
(
pFile
,
"case ( %s )
\n
"
,
Wlc_ObjName
(
p
,
Wlc_ObjFaninId
(
pObj
,
0
))
);
Wlc_ObjForEachFanin
(
pObj
,
iFanin
,
k
)
{
if
(
!
k
)
continue
;
fprintf
(
pFile
,
" "
);
fprintf
(
pFile
,
"%d
\'
b"
,
Wlc_ObjFaninNum
(
pObj
)
-
1
);
for
(
j
=
Wlc_ObjFaninNum
(
pObj
)
-
1
;
j
>
0
;
j
--
)
fprintf
(
pFile
,
"%d"
,
(
int
)(
j
==
k
)
);
fprintf
(
pFile
,
" : %s = "
,
Wlc_ObjName
(
p
,
i
)
);
fprintf
(
pFile
,
"%s ;
\n
"
,
Wlc_ObjName
(
p
,
Wlc_ObjFaninId
(
pObj
,
k
))
);
}
fprintf
(
pFile
,
" "
);
fprintf
(
pFile
,
"endcase
\n
"
);
fprintf
(
pFile
,
" "
);
fprintf
(
pFile
,
"end
\n
"
);
continue
;
}
else
if
(
pObj
->
Type
==
WLC_OBJ_READ
||
pObj
->
Type
==
WLC_OBJ_WRITE
)
{
if
(
p
->
fMemPorts
)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment