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lvzhengyang
abc
Commits
16cf6bf1
Commit
16cf6bf1
authored
Mar 26, 2012
by
Alan Mishchenko
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Plain Diff
Logic sharing for multi-input gates.
parent
45f07795
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2 changed files
with
204 additions
and
12 deletions
+204
-12
src/base/abci/abcExtract.c
+10
-5
src/opt/dar/darBalance.c
+194
-7
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src/base/abci/abcExtract.c
View file @
16cf6bf1
...
...
@@ -315,17 +315,19 @@ void Abc_NtkTraverseSupers( Abc_ShaMan_t * p, int fAnd )
int
i
,
nOnesMax
;
// create mapping of nodes into their column vectors
vInputs
=
Vec_PtrStart
(
Abc_NtkObjNumMax
(
p
->
pNtk
)
);
vInputs
=
Vec_PtrStart
(
Abc_NtkObjNumMax
(
p
->
pNtk
)
*
(
1
+
fAnd
)
);
Abc_NtkIncrementTravId
(
p
->
pNtk
);
if
(
fAnd
)
{
Abc_NtkForEachCo
(
p
->
pNtk
,
pObj
,
i
)
Abc_NtkTraverseSupersAnd_rec
(
p
,
Abc_ObjFanin0
(
pObj
),
vInputs
);
if
(
Abc_ObjIsNode
(
Abc_ObjFanin0
(
pObj
))
)
Abc_NtkTraverseSupersAnd_rec
(
p
,
Abc_ObjFanin0
(
pObj
),
vInputs
);
}
else
{
Abc_NtkForEachCo
(
p
->
pNtk
,
pObj
,
i
)
Abc_NtkTraverseSupersXor_rec
(
p
,
Abc_ObjFanin0
(
pObj
),
vInputs
);
if
(
Abc_ObjIsNode
(
Abc_ObjFanin0
(
pObj
))
)
Abc_NtkTraverseSupersXor_rec
(
p
,
Abc_ObjFanin0
(
pObj
),
vInputs
);
}
p
->
nStartCols
=
Vec_IntSize
(
p
->
vObj2Lit
);
...
...
@@ -646,7 +648,10 @@ Abc_Ntk_t * Abc_NtkUpdateNetwork( Abc_ShaMan_t * p, int fAnd )
// create map of originals
vMap2Repl
=
Vec_IntStartFull
(
Abc_NtkObjNumMax
(
p
->
pNtk
)
);
Vec_PtrForEachEntry
(
Abc_Obj_t
*
,
vOrig
,
pObj
,
i
)
{
// printf( "Replacing %d by %d.\n", Abc_ObjId(pObj), Abc_ObjToLit((Abc_Obj_t *)Vec_PtrEntry(vRepl, i)) );
Vec_IntWriteEntry
(
vMap2Repl
,
Abc_ObjId
(
pObj
),
Abc_ObjToLit
((
Abc_Obj_t
*
)
Vec_PtrEntry
(
vRepl
,
i
))
);
}
Vec_PtrFree
(
vOrig
);
Vec_PtrFree
(
vRepl
);
...
...
@@ -660,7 +665,7 @@ Abc_Ntk_t * Abc_NtkUpdateNetwork( Abc_ShaMan_t * p, int fAnd )
{
if
(
iLit
==
iLitConst1
&&
fAnd
)
{
pObj
->
fCompl0
=
1
;
pObj
->
fCompl0
^
=
1
;
Vec_IntWriteEntry
(
&
pObj
->
vFanins
,
0
,
Abc_Lit2Var
(
iLitConst1
)
);
}
else
...
...
@@ -677,7 +682,7 @@ Abc_Ntk_t * Abc_NtkUpdateNetwork( Abc_ShaMan_t * p, int fAnd )
{
if
(
iLit
==
iLitConst1
&&
fAnd
)
{
pObj
->
fCompl1
=
1
;
pObj
->
fCompl1
^
=
1
;
Vec_IntWriteEntry
(
&
pObj
->
vFanins
,
1
,
Abc_Lit2Var
(
iLitConst1
)
);
}
else
...
...
src/opt/dar/darBalance.c
View file @
16cf6bf1
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