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abc
Commit 1229d1ff by Alan Mishchenko
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New options to print out sim info.

parent a5f48414
Showing with 71 additions and 12 deletions
src/base/abci/abc.c
...@@ -33969,11 +33969,11 @@ usage: ...@@ -33969,11 +33969,11 @@ usage:
***********************************************************************/ ***********************************************************************/
int Abc_CommandAbc9WriteSim( Abc_Frame_t * pAbc, int argc, char ** argv ) int Abc_CommandAbc9WriteSim( Abc_Frame_t * pAbc, int argc, char ** argv )
{ {
int c, fOutputs = 0, fTrans = 0, fVerbose = 0; int c, fOutputs = 0, fTrans = 0, fBool = 0, fVerbose = 0;
char ** pArgvNew; char ** pArgvNew;
int nArgcNew; int nArgcNew;
Extra_UtilGetoptReset(); Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "otvh" ) ) != EOF ) while ( ( c = Extra_UtilGetopt( argc, argv, "otbvh" ) ) != EOF )
{ {
switch ( c ) switch ( c )
{ {
...@@ -33983,6 +33983,9 @@ int Abc_CommandAbc9WriteSim( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -33983,6 +33983,9 @@ int Abc_CommandAbc9WriteSim( Abc_Frame_t * pAbc, int argc, char ** argv )
case 't': case 't':
fTrans ^= 1; fTrans ^= 1;
break; break;
case 'b':
fBool ^= 1;
break;
case 'v': case 'v':
fVerbose ^= 1; fVerbose ^= 1;
break; break;
...@@ -34017,46 +34020,63 @@ int Abc_CommandAbc9WriteSim( Abc_Frame_t * pAbc, int argc, char ** argv ) ...@@ -34017,46 +34020,63 @@ int Abc_CommandAbc9WriteSim( Abc_Frame_t * pAbc, int argc, char ** argv )
if ( fOutputs ) if ( fOutputs )
{ {
Vec_Wrd_t * vTemp; Vec_Wrd_t * vTemp;
int nWords = Vec_WrdSize(pAbc->pGia->vSimsPo) / Gia_ManCoNum(pAbc->pGia);
assert( Vec_WrdSize(pAbc->pGia->vSimsPo) % Gia_ManCoNum(pAbc->pGia) == 0 ); assert( Vec_WrdSize(pAbc->pGia->vSimsPo) % Gia_ManCoNum(pAbc->pGia) == 0 );
if ( fTrans ) if ( fTrans )
{ {
int nSize = Vec_WrdSize(pAbc->pGia->vSimsPo); int nSize = Vec_WrdSize(pAbc->pGia->vSimsPo);
int nWords = Vec_WrdSize(pAbc->pGia->vSimsPo) / Gia_ManCoNum(pAbc->pGia);
Vec_WrdFillExtra( pAbc->pGia->vSimsPo, nWords * 64 * ((Gia_ManCoNum(pAbc->pGia) + 63)/64), 0 ); Vec_WrdFillExtra( pAbc->pGia->vSimsPo, nWords * 64 * ((Gia_ManCoNum(pAbc->pGia) + 63)/64), 0 );
vTemp = Vec_WrdStart( Vec_WrdSize(pAbc->pGia->vSimsPo) ); vTemp = Vec_WrdStart( Vec_WrdSize(pAbc->pGia->vSimsPo) );
Extra_BitMatrixTransposeP( pAbc->pGia->vSimsPo, nWords, vTemp, (Gia_ManCoNum(pAbc->pGia) + 63)/64 ); Extra_BitMatrixTransposeP( pAbc->pGia->vSimsPo, nWords, vTemp, (Gia_ManCoNum(pAbc->pGia) + 63)/64 );
Vec_WrdDumpHex( pArgvNew[0], vTemp, (Gia_ManCoNum(pAbc->pGia) + 63)/64, 1 ); if ( fBool )
Vec_WrdDumpBool( pArgvNew[0], vTemp, (Gia_ManCoNum(pAbc->pGia) + 63)/64, Gia_ManCoNum(pAbc->pGia), 1, 1 );
else
Vec_WrdDumpHex( pArgvNew[0], vTemp, (Gia_ManCoNum(pAbc->pGia) + 63)/64, 1 );
Vec_WrdShrink( pAbc->pGia->vSimsPo, nSize ); Vec_WrdShrink( pAbc->pGia->vSimsPo, nSize );
Vec_WrdFree( vTemp ); Vec_WrdFree( vTemp );
} }
else else
Vec_WrdDumpHex( pArgvNew[0], pAbc->pGia->vSimsPo, Vec_WrdSize(pAbc->pGia->vSimsPo) / Gia_ManCoNum(pAbc->pGia), 1 ); {
if ( fBool )
Vec_WrdDumpBool( pArgvNew[0], pAbc->pGia->vSimsPo, nWords, Gia_ManCoNum(pAbc->pGia), 1, 1 );
else
Vec_WrdDumpHex( pArgvNew[0], pAbc->pGia->vSimsPo, nWords, 1 );
}
} }
else else
{ {
Vec_Wrd_t * vTemp; Vec_Wrd_t * vTemp;
int nWords = Vec_WrdSize(pAbc->pGia->vSimsPi) / Gia_ManCiNum(pAbc->pGia);
assert( Vec_WrdSize(pAbc->pGia->vSimsPi) % Gia_ManCiNum(pAbc->pGia) == 0 ); assert( Vec_WrdSize(pAbc->pGia->vSimsPi) % Gia_ManCiNum(pAbc->pGia) == 0 );
if ( fTrans ) if ( fTrans )
{ {
int nSize = Vec_WrdSize(pAbc->pGia->vSimsPi); int nSize = Vec_WrdSize(pAbc->pGia->vSimsPi);
int nWords = Vec_WrdSize(pAbc->pGia->vSimsPi) / Gia_ManCiNum(pAbc->pGia);
Vec_WrdFillExtra( pAbc->pGia->vSimsPi, nWords * 64 * ((Gia_ManCiNum(pAbc->pGia) + 63)/64), 0 ); Vec_WrdFillExtra( pAbc->pGia->vSimsPi, nWords * 64 * ((Gia_ManCiNum(pAbc->pGia) + 63)/64), 0 );
vTemp = Vec_WrdStart( Vec_WrdSize(pAbc->pGia->vSimsPi) ); vTemp = Vec_WrdStart( Vec_WrdSize(pAbc->pGia->vSimsPi) );
Extra_BitMatrixTransposeP( pAbc->pGia->vSimsPi, nWords, vTemp, (Gia_ManCiNum(pAbc->pGia) + 63)/64 ); Extra_BitMatrixTransposeP( pAbc->pGia->vSimsPi, nWords, vTemp, (Gia_ManCiNum(pAbc->pGia) + 63)/64 );
Vec_WrdDumpHex( pArgvNew[0], vTemp, (Gia_ManCiNum(pAbc->pGia) + 63)/64, 1 ); if ( fBool )
Vec_WrdDumpBool( pArgvNew[0], vTemp, (Gia_ManCiNum(pAbc->pGia) + 63)/64, Gia_ManCiNum(pAbc->pGia), 1, 1 );
else
Vec_WrdDumpHex( pArgvNew[0], vTemp, (Gia_ManCiNum(pAbc->pGia) + 63)/64, 1 );
Vec_WrdShrink( pAbc->pGia->vSimsPi, nSize ); Vec_WrdShrink( pAbc->pGia->vSimsPi, nSize );
Vec_WrdFree( vTemp ); Vec_WrdFree( vTemp );
} }
else else
Vec_WrdDumpHex( pArgvNew[0], pAbc->pGia->vSimsPi, Vec_WrdSize(pAbc->pGia->vSimsPi) / Gia_ManCiNum(pAbc->pGia), 1 ); {
if ( fBool )
Vec_WrdDumpBool( pArgvNew[0], pAbc->pGia->vSimsPi, nWords, Gia_ManCiNum(pAbc->pGia), 1, 1 );
else
Vec_WrdDumpHex( pArgvNew[0], pAbc->pGia->vSimsPi, nWords, 1 );
}
} }
return 0; return 0;
usage: usage:
Abc_Print( -2, "usage: &sim_write [-otvh] <file>\n" ); Abc_Print( -2, "usage: &sim_write [-otbvh] <file>\n" );
Abc_Print( -2, "\t writes simulation patterns into a file\n" ); Abc_Print( -2, "\t writes simulation patterns into a file\n" );
Abc_Print( -2, "\t-o : toggle writing output information [default = %s]\n", fOutputs? "yes": "no" ); Abc_Print( -2, "\t-o : toggle writing output information [default = %s]\n", fOutputs? "yes": "no" );
Abc_Print( -2, "\t-t : toggle transposing the simulation information [default = %s]\n", fTrans? "yes": "no" ); Abc_Print( -2, "\t-t : toggle transposing the simulation information [default = %s]\n", fTrans? "yes": "no" );
Abc_Print( -2, "\t-b : toggle dumping in boolean vs hexadecimal notation [default = %s]\n", fBool? "yes": "no" );
Abc_Print( -2, "\t-v : toggle printing verbose information [default = %s]\n", fVerbose? "yes": "no" ); Abc_Print( -2, "\t-v : toggle printing verbose information [default = %s]\n", fVerbose? "yes": "no" );
Abc_Print( -2, "\t-h : print the command usage\n"); Abc_Print( -2, "\t-h : print the command usage\n");
Abc_Print( -2, "\t<file> : file to store the simulation info\n"); Abc_Print( -2, "\t<file> : file to store the simulation info\n");
src/misc/vec/vecWrd.h
...@@ -1284,7 +1284,46 @@ static inline void Vec_WrdAppend( Vec_Wrd_t * vVec1, Vec_Wrd_t * vVec2 ) ...@@ -1284,7 +1284,46 @@ static inline void Vec_WrdAppend( Vec_Wrd_t * vVec1, Vec_Wrd_t * vVec2 )
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
static inline void Gia_ManSimPatWriteOne( FILE * pFile, word * pSim, int nWords ) static inline void Vec_WrdDumpBoolOne( FILE * pFile, word * pSim, int nBits, int fReverse )
{
int k;
if ( fReverse )
for ( k = nBits-1; k >= 0; k-- )
fprintf( pFile, "%d", (pSim[k/64] >> (k%64)) & 1 );
else
for ( k = 0; k < nBits; k++ )
fprintf( pFile, "%d", (pSim[k/64] >> (k%64)) & 1 );
fprintf( pFile, "\n" );
}
static inline void Vec_WrdDumpBool( char * pFileName, Vec_Wrd_t * p, int nWords, int nBits, int fReverse, int fVerbose )
{
int i, nNodes = Vec_WrdSize(p) / nWords;
FILE * pFile = fopen( pFileName, "wb" );
if ( pFile == NULL )
{
printf( "Cannot open file \"%s\" for writing.\n", pFileName );
return;
}
assert( Vec_WrdSize(p) % nWords == 0 );
for ( i = 0; i < nNodes; i++ )
Vec_WrdDumpBoolOne( pFile, Vec_WrdEntryP(p, i*nWords), nBits, fReverse );
fclose( pFile );
if ( fVerbose )
printf( "Written %d bits of simulation data for %d objects into file \"%s\".\n", nBits, Vec_WrdSize(p)/nWords, pFileName );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Vec_WrdDumpHexOne( FILE * pFile, word * pSim, int nWords )
{ {
int k, Digit, nDigits = nWords*16; int k, Digit, nDigits = nWords*16;
for ( k = 0; k < nDigits; k++ ) for ( k = 0; k < nDigits; k++ )
...@@ -1302,7 +1341,7 @@ static inline void Vec_WrdPrintHex( Vec_Wrd_t * p, int nWords ) ...@@ -1302,7 +1341,7 @@ static inline void Vec_WrdPrintHex( Vec_Wrd_t * p, int nWords )
int i, nNodes = Vec_WrdSize(p) / nWords; int i, nNodes = Vec_WrdSize(p) / nWords;
assert( Vec_WrdSize(p) % nWords == 0 ); assert( Vec_WrdSize(p) % nWords == 0 );
for ( i = 0; i < nNodes; i++ ) for ( i = 0; i < nNodes; i++ )
Gia_ManSimPatWriteOne( stdout, Vec_WrdEntryP(p, i*nWords), nWords ); Vec_WrdDumpHexOne( stdout, Vec_WrdEntryP(p, i*nWords), nWords );
} }
static inline void Vec_WrdDumpHex( char * pFileName, Vec_Wrd_t * p, int nWords, int fVerbose ) static inline void Vec_WrdDumpHex( char * pFileName, Vec_Wrd_t * p, int nWords, int fVerbose )
{ {
...@@ -1315,7 +1354,7 @@ static inline void Vec_WrdDumpHex( char * pFileName, Vec_Wrd_t * p, int nWords, ...@@ -1315,7 +1354,7 @@ static inline void Vec_WrdDumpHex( char * pFileName, Vec_Wrd_t * p, int nWords,
} }
assert( Vec_WrdSize(p) % nWords == 0 ); assert( Vec_WrdSize(p) % nWords == 0 );
for ( i = 0; i < nNodes; i++ ) for ( i = 0; i < nNodes; i++ )
Gia_ManSimPatWriteOne( pFile, Vec_WrdEntryP(p, i*nWords), nWords ); Vec_WrdDumpHexOne( pFile, Vec_WrdEntryP(p, i*nWords), nWords );
fclose( pFile ); fclose( pFile );
if ( fVerbose ) if ( fVerbose )
printf( "Written %d words of simulation data for %d objects into file \"%s\".\n", nWords, Vec_WrdSize(p)/nWords, pFileName ); printf( "Written %d words of simulation data for %d objects into file \"%s\".\n", nWords, Vec_WrdSize(p)/nWords, pFileName );
......
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