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Commit 10c90de0 by Alan Mishchenko
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New technology mapper.

parent d22da3ae
Showing with 408 additions and 36 deletions
abclib.dsp
......@@ -2507,6 +2507,10 @@ SOURCE=.\src\map\mpm\mpmDsd.c
# End Source File
# Begin Source File
SOURCE=.\src\map\mpm\mpmGates.c
# End Source File
# Begin Source File
SOURCE=.\src\map\mpm\mpmInt.h
# End Source File
# Begin Source File
......
src/base/abci/abc.c
......@@ -29528,15 +29528,17 @@ usage:
***********************************************************************/
int Abc_CommandAbc9If2( Abc_Frame_t * pAbc, int argc, char ** argv )
{
extern Gia_Man_t * Mpm_ManMappingTest( Gia_Man_t * p, Mpm_Par_t * pPars );
extern Abc_Ntk_t * Mpm_ManCellMapping( Gia_Man_t * p, Mpm_Par_t * pPars, void * pMio );
extern Gia_Man_t * Mpm_ManLutMapping( Gia_Man_t * p, Mpm_Par_t * pPars );
char Buffer[200];
Abc_Ntk_t * pTemp;
Gia_Man_t * pNew;
Mpm_Par_t Pars, * pPars = &Pars;
int c, nLutSize = 6;
// set defaults
Mpm_ManSetParsDefault( pPars );
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "KCDtmzrcuvwh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "KCDtmzrcuxvwh" ) ) != EOF )
{
switch ( c )
{
......@@ -29596,6 +29598,9 @@ int Abc_CommandAbc9If2( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'u':
pPars->fMap4Aig ^= 1;
break;
case 'x':
pPars->fMap4Gates ^= 1;
break;
case 'v':
pPars->fVerbose ^= 1;
break;
......@@ -29612,17 +29617,48 @@ int Abc_CommandAbc9If2( Abc_Frame_t * pAbc, int argc, char ** argv )
if ( pPars->fMap4Cnf )
pPars->fUseDsd = 1;
if ( pPars->fCutMin )
pPars->fUseTruth = 1;
// pPars->fUseDsd = 1;
pPars->fUseDsd = 1;
// pPars->fUseTruth = 1;
if ( pPars->fMap4Gates )
{
pPars->fUseDsd = 1;
if ( pAbc->pLibScl == NULL )
{
Abc_Print( -1, "There is no SCL library available.\n" );
return 1;
}
pPars->pScl = pAbc->pLibScl;
}
if ( pPars->fUseDsd || pPars->fUseTruth )
pPars->fDeriveLuts = 1;
// perform mapping
pNew = Mpm_ManMappingTest( pAbc->pGia, pPars );
Mpm_LibLutFree( pPars->pLib );
if ( pNew == NULL )
if ( pPars->fMap4Gates )
{
Abc_Print( -1, "Abc_CommandAbc9If2(): Mapping of GIA has failed.\n" );
return 1;
if ( Abc_FrameReadLibGen() == NULL )
{
Abc_Print( -1, "There is no GENLIB library available.\n" );
return 1;
}
pTemp = Mpm_ManCellMapping( pAbc->pGia, pPars, Abc_FrameReadLibGen() );
Mpm_LibLutFree( pPars->pLib );
if ( pTemp == NULL )
{
Abc_Print( -1, "Abc_CommandAbc9If2(): Mapping into standard cells has failed.\n" );
return 1;
}
Abc_FrameReplaceCurrentNetwork( pAbc, pTemp );
}
else
{
pNew = Mpm_ManLutMapping( pAbc->pGia, pPars );
Mpm_LibLutFree( pPars->pLib );
if ( pNew == NULL )
{
Abc_Print( -1, "Abc_CommandAbc9If2(): Mapping into LUTs has failed.\n" );
return 1;
}
Abc_FrameUpdateGia( pAbc, pNew );
}
Abc_FrameUpdateGia( pAbc, pNew );
return 0;
usage:
......@@ -29630,7 +29666,7 @@ usage:
sprintf(Buffer, "best possible" );
else
sprintf(Buffer, "%d", pPars->DelayTarget );
Abc_Print( -2, "usage: &if2 [-KCD num] [-tmzrcuvwh]\n" );
Abc_Print( -2, "usage: &if2 [-KCD num] [-tmzrcuxvwh]\n" );
Abc_Print( -2, "\t performs technology mapping of the network\n" );
Abc_Print( -2, "\t-K num : sets the LUT size for the mapping [default = %d]\n", nLutSize );
Abc_Print( -2, "\t-C num : the max number of priority cuts (0 < num < 2^12) [default = %d]\n", pPars->nNumCuts );
......@@ -29641,6 +29677,7 @@ usage:
Abc_Print( -2, "\t-r : toggles using one round of mapping [default = %s]\n", pPars->fOneRound? "yes": "no" );
Abc_Print( -2, "\t-c : toggles mapping for CNF computation [default = %s]\n", pPars->fMap4Cnf? "yes": "no" );
Abc_Print( -2, "\t-u : toggles mapping for AIG computation [default = %s]\n", pPars->fMap4Aig? "yes": "no" );
Abc_Print( -2, "\t-x : toggles mapping for standard cells [default = %s]\n", pPars->fMap4Gates? "yes": "no" );
Abc_Print( -2, "\t-v : toggles verbose output [default = %s]\n", pPars->fVerbose? "yes": "no" );
Abc_Print( -2, "\t-w : toggles very verbose output [default = %s]\n", pPars->fVeryVerbose? "yes": "no" );
Abc_Print( -2, "\t-h : prints the command usage\n");
src/map/mpm/module.make
SRC += src/map/mpm/mpmAbc.c \
src/map/mpm/mpmCore.c \
src/map/mpm/mpmDsd.c \
src/map/mpm/mpmGates.c \
src/map/mpm/mpmLib.c \
src/map/mpm/mpmMan.c \
src/map/mpm/mpmMap.c \
......
src/map/mpm/mpm.h
......@@ -57,6 +57,7 @@ typedef struct Mpm_Par_t_ Mpm_Par_t;
struct Mpm_Par_t_
{
Mpm_LibLut_t * pLib;
void * pScl;
int nNumCuts;
int DelayTarget;
int fUseGates;
......@@ -67,6 +68,7 @@ struct Mpm_Par_t_
int fDeriveLuts;
int fMap4Cnf;
int fMap4Aig;
int fMap4Gates;
int fVerbose;
int fVeryVerbose;
};
......
src/map/mpm/mpmCore.c
......@@ -56,6 +56,7 @@ void Mpm_ManSetParsDefault( Mpm_Par_t * p )
p->fDeriveLuts = 0; // use truth tables to derive AIG structure
p->fMap4Cnf = 0; // mapping for CNF
p->fMap4Aig = 0; // mapping for AIG
p->fMap4Gates = 0; // mapping for gates
p->fVerbose = 0; // verbose output
p->fVeryVerbose = 0; // verbose output
}
......@@ -71,13 +72,15 @@ void Mpm_ManSetParsDefault( Mpm_Par_t * p )
SeeAlso []
***********************************************************************/
Gia_Man_t * Mpm_ManPerformTest( Mig_Man_t * pMig, Mpm_Par_t * pPars )
Gia_Man_t * Mpm_ManPerformLutMapping( Mig_Man_t * pMig, Mpm_Par_t * pPars )
{
Gia_Man_t * pNew;
Mpm_Man_t * p;
p = Mpm_ManStart( pMig, pPars );
if ( p->pPars->fVerbose )
Mpm_ManPrintStatsInit( p );
// if ( p->pPars->fMap4Gates )
// p->vGateNpnConfig = Mpm_ManFindDsdMatches( p, p->pPars->pScl, &p->vNpnCosts );
Mpm_ManPrepare( p );
Mpm_ManPerform( p );
if ( p->pPars->fVerbose )
......@@ -86,7 +89,7 @@ Gia_Man_t * Mpm_ManPerformTest( Mig_Man_t * pMig, Mpm_Par_t * pPars )
Mpm_ManStop( p );
return pNew;
}
Gia_Man_t * Mpm_ManMappingTest( Gia_Man_t * pGia, Mpm_Par_t * pPars )
Gia_Man_t * Mpm_ManLutMapping( Gia_Man_t * pGia, Mpm_Par_t * pPars )
{
Mig_Man_t * p;
Gia_Man_t * pNew;
......@@ -100,7 +103,7 @@ Gia_Man_t * Mpm_ManMappingTest( Gia_Man_t * pGia, Mpm_Par_t * pPars )
}
else
p = Mig_ManCreate( pGia );
pNew = Mpm_ManPerformTest( p, pPars );
pNew = Mpm_ManPerformLutMapping( p, pPars );
Mig_ManStop( p );
return pNew;
}
......
src/map/mpm/mpmDsd.c
......@@ -643,7 +643,6 @@ static Mpm_Dsd_t s_DsdClass6[595] = {
void Mpm_ManPrintDsdStats( Mpm_Man_t * p )
{
int i, Absent = 0;
for ( i = 0; i < 595; i++ )
{
if ( p->nCountDsd[i] == 0 )
......@@ -659,9 +658,9 @@ void Mpm_ManPrintDsdStats( Mpm_Man_t * p )
printf( "\n" );
}
}
printf( "Unused classes = %d (%.2f %%). Non-DSD cuts = %d (%.2f %%).\n",
Absent, 100.0 * Absent / 595,
p->nNonDsd, 100.0 * p->nNonDsd / p->nCutsMergedAll );
printf( "Unused classes = %d (%.2f %%). ", Absent, 100.0 * Absent / 595 );
printf( "Non-DSD cuts = %d (%.2f %%). ", p->nNonDsd, 100.0 * p->nNonDsd / p->nCutsMergedAll );
printf( "No-match cuts = %d (%.2f %%).\n", p->nNoMatch, 100.0 * p->nNoMatch / p->nCutsMergedAll );
}
/**Function*************************************************************
......@@ -872,6 +871,31 @@ word Mpm_CutTruthFromDsd( Mpm_Man_t * pMan, Mpm_Cut_t * pCut, int iClass )
/**Function*************************************************************
Synopsis [Checks hash table for DSD class.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Mpm_CutCheckDsd6( Mpm_Man_t * p, word t )
{
int fCompl, Entry, Config;
if ( (fCompl = (t & 1)) )
t = ~t;
Entry = *Hsh_IntManLookup( p->pHash, (unsigned *)&t );
if ( Entry == -1 )
return -1;
Config = Vec_IntEntry( p->vConfgRes, Entry );
if ( fCompl )
Config ^= (1 << 16);
return Config;
}
/**Function*************************************************************
Synopsis []
Description []
......@@ -884,7 +908,7 @@ word Mpm_CutTruthFromDsd( Mpm_Man_t * pMan, Mpm_Cut_t * pCut, int iClass )
int Mpm_CutComputeDsd6( Mpm_Man_t * p, Mpm_Cut_t * pCut, Mpm_Cut_t * pCut0, Mpm_Cut_t * pCut1, Mpm_Cut_t * pCutC, int fCompl0, int fCompl1, int fComplC, int Type )
{
int fVerbose = 0;
int i, Config, iClass, Entry, fCompl = 0;
int i, Config, iClass, fCompl;
int pLeavesNew[6] = { -1, -1, -1, -1, -1, -1 };
word t = 0;
if ( pCutC == NULL )
......@@ -946,23 +970,31 @@ Kit_DsdPrintFromTruth( (unsigned *)&t, 6 ); printf( "\n" );
t = (tC & t1) | (~tC & t0);
}
if ( t & 1 )
{
fCompl = 1; t = ~t;
}
Entry = *Hsh_IntManLookup( p->pHash, (unsigned *)&t );
if ( Entry == -1 )
// find configuration
Config = Mpm_CutCheckDsd6( p, t );
if ( Config == -1 )
{
p->nNonDsd++;
return 0;
}
Config = Vec_IntEntry( p->vConfgRes, Entry );
if ( Config & (1 << 16) )
fCompl ^= 1;
// get the class
iClass = Config >> 17;
pCut->iFunc = Abc_Var2Lit( iClass, fCompl );
fCompl = (Config >> 16) & 1;
Config &= 0xFFFF;
assert( (Config >> 6) < 720 );
// check if the gate exists
if ( p->pPars->fMap4Gates )
{
if ( Vec_IntEntry(p->vGateNpnConfig, iClass) < 0 )
{
p->nNoMatch++;
return 0;
}
}
// set the function
pCut->iFunc = Abc_Var2Lit( iClass, fCompl );
if ( fVerbose )
{
......@@ -971,11 +1003,13 @@ Mpm_CutPrint( pCut1 );
Mpm_CutPrint( pCut );
}
// update cut
assert( (Config >> 6) < 720 );
for ( i = 0; i < (int)pCut->nLeaves; i++ )
pLeavesNew[(int)p->Perm6[Config >> 6]] = Abc_LitNotCond( pCut->pLeaves[i], (Config >> i) & 1 );
pLeavesNew[(int)(p->Perm6[Config >> 6][i])] = Abc_LitNotCond( pCut->pLeaves[i], (Config >> i) & 1 );
pCut->nLeaves = p->pDsd6[iClass].nVars;
// for ( i = 0; i < (int)pCut->nLeaves; i++ )
// assert( pLeavesNew[i] != -1 );
for ( i = 0; i < (int)pCut->nLeaves; i++ )
assert( pLeavesNew[i] != -1 );
for ( i = 0; i < (int)pCut->nLeaves; i++ )
pCut->pLeaves[i] = pLeavesNew[i];
p->nCountDsd[iClass]++;
......
src/map/mpm/mpmGates.c 0 → 100644
/**CFile****************************************************************
FileName [mpmGates.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Configurable technology mapper.]
Synopsis [Standard-cell mapping.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 1, 2013.]
Revision [$Id: mpmGates.c,v 1.00 2013/06/01 00:00:00 alanmi Exp $]
***********************************************************************/
#include "mpmInt.h"
#include "misc/st/st.h"
#include "map/mio/mio.h"
#include "map/scl/sclInt.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Finds matches fore each DSD class.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Mpm_ManFindDsdMatches( Mpm_Man_t * p, void * pScl, Vec_Int_t ** pvNpnCosts )
{
int fVerbose = p->pPars->fVeryVerbose;
SC_Lib * pLib = (SC_Lib *)pScl;
Vec_Int_t * vClasses;
SC_Cell * pRepr;
int i, Config, iClass;
word Truth;
vClasses = Vec_IntStartFull( 600 );
*pvNpnCosts = Vec_IntStartFull( 600 );
SC_LibForEachCellClass( pLib, pRepr, i )
{
if ( pRepr->n_inputs > 6 || pRepr->n_outputs > 1 )
{
if ( fVerbose )
printf( "Skipping cell %s with %d inputs and %d outputs\n", pRepr->pName, pRepr->n_inputs, pRepr->n_outputs );
continue;
}
Truth = *Vec_WrdArray( SC_CellPin(pRepr, pRepr->n_inputs)->vFunc );
Config = Mpm_CutCheckDsd6( p, Truth );
if ( Config == -1 )
{
if ( fVerbose )
printf( "Skipping cell %s with non-DSD function\n", pRepr->pName );
continue;
}
iClass = Config >> 17;
Config = (pRepr->Id << 17) | (Config & 0x1FFFF);
// write gate and NPN config for this DSD class
Vec_IntWriteEntry( vClasses, iClass, Config );
Vec_IntWriteEntry( *pvNpnCosts, iClass, (int)(100 * pRepr->area) );
if ( !fVerbose )
continue;
printf( "Gate %5d %-30s : ", pRepr->Id, pRepr->pName );
printf( "Class %3d ", iClass );
printf( "Area %10.3f ", pRepr->area );
Extra_PrintBinary( stdout, &Config, 17 );
printf( " " );
Kit_DsdPrintFromTruth( (unsigned *)&Truth, pRepr->n_inputs ); printf( "\n" );
}
return vClasses;
}
/**Function*************************************************************
Synopsis [Find mapping of DSD classes into Genlib library cells.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Mpm_ManFindCells( Mio_Library_t * pMio, SC_Lib * pScl, Vec_Int_t * vNpnGates )
{
Vec_Ptr_t * vNpnGatesMio;
Mio_Gate_t * pMioGate;
SC_Cell * pCell;
int iCell, iClass;
vNpnGatesMio = Vec_PtrStart( Vec_IntSize(vNpnGates) );
Vec_IntForEachEntry( vNpnGates, iCell, iClass )
{
if ( iCell == -1 )
continue;
pCell = SC_LibCell( pScl, (iCell >> 17) );
pMioGate = Mio_LibraryReadGateByName( pMio, pCell->pName, NULL );
assert( pMioGate != NULL );
Vec_PtrWriteEntry( vNpnGatesMio, iClass, pMioGate );
}
return vNpnGatesMio;
}
/**Function*************************************************************
Synopsis [Derive mapped network as an ABC network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Mpm_ManFindMappedNodes( Mpm_Man_t * p )
{
Vec_Int_t * vNodes;
Mig_Obj_t * pObj;
vNodes = Vec_IntAlloc( 1000 );
Mig_ManForEachObj( p->pMig, pObj )
if ( Mig_ObjIsNode(pObj) && Mpm_ObjMapRef(p, pObj) )
Vec_IntPush( vNodes, Mig_ObjId(pObj) );
return vNodes;
}
Abc_Obj_t * Mpm_ManGetAbcNode( Abc_Ntk_t * pNtk, Vec_Int_t * vCopy, int iMigLit )
{
Abc_Obj_t * pObj;
int iObjId = Vec_IntEntry( vCopy, iMigLit );
if ( iObjId >= 0 )
return Abc_NtkObj( pNtk, iObjId );
iObjId = Vec_IntEntry( vCopy, Abc_LitNot(iMigLit) );
assert( iObjId >= 0 );
pObj = Abc_NtkCreateNodeInv( pNtk, Abc_NtkObj(pNtk, iObjId) );
Vec_IntWriteEntry( vCopy, iMigLit, Abc_ObjId(pObj) );
return pObj;
}
Abc_Ntk_t * Mpm_ManDeriveMappedAbcNtk( Mpm_Man_t * p, Mio_Library_t * pMio )
{
Abc_Ntk_t * pNtk;
Vec_Ptr_t * vNpnGatesMio;
Vec_Int_t * vNodes, * vCopy;
Abc_Obj_t * pObj, * pFanin;
Mig_Obj_t * pNode;
Mpm_Cut_t * pCutBest;
int i, k, iNode, iMigLit, fCompl;
// find mapping of SCL cells into MIO cells
vNpnGatesMio = Mpm_ManFindCells( pMio, (SC_Lib *)p->pPars->pScl, p->vGateNpnConfig );
// create mapping for each phase of each node
vCopy = Vec_IntStartFull( 2 * Mig_ManObjNum(p->pMig) );
// get internal nodes
vNodes = Mpm_ManFindMappedNodes( p );
// start the network
pNtk = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_MAP, 1 );
pNtk->pName = Extra_UtilStrsav( p->pMig->pName );
pNtk->pManFunc = pMio;
// create primary inputs
Mig_ManForEachCi( p->pMig, pNode, i )
{
pObj = Abc_NtkCreatePi(pNtk);
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( Mig_ObjId(pNode), 0 ), Abc_ObjId(pObj) );
}
Abc_NtkAddDummyPiNames( pNtk );
// create constant nodes
pObj = Abc_NtkCreateNodeConst0(pNtk);
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( 0, 0 ), Abc_ObjId(pObj) );
pObj = Abc_NtkCreateNodeConst1(pNtk);
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( 0, 1 ), Abc_ObjId(pObj) );
// create internal nodes
Vec_IntForEachEntry( vNodes, iNode, i )
{
pNode = Mig_ManObj( p->pMig, iNode );
pCutBest = Mpm_ObjCutBestP( p, pNode );
pObj = Abc_NtkCreateNode( pNtk );
pObj->pData = Vec_PtrEntry( vNpnGatesMio, Abc_Lit2Var(pCutBest->iFunc) );
fCompl = Abc_LitIsCompl(pCutBest->iFunc);
Mpm_CutForEachLeafLit( pCutBest, iMigLit, k )
{
pFanin = Mpm_ManGetAbcNode( pNtk, vCopy, iMigLit );
Abc_ObjAddFanin( pObj, pFanin );
}
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( iNode, fCompl ), Abc_ObjId(pObj) );
}
// create primary outputs
Mig_ManForEachCo( p->pMig, pNode, i )
{
pObj = Abc_NtkCreatePo(pNtk);
pFanin = Mpm_ManGetAbcNode( pNtk, vCopy, Mig_ObjFaninLit(pNode, 0) );
Abc_ObjAddFanin( pObj, pFanin );
}
Abc_NtkAddDummyPoNames( pNtk );
// clean up
Vec_PtrFree( vNpnGatesMio );
Vec_IntFree( vNodes );
Vec_IntFree( vCopy );
return pNtk;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Mpm_ManPerformCellMapping( Mig_Man_t * pMig, Mpm_Par_t * pPars, Mio_Library_t * pMio )
{
Abc_Ntk_t * pNew;
Mpm_Man_t * p;
assert( pPars->fMap4Gates );
p = Mpm_ManStart( pMig, pPars );
if ( p->pPars->fVerbose )
Mpm_ManPrintStatsInit( p );
p->vGateNpnConfig = Mpm_ManFindDsdMatches( p, p->pPars->pScl, &p->vNpnCosts );
Mpm_ManPrepare( p );
Mpm_ManPerform( p );
if ( p->pPars->fVerbose )
Mpm_ManPrintStats( p );
pNew = Mpm_ManDeriveMappedAbcNtk( p, pMio );
Mpm_ManStop( p );
return pNew;
}
Abc_Ntk_t * Mpm_ManCellMapping( Gia_Man_t * pGia, Mpm_Par_t * pPars, void * pMio )
{
Mig_Man_t * p;
Abc_Ntk_t * pNew;
assert( pMio != NULL );
assert( pPars->pLib->LutMax <= MPM_VAR_MAX );
assert( pPars->nNumCuts <= MPM_CUT_MAX );
if ( pPars->fUseGates )
{
pGia = Gia_ManDupMuxes( pGia );
p = Mig_ManCreate( pGia );
Gia_ManStop( pGia );
}
else
p = Mig_ManCreate( pGia );
pNew = Mpm_ManPerformCellMapping( p, pPars, (Mio_Library_t *)pMio );
Mig_ManStop( p );
return pNew;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END
src/map/mpm/mpmInt.h
......@@ -101,10 +101,10 @@ struct Mpm_Man_t_
int nTruWords; // words in the truth table
Mpm_LibLut_t * pLibLut; // LUT library
// mapping attributes
int GloRequired; // global arrival time
int GloArea; // total area
int GloEdge; // total edge
int fMainRun; // after preprocessing is finished
int GloRequired; // global arrival time
word GloArea; // total area
word GloEdge; // total edge
// cut management
Mmr_Step_t * pManCuts; // cut memory
// temporary cut storage
......@@ -140,6 +140,8 @@ struct Mpm_Man_t_
Vec_Int_t * vMap2Perm; // maps number into its permutation
unsigned uPermMask[3];
unsigned uComplMask[3];
Vec_Int_t * vGateNpnConfig;
Vec_Int_t * vNpnCosts; // area cost of each NPN class
// mapping attributes
Vec_Int_t vCutBests; // cut best
Vec_Int_t vCutLists; // cut list
......@@ -152,6 +154,7 @@ struct Mpm_Man_t_
Vec_Int_t vEdges; // edge
int nCountDsd[600];
int nNonDsd;
int nNoMatch;
// statistics
int nCutsMerged;
int nCutsMergedAll;
......@@ -218,6 +221,8 @@ static inline void Mpm_VarsSwap( int * V2P, int * P2V, int iVar, int jVar
// iterators over cut leaves
#define Mpm_CutForEachLeafId( pCut, iLeafId, i ) \
for ( i = 0; i < (int)pCut->nLeaves && ((iLeafId = Abc_Lit2Var(pCut->pLeaves[i])), 1); i++ )
#define Mpm_CutForEachLeafLit( pCut, iLeafLit, i ) \
for ( i = 0; i < (int)pCut->nLeaves && ((iLeafLit = pCut->pLeaves[i]), 1); i++ )
#define Mpm_CutForEachLeaf( p, pCut, pLeaf, i ) \
for ( i = 0; i < (int)pCut->nLeaves && (pLeaf = Mig_ManObj(p, Abc_Lit2Var(pCut->pLeaves[i]))); i++ )
......@@ -238,7 +243,10 @@ extern void Mpm_ManPrintDsdStats( Mpm_Man_t * p );
extern void Mpm_ManPrintPerm( unsigned s );
extern void Mpm_ManPrecomputePerms( Mpm_Man_t * p );
extern word Mpm_CutTruthFromDsd( Mpm_Man_t * pMan, Mpm_Cut_t * pCut, int iDsdLit );
extern int Mpm_CutCheckDsd6( Mpm_Man_t * p, word t );
extern int Mpm_CutComputeDsd6( Mpm_Man_t * p, Mpm_Cut_t * pCut, Mpm_Cut_t * pCut0, Mpm_Cut_t * pCut1, Mpm_Cut_t * pCutC, int fCompl0, int fCompl1, int fComplC, int Type );
/*=== mpmGates.c ===========================================================*/
extern Vec_Int_t * Mpm_ManFindDsdMatches( Mpm_Man_t * p, void * pScl, Vec_Int_t ** pvNpnCosts );
/*=== mpmLib.c ===========================================================*/
extern Mpm_LibLut_t * Mpm_LibLutSetSimple( int nLutSize );
extern void Mpm_LibLutFree( Mpm_LibLut_t * pLib );
......
src/map/mpm/mpmMan.c
......@@ -138,6 +138,8 @@ void Mpm_ManStop( Mpm_Man_t * p )
Vec_IntFree( p->pHash->vData );
Hsh_IntManStop( p->pHash );
}
Vec_IntFreeP( &p->vNpnCosts );
Vec_IntFreeP( &p->vGateNpnConfig );
Vec_PtrFree( p->vTemp );
Mmr_StepStop( p->pManCuts );
ABC_FREE( p->vObjPresUsed.pArray );
......
src/map/mpm/mpmMap.c
......@@ -158,6 +158,8 @@ static inline int Mpm_CutGetArea( Mpm_Man_t * p, Mpm_Cut_t * pCut )
return MPM_UNIT_AREA * p->pDsd6[Abc_Lit2Var(pCut->iFunc)].nClauses;
if ( p->pPars->fMap4Aig )
return MPM_UNIT_AREA * p->pDsd6[Abc_Lit2Var(pCut->iFunc)].nAnds;
if ( p->pPars->fMap4Gates )
return MPM_UNIT_AREA * Vec_IntEntry( p->vNpnCosts, Abc_Lit2Var(pCut->iFunc) );
return p->pLibLut->pLutAreas[pCut->nLeaves];
}
static inline word Mpm_CutGetSign( Mpm_Cut_t * pCut )
......
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